JPH038459U - - Google Patents

Info

Publication number
JPH038459U
JPH038459U JP6834789U JP6834789U JPH038459U JP H038459 U JPH038459 U JP H038459U JP 6834789 U JP6834789 U JP 6834789U JP 6834789 U JP6834789 U JP 6834789U JP H038459 U JPH038459 U JP H038459U
Authority
JP
Japan
Prior art keywords
led element
lead frame
wire
led
tip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6834789U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP6834789U priority Critical patent/JPH038459U/ja
Publication of JPH038459U publication Critical patent/JPH038459U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch

Description

【図面の簡単な説明】
第１図Ａ，Ｂは本考案の一実施例を示す平面図
及び正面断面図、第２図は他の実施例を示す平面
図、第３図は従来例を示す平面図及び正面断面図
、第４図は他の従来例を示す平面図、第５図は更
に他の従来例を示す平面図である。 １……カソード側リードフレーム、１ａ……ダ
イボンドエリア、２……アノード側リードフレー
ム、３……ＬＥＤ素子、４……ワイヤ、５……樹
脂、６……溝。

Claims (1)

    【実用新案登録請求の範囲】
  1. ＬＥＤ素子が先端部に搭載された一方のリード
    フレームと、このＬＥＤ素子と先端部がワイヤで
    ボンデイングされた他方のリードフレームとをそ
    の先端部同士を対向させて配置し、前記ＬＥＤ素
    子及び前記ワイヤを含む両リードフレームの先端
    部を樹脂で一体的にモールドした構造のＬＥＤラ
    ンプにおいて、前記モールド樹脂内にあつて、前
    記リードフレームＬＥＤ素子搭載部分の前のフレ
    ーム表面に１個又は複数個の溝を形成したことを
    特徴とするＬＥＤランプ。
JP6834789U 1989-06-12 1989-06-12 Pending JPH038459U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6834789U JPH038459U (ja) 1989-06-12 1989-06-12

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6834789U JPH038459U (ja) 1989-06-12 1989-06-12

Publications (1)

Publication Number Publication Date
JPH038459U true JPH038459U (ja) 1991-01-28

Family

ID=31602707

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6834789U Pending JPH038459U (ja) 1989-06-12 1989-06-12

Country Status (1)

Country Link
JP (1) JPH038459U (ja)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009135379A (ja) * 2007-11-29 2009-06-18 Seoul Semiconductor Co Ltd 防湿ｌｅｄパッケージ
JP2011505689A (ja) * 2007-12-03 2011-02-24 ソウル セミコンダクター カンパニー リミテッド スリム型ｌｅｄパッケージ
JP2011066144A (ja) * 2009-09-16 2011-03-31 Dainippon Printing Co Ltd Ｌｅｄ用リードフレームまたは基板、半導体装置、およびｌｅｄ用リードフレームまたは基板の製造方法
JP2011228687A (ja) * 2010-03-30 2011-11-10 Dainippon Printing Co Ltd Ｌｅｄ用リードフレームまたは基板、半導体装置、およびｌｅｄ用リードフレームまたは基板の製造方法
JP2012028630A (ja) * 2010-07-26 2012-02-09 Dainippon Printing Co Ltd Ｌｅｄ用リードフレームまたは基板およびその製造方法、ならびに半導体装置およびその製造方法
JP2012039162A (ja) * 2007-01-24 2012-02-23 Cree Inc 固体発光デバイス用のリード・フレーム・ベースのパッケージと固体発光デバイス用のリード・フレーム・ベースのパッケージを形成する方法
JP2012114286A (ja) * 2010-11-25 2012-06-14 Toshiba Corp Ｌｅｄパッケージ
JP2013089834A (ja) * 2011-10-20 2013-05-13 Nichia Chem Ind Ltd 発光装置
JP2017076806A (ja) * 2016-11-28 2017-04-20 大日本印刷株式会社 樹脂付リードフレーム、リードフレーム、半導体装置および樹脂付リードフレームの製造方法

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8941134B2 (en) 2006-07-13 2015-01-27 Cree, Inc. Leadframe-based packages for solid state light emitting devices having heat dissipating regions in packaging
JP2012039162A (ja) * 2007-01-24 2012-02-23 Cree Inc 固体発光デバイス用のリード・フレーム・ベースのパッケージと固体発光デバイス用のリード・フレーム・ベースのパッケージを形成する方法
JP2009135379A (ja) * 2007-11-29 2009-06-18 Seoul Semiconductor Co Ltd 防湿ｌｅｄパッケージ
JP2011505689A (ja) * 2007-12-03 2011-02-24 ソウル セミコンダクター カンパニー リミテッド スリム型ｌｅｄパッケージ
JP2011066144A (ja) * 2009-09-16 2011-03-31 Dainippon Printing Co Ltd Ｌｅｄ用リードフレームまたは基板、半導体装置、およびｌｅｄ用リードフレームまたは基板の製造方法
JP2011228687A (ja) * 2010-03-30 2011-11-10 Dainippon Printing Co Ltd Ｌｅｄ用リードフレームまたは基板、半導体装置、およびｌｅｄ用リードフレームまたは基板の製造方法
JP2012028630A (ja) * 2010-07-26 2012-02-09 Dainippon Printing Co Ltd Ｌｅｄ用リードフレームまたは基板およびその製造方法、ならびに半導体装置およびその製造方法
JP2012114286A (ja) * 2010-11-25 2012-06-14 Toshiba Corp Ｌｅｄパッケージ
JP2013089834A (ja) * 2011-10-20 2013-05-13 Nichia Chem Ind Ltd 発光装置
JP2017076806A (ja) * 2016-11-28 2017-04-20 大日本印刷株式会社 樹脂付リードフレーム、リードフレーム、半導体装置および樹脂付リードフレームの製造方法

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