JPH038389U - - Google Patents
Info
- Publication number
- JPH038389U JPH038389U JP6844589U JP6844589U JPH038389U JP H038389 U JPH038389 U JP H038389U JP 6844589 U JP6844589 U JP 6844589U JP 6844589 U JP6844589 U JP 6844589U JP H038389 U JPH038389 U JP H038389U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- data
- display
- circuit
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Digital Computer Display Output (AREA)
Description
第１図は本考案の一実施例に係る表示制御装置
のブロツク図、第２図はメモリの構成の概要説明
図、第３図は第１図の構成の動作を説明するため
のタイミングチヤート、第４図は従来の表示制御
装置のブロツク図である。
２……第１のＶＲＡＭ、４……第２のＶＲＡＭ
、６……ＣＰＵ、８……プログラムＲＯＭ、１０
……割込コントローラ、１２……タイマーコント
ローラ、１４……Ｉ／Ｏコントローラ、１６……
キーボード、１８……キヤラクタフオントＲＯＭ
、２０……アトリビユートコントロール、２２…
…ＣＲＴ駆動回路、２４……ＣＲＴ、２６……ク
ロツク回路、２８……表示専用ＬＳＩ、３０……
アドレス切換、３２……制御信号切換、３４……
デマルチプレツクサ、３６……ナンド回路、３８
……フリツプフロツプ、４０……アドレスバス、
４２……データバス、４４……ＶＲＡＭアドレス
、４６……ラスタアドレス、４８……ラスタカウ
ンタ、５０……制御回路。
FIG. 1 is a block diagram of a display control device according to an embodiment of the present invention, FIG. 2 is a schematic explanatory diagram of a memory configuration, and FIG. 3 is a timing chart for explaining the operation of the configuration of FIG. 1. FIG. 4 is a block diagram of a conventional display control device. 2...First VRAM, 4...Second VRAM
, 6... CPU, 8... Program ROM, 10
...Interrupt controller, 12...Timer controller, 14...I/O controller, 16...
Keyboard, 18...Character font ROM
, 20... attribute control, 22...
...CRT drive circuit, 24...CRT, 26...clock circuit, 28...display-only LSI, 30...
Address switching, 32... Control signal switching, 34...
Demultiplexer, 36... NAND circuit, 38
...flipflop, 40...address bus,
42...Data bus, 44...VRAM address, 46...Raster address, 48...Raster counter, 50...Control circuit.
Claims (1)
データの先頭アドレスを付加すると共に、第２の
メモリに、表示に必要なアトリビユートデータと
表示制御データとを書き込む回路と、 データの表示期間に第２のメモリからアトリビ
ユートデータを読み出し、このアトリビユートデ
ータに基づいて第１のメモリから読み出した表示
データを表示させる回路と、 第１のメモリから読み出した次の表示データの
先頭アドレスを第１のメモリと第２のメモリにア
ドレスとして与える回路と、 ブランキング期間に第２メモリから読み出した
表示制御データにより第１のメモリと第２のメモ
リを制御する回路と を備えることを特徴とする表示制御装置。[Claims for Utility Model Registration] In addition to the display data, the first address of the next display data is added to the first memory, and the attribute data and display control data necessary for display are added to the second memory. A circuit that reads attribute data from a second memory during a data display period and displays display data read from a first memory based on this attribute data; A circuit that provides the first address of the read next display data as an address to the first memory and the second memory, and a circuit that provides the first memory and the second memory with the display control data read from the second memory during the blanking period. A display control device comprising: a control circuit;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6844589U JPH038389U (en) | 1989-06-12 | 1989-06-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6844589U JPH038389U (en) | 1989-06-12 | 1989-06-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH038389U true JPH038389U (en) | 1991-01-25 |
Family
ID=31602896
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6844589U Pending JPH038389U (en) | 1989-06-12 | 1989-06-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH038389U (en) |
-
1989
- 1989-06-12 JP JP6844589U patent/JPH038389U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS644193B2 (en) | ||
| JPH0377530B2 (en) | ||
| JPS62257524A (en) | Display character output controller | |
| JPH038389U (en) | ||
| JPH0522933B2 (en) | ||
| JPH0344735U (en) | ||
| JPH0720833A (en) | Graphics computer | |
| KR900001527Y1 (en) | Crt display control circuit | |
| JPH0227677B2 (en) | ||
| JPS6316331U (en) | ||
| JPS59152488A (en) | Display controller | |
| JPS62148992A (en) | Display controller | |
| JPS5946681A (en) | Pattern writing system for user's definition ram | |
| JPH03126991A (en) | Display system for information processor | |
| JPS63179556U (en) | ||
| JPS61145991U (en) | ||
| JPS59187838U (en) | word processor | |
| JPS6067991A (en) | Scrolling of display screen | |
| JPS639647U (en) | ||
| JPS62146223U (en) | ||
| JPS6368390U (en) | ||
| JPS61204258U (en) | ||
| JPS6026086U (en) | CRT device | |
| JPS6246494U (en) | ||
| JPS5927911B2 (en) | Display device control method |