JPH0382218A - Two-way buffer - Google Patents

Abstract

PURPOSE:To attain the control of a current flowing to a bus line and a through- current and to reduce the power consumption by acting a field effect transistor(TR) connected between the bus line and a power supply as a pullup resistor in an input state, and releasing its function in the output state. CONSTITUTION:A TR TP2 is turned on in the high impedance state as a pullup resistor, then a level of a bus line BUL 1 is fixed by the resistor and a through- current flowing from a TR TP4 of an input buffer 1 to a TR TN 4 is prevented. Moreover, the TR TP 2 is turned off in the output state to release the resistance function, then a current flowing from the TR TP2 of an output buffer 2 to a TR TN 3 via the bus line BUL 1 is prevented. Thus, the through-current and the current flowing to the bus line are decreased and the power consumption of the buffer is reduced.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figure 6) Means for solving the problems to be solved by the invention (Figure 1) Working examples First embodiment (Figures 2 and 3) Second embodiment (Figures 4 and 5) Effects of the invention [Summary] Bidirectionality of inputting and outputting signals by selecting a bidirectional buffer, especially a human output buffer Regarding buffer improvements, we aim to reduce power consumption by reducing the through current in the input buffer and the current flowing into the bus line without electrically isolating the output buffer or fixing the bus line to a certain level. The first buffer has an input buffer, an output buffer and a p
A channel-type field effect transistor is provided, and the field effect transistor is provided between a power supply and a bus line that connects a connection point between the output of the input buffer and the output buffer and an input/output terminal, and a gate of the effect transistor is controlled by a control signal of the output buffer, and the second buffer includes an input buffer, an output buffer and an n
A channel-type field effect transistor is provided, and the field effect transistor is provided between a power source and a bus line that connects the connection point of the input of the input buffer sofa and the output of the output buffer and the input/output terminal. The gate of the effect transistor is controlled by the control signal of the output buffer.

[Industrial application field]

The present invention relates to a bidirectional buffer, and more specifically, to an improvement in a bidirectional buffer that selects an input/output buffer and inputs/outputs a signal.

In recent years, I10 interfaces using bidirectional buffers have been widely used in various signal processing devices.

Therefore, there is a need for a bidirectional buffer that can reduce wasteful current flowing through input/output buffers and bus lines, thereby reducing power consumption.

[Conventional technology]

FIGS. 6(a) and 6(b) are configuration diagrams of a conventional dual-copy buffer.

FIG. 1A shows a configuration diagram of a bidirectional bus buffer that electrically separates input and output signals.

In the figure (a), the bidirectional bus buffer as seen in Japanese Patent Application Laid-Open No. 62-179219 has a manual buffer 11. Output buffer 12. P-channel MOS transistor TP7
n-channel MO3) from transistor Tn7. The function of the buffer is that it is in an output state when the input/output selection signal OE is at the rH level, and becomes an input state when it is at the "high" level.

In other words, when the level is OE-rH, the transistor TP7
performs rOFFJ operation and electrically disconnects the input buffer 11 from the bus line BUL3. At this time, since the transistor TN7 performs an "ON" operation, the input buffer 11 is fixed at the "L" level. This results in
Wasteful power consumption in the input buffer 11 in the output state is suppressed.

Also, at ○E−rLJ level, transistor TP7 is “
ON” operation and connects the input buffer 11 to the bus line BUL.
Connected to 3. At this time, it is in a high impedance state from the time it enters the manual state until the input signal is supplied.

FIG. 5B shows a configuration diagram of a bidirectional buffer that separates input and output functions. This is different from the bidirectional 1III bus buffer shown in FIG. is always electrically connected to the bus line BUL4.

This bidirectional buffer consists of an input buffer 13 which is supplied from a p-channel MO3) transistor TPO, an n-channel MOS transistor TN9, and a p-channel MOS transistor TP8. It includes an output buffer 14 made up of an n-channel MOS transistor TN8 and a control circuit 15, and either a pull-amplifier resistor Rpu or a pull-down resistor Rpd.

The function of the buffer is that the manual selection signal C3°C3 is rH.
” level, it is in the input state, and when it is at the “L” level, it is in the output state.

The pull-up resistor Rpu is composed of a p-channel MOS transistor TPIO, and its drain is connected to the power supply VDD, its gate is connected to the power supply SS, and its source is connected to the bus line BUL4. Also, pull-down Rp
u consists of an n-channel MOS transistor TNIO, the drain of which is connected to the bus line BUL4, the gate connected to the power supply VDD, and the source connected to the voltage avss. This pull amplifier and pull-down resistor "IT" are for preventing a through current flowing from the transistor TP9 of the input bath sofa to the transistor TN9 when the impedance is high. This suppresses wasteful power consumption in the manual buffer 13 during high impedance.

[Problem to be solved by the invention]

1. According to the bidirectional bus buffer shown in FIG. 6(a), the input buffer 11 and the bus line BUL3 are electrically separated by the transistor TP7 in the output state.

For this reason, in modern microcomputer bus circuits, the buffer cannot be used as a monitor function for inputting the output of the output buffer 12 again.

Also, in the high impedance state, the transistor T
Since N7 operates rOFF, 1, input buffer 1
1 may be in a floating state, and a through current may flow through the buffer 11, resulting in wasteful power consumption.

Furthermore, if the input signal is supplied, the transistor TP
There is a problem in that the rON of T and the equivalent resistance during operation (approximately 50 to 100 Ω) cause a signal transmission delay.

In addition, according to the bidirectional positive buffer shown in FIG. 4B, a pull-up resistor Rpu or a pull-down resistor Rpd is fixedly connected to the bus line BUL4.

These resistances Rpu and Rpd are MOS transistors T
PIO and TNIO are always operated rON and used.

Therefore, in FIG. 6(b), the bus line BUL4
When reaches the level determined by the resistor Rpu or Rpd, a steady current 1bp flows from the pull-up resistor Rpu to the transistor TN8 of the output buffer 14, or a current 1bn flows from the transistor TP8 of the buffer 14 to the pull-down resistor. Flows to Rpd.

As a result, when switching the input/output state, the bus line B
There is a problem that UL4 causes unnecessary power consumption.

The present invention was created in view of the problems of the conventional example, and eliminates the through current in the input buffer and the bus line without electrically separating the input/output buffer or fixing the bus line to a constant level. The purpose of the present invention is to provide a bidirectional buffer that can reduce the current flowing into the device and reduce power consumption.

[Means to solve the problem]

FIGS. 1(a) and 1(b) show a principle diagram of the bidirectional buffer of the present invention.

The first buffer is input buffer 1.1 as shown in FIG. An output buffer 2 and a p-channel field effect transistor TPI are provided, and the field effect transistor TPI is connected to a bus line connecting a connection point Y of the input of the input buffer l and the output of the output buffer 2 to an input/output point X. The gate G of the field effect transistor TPI, which is provided between BUL and the power supply VDD, is controlled by the control signal C of the output buffer 2, and the second buffer is configured as shown in FIG. As shown in the input buffer 3. An output buffer 4 and an n-channel field effect transistor TNI are provided, and the field effect transistor TNI is connected to a bus line connecting a connection point Y of the input of the input buffer 3 and the output of the output buffer 4 to the input/output terminal X. The gate of the field effect transistor TNI, which is provided between BUL and the power supply vSS, is controlled by the control signal C of the output buffer 4, thereby achieving the above object.

[Effect]

According to the first bidirectional buffer of the invention, the gate of the field effect transistor TPI is controlled by the control signal C of the output buffer 2.

That is, when the control signal C changes from the rH level to the "L" level, the buffer changes from the output state to the input state. At the same time, the transistor TPI becomes rON and operates.
Functions as a pull-up resistor. Therefore, the level of the bus line is fixed, and it is possible to prevent a through current flowing through the input buffer l as in the conventional case.

Further, when the control signal C changes from the "L" level to rH, the buffer changes from the input state to the output state.

At the same time, the transistor TPI enters the rOFFJ operation, and its function as a pull-up resistor is canceled. Therefore, it is possible to prevent current from flowing into the output buffer 2 from the transistor TPI via the bus line BUL as in the conventional case.

Furthermore, according to the second bidirectional buffer, the gate of the field effect transistor TNI is controlled by the control signal C of the output buffer 4.

That is, similarly to the first buffer, the first signal C is "
When the level changes from "L" to "rH", the state changes from output to input. At the same time, the transistor TNI becomes "ON" and functions as a pull-down resistor. Therefore, the level of the bus line BUL is fixed, and it is possible to prevent a through current flowing through the input buffer 2 as in the conventional case.

Further, when the control signal C changes from rH to "L" level, the state changes from input to output. Along with this, the transistor TNI
becomes "○FFJFF" and the function of the pull-down resistor is canceled. Therefore, it becomes possible to prevent the current from flowing from the output buffer 4 to the transistor TNI via the bus line BUL as in the conventional case.

This makes it possible to reduce the through current and the current flowing into the bus line, making it possible to reduce power consumption.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

2 to 4 are diagrams illustrating a bidirectional buffer according to an embodiment of the present invention.

(i) Description of the first embodiment FIG. 2 shows a block diagram of a bidirectional buffer according to the first embodiment of the present invention.

In the figure, 1 is an input buffer, which is a p-channel MO
S) Powered by transistor TP4 and n-channel M○S transistor TN4. Input buffer 1 is bus line BULI
It is connected to the bus line BUL1 and inputs signal information of the bus line BUL1. 2 is an output buffer, P channel M
OS) Transistor TP3. This is a 3-state output buffer output from the n-channel MO3 transistor TN3 and the control circuit 2a. Output buffer 4 is bus line BU
Connected to L2.

The control circuit 2a receives an input selection signal CI.

Bus line BUL 1 is output based on C1.

It is used to set the input state and high impedance state, and to control the gate of the P-channel MOS transistor TP2. Note that an example of the configuration is shown in FIG.

TP2 is a p-channel MOS transistor, and is connected between the power supply vDp and the bus line BUL1.

The transistor TP2 has an input selection signal C1 of rH, →
When it goes to "L" level, "○FFJ" becomes "ON" operation and functions as a pull-up resistor. As a result, the level of the bus line BULI is fixed.

Also, when the signal C changes from "L" to rH, "ON" → rO
It becomes FF operation and its function as a pull-up resistor is canceled. As a result, the level of the bus line BULI is
The level depends on the output level.

FIG. 3 is a configuration diagram of a control circuit according to a seventh embodiment of the present invention.

In the figure, the control circuit 2a operates from a two-man NAND circuit 21 and a two-man NOR circuit 22 to the inverter (2). The inverter INI inverts the inverted input/output selection signal C and outputs the inverted input/output selection signal C.

A two-man NAND circuit 21 controls the gate of the transistor TP3 based on output data and an input/output selection signal TCl. A two-man NOR circuit 22 controls the gate of the transistor TN3 based on the output data and the input/output selection signal CI.

Next, the operation of the first bidirectional buffer will be explained.

(2) Operation from output state to input state First, it is assumed that the buffer is in the output state where, for example, the rH level is input to the output ○UTI.

At this time, the input/output selection signal C1 changes from rH, level to “L”.
” level, the transistor TP3 of the output buffer 2 changes from “ON” to rOFF.

Move to action. Further, the transistor TN3 of the output buffer 2 continues the rOFFJ operation.

As a result, the X1 point of the bus line BULL shifts from the "H" level to the high impedance state. At this time, the transistor TP2 shifts from "○FFJ" to "ON" operation and functions as a pull-up resistor Rpu.゛Therefore,
The level of bus line BUL 1 is the pull-up resistor Rpu
Fixed by

From this, the input level of input buffer 1 is fixed,
To move to an input state without going into a floating state as in the conventional case. This prevents a through current from flowing from transistor TP4 to TN4 in the high impedance state as in the conventional case.

■Operation from input state to output state In this case as well, assuming that the rH level is added to the output ○UTI, the selection signal C1 shifts from "L" to "H" level, causing transistor TP3 is rO
FFJ → Shifts to “ON” operation. Also, the transistor TN3 continues the FFJ operation.

As a result, the X1 point of the bus line BULL shifts from the high impedance state to the "H" level. At this time, the transistor TP2 shifts from rONJ to rOFFJ operation, and its function as a pull-up resistor Rpu is canceled.

Therefore, the level of bus line BUL 1 is output 0UT.
The level depends on the "H" level of I. This eliminates the current flowing from the pull amplifier resistor RρU to the transistor TN3 via the bus line BULL as in the conventional case.

Note that Table 1 shows the operational relationship including the case where the "L" level is input to the output ○UTI.

(Left below) Table 1 In this way, according to the first embodiment of the present invention, the transistor TP2 is turned on in the high impedance state.
'' to function as a pull amplifier resistor Rpu.

Therefore, the level of the bus line BULI is 3 and the resistance Rp
This makes it possible to prevent a through-flow from flowing from the transistor TP4 to the transistor TN4 of the conventional manual buffer 1.

Also, in the output state, the transistor TP2 is turned to rOFFJ.
The resistor function is released by operating the resistor. For this reason,
It becomes possible to prevent current from flowing into the transistor TN3 from the transistor TP2 of the output buffer 2 via the bus line BULI, as in the conventional case.

Thereby, the through current and the current flowing into the bus line can be reduced. This makes it possible to reduce the power consumption of the buffer.

(ii) Description of the second embodiment FIG. 4 is a block diagram of the bidirectional buffer of the second embodiment.

In the figure, the difference from the first embodiment is that in the second embodiment, there is n between the bus line BUL2 and the voltage 1flVss.
Channel MO5) transistor TN2 is connected, and the transistor TN2 is connected to the control circuit 1i of the output buffer 4.
It is gate-controlled by the manual selection signal C2 of '34a. Therefore, transistors TP5 . TP6 is TP3.
TP4 and TN3. Since it is the same as TN4, the explanation will be omitted.

FIG. 5 is a configuration diagram of a control circuit according to a second embodiment of the present invention.

In the figure, the difference from the first embodiment is that in the second embodiment, the input selection signal C2 is input directly to the gate of the transistor TN2 without passing through the inverter IN2.

Next, the operation of the second bidirectional buffer will be explained.

(2) Operation from output state to input state First, as in the first embodiment, it is assumed that the output state is in the output state where the "H" level is input to the output 0UT2.

At this time, the input/output selection signal C2 changes from the "L" level to the "H" level.
” level, the transistor TP5 of the output buffer 4 changes from “ON” to rOFFJ operation. Further, the transistor TN5 of the output buffer 4 performs an "OFF" operation.

As a result, the point X2 of the bus line BUL2 shifts from the "H" level to the high impedance state. At this time, the transistor TN2 shifts from "rOFF" to "ON" operation and functions as a pull-down resistor Rpd. Therefore,
The level of bus line BUL2 is fixed by pull-down resistor Rpd. Therefore, as in the first embodiment, the input level of the input buffer 3 is fixed, and the input buffer 3 enters an input state instead of being in a floating state as in the conventional case. Therefore, unlike the conventional input buffer 3, the transistor TP
Through current flowing from TN6 to TN6 is prevented.

■Operation from input state to output state First, as the input/output selection signal C2 shifts from rH to "LJ level," transistor TP5 turns "OFF".
”→Moves to “ON” operation. Also, the transistor TN
5 continues the rOFFJ operation.

As a result, the X2 point of bus line [3UL1 is high
The impedance state shifts to the r[(J level. At this time, the transistor TN2 shifts from "ON" to "○FFJ" operation, and the function as the pull-down resistor Rpd is canceled.

Therefore, the level of the bus line BUL2 is the output 0UT2.
The level depends on the "H" level of. As a result, the transistor TP5 of the output buffer 4 as in the conventional example
There is no current flowing into the transistor TN2 via the bus line BUL2.

Note that Table 2 shows the operational relationship including the case where "L" level is input to the output 0UT2.

Table 2 Thus, according to the second embodiment of the present invention, transistor TN2 is turned to rON during high impedance state.
'' to function as a pull-down resistor Rpd.

Therefore, the level of the bus line BUL2 becomes higher than the level of the resistor Rpd.
It is possible to prevent the through current flowing from the transistor TP6 to the transistor TN6 of the input buffer 3 as in the conventional case.

Also, in the output state, the transistor TN2 is turned to rOFFJ.
The resistor function is released by operating the resistor. For this reason,
It becomes possible to prevent current from flowing into the transistor TN2 from the transistor TP5 of the output buffer 4 via the bus line BUL2 as in the conventional case.

As a result, as in the first embodiment, it is possible to reduce the through current flowing into the human cover sofa and the current flowing into the bus line. This makes it possible to reduce the power consumption of the buffer.

Also, in the bus circuit of a microcomputer, the output buffer 12
There is no problem when using it as a monitor function, such as inputting the output output to again.

〔Effect of the invention〕

As explained above, according to the present invention, the field effect transistor connected between the bus line and the power supply can function as a pull-amp resistor or pull-down resistor in the manual state, and can function as a pull-amp resistor or pull-down resistor in the output state. As a result, the through current in the in-cover sofa and the current flowing into the bus line can be suppressed, making it possible to reduce power consumption.

[Brief explanation of drawings]

FIG. 1 is a principle diagram of a bidirectional buffer of the present invention, FIG. 2 is a block diagram of a bidirectional buffer of a first embodiment of the present invention, and FIG. 3 is a diagram of a bidirectional buffer of a first embodiment of the present invention. FIG. 4 is a block diagram of a control circuit according to the second embodiment of the present invention; FIG. 5 is a block diagram of a bidirectional buffer according to the second embodiment of the present invention; FIG. Circuit Block Diagram FIG. 6 is a block diagram of a conventional bidirectional buffer. (Explanation of symbols) 1.3...Person cover sofa, 2.4...Output buffer, TPI...P-channel field effect transistor, T
NI...n-channel field effect transistor, BU
L: Bus line, C, C: Control signal.

Claims (2)

[Claims] (1) Input buffer (1), output buffer (2) and p
A channel type field effect transistor (TP1) is provided, and the field effect transistor (TP1) is connected to a connection point (Y) between the input of the input buffer (1) and the output of the output buffer (2), and an input/output terminal (X ) and the bus line (
BUL) and a power supply (VDD), and the gate (G) of the field effect transistor (TP1) is controlled by the control signal (@C@) of the output buffer (2). bidirectional buffer. (2) Input buffer (3), output buffer (4) and n
A channel type field effect transistor (TN1) is provided, and the field effect transistor (TN1) is connected to a connection point (Y) between the input of the input buffer (3) and the output of the output buffer (4), and an input/output terminal (X ) and the bus line (
BUL) and a power supply (VSS), the gate of the field effect transistor (TN1) being controlled by the control signal (C) of the output buffer (4). .