JPH0379950B2 - - Google Patents
Info
- Publication number
- JPH0379950B2 JPH0379950B2 JP15669481A JP15669481A JPH0379950B2 JP H0379950 B2 JPH0379950 B2 JP H0379950B2 JP 15669481 A JP15669481 A JP 15669481A JP 15669481 A JP15669481 A JP 15669481A JP H0379950 B2 JPH0379950 B2 JP H0379950B2
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- transformer
- circuit
- amplifier
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 32
- 238000009499 grossing Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 230000005283 ground state Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Rectifiers (AREA)
- Dc-Dc Converters (AREA)
- Power Conversion In General (AREA)
Description
【発明の詳細な説明】
本発明は、スイツチド・キヤパシタ変成器（以
下、SC変成器と称す）にCNIC回路（current−
inversion negative−impedance conve−rter，
電流反転型負性インピーダンス変換回路）を用い
た平滑回路を接続して構成される集積化可能な電
源回路に関する。Detailed Description of the Invention The present invention provides a switched capacitor transformer (hereinafter referred to as an SC transformer) with a CNIC circuit (current-
inversion negative−impedance conve−rter,
The present invention relates to an integrated power supply circuit configured by connecting a smoothing circuit using a current reversal type negative impedance conversion circuit.
通信システムのデジタル化及びLSI（高密度集
積回路）化に伴い集積化可能なSC変成器を用い
た電源回路が採用されている。 With the digitalization of communication systems and the shift to LSI (high-density integrated circuits), power supply circuits using SC transformers that can be integrated are being adopted.
従来、このSC変成器の出力から直流信号を得
るための平滑回路としては、該変成器の出力に平
滑用蓄電器を並列に接続する構成が周知である。 Conventionally, as a smoothing circuit for obtaining a DC signal from the output of this SC transformer, a configuration in which a smoothing capacitor is connected in parallel to the output of the transformer is well known.
しかしながら、蓄電器のみの平滑回路を用いた
場合、リツプルを低減するためには極めて大容量
の蓄電器が必要となり、小型・軽量化及び集積化
が困難になるという欠点がある。 However, when a smoothing circuit including only a capacitor is used, an extremely large capacity capacitor is required in order to reduce ripples, which has the disadvantage of making it difficult to reduce size, weight, and integration.
本発明の目的は、上述の欠点を除去し小容量の
蓄電器でリツプル電圧を極めて小さくでき同時
に、集積化可能な電源回路を提供することにあ
る。 SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks, to provide a power supply circuit that can extremely reduce ripple voltage with a small-capacity capacitor, and at the same time can be integrated.
本発明の電源回路は、スイツチド・キヤパシタ
変成器を有する電源回路において、一端が前記変
成器の一方の出力端子と接続された第１の蓄電器
と、一端が前記変成器の他方の出力端子と接続さ
れ前記第１の蓄電器と等しい容量値を持つ第２の
蓄電器と、反転入力端子が前記第１の蓄電器の他
端と接続され非反転入力端子が前記第２の蓄電器
の他端と接続された増幅器と、該増幅器の出力端
子と前記反転入力端子との間に接続され第１の抵
抗器と第３の蓄電器との並列接続からなる第１の
並列回路と、前記増幅器の出力端子と前記非反転
入力端子との間に接続され前記第１の並列回路と
等しいインピーダンスを有し第２の抵抗器と第４
の蓄電器との並列接続からなる第２の並列回路と
を備えている。 The power supply circuit of the present invention includes a first capacitor having one end connected to one output terminal of the transformer, and one end connected to the other output terminal of the transformer in a power supply circuit having a switched capacitor transformer. a second capacitor having a capacitance value equal to that of the first capacitor; an inverting input terminal is connected to the other end of the first capacitor, and a non-inverting input terminal is connected to the other end of the second capacitor. an amplifier, a first parallel circuit connected between the output terminal of the amplifier and the inverting input terminal and consisting of a parallel connection of a first resistor and a third capacitor; a second resistor and a fourth resistor connected between the inverting input terminal and having an impedance equal to that of the first parallel circuit;
and a second parallel circuit consisting of a parallel connection with a power storage device.
次に本発明について図面を参照して詳細に説明
する。 Next, the present invention will be explained in detail with reference to the drawings.
第１図は本発明の一実施例を示す構成図であ
る。 FIG. 1 is a block diagram showing an embodiment of the present invention.
図において、入力電源１からの入力電圧Ｅはク
ロツク周波数fcで動作する変成比±ｎ（但し、ｎ
は正の整数または、正の整数分の一）のSC変成
器２に印加され、このSC変成器２の出力と並列
に負荷抵抗器１１が接続される。また、SC変成
器２の出力端子間にはCNIC回路を用いた平滑回
路が接続されている。 In the figure, the input voltage E from the input power supply 1 is the transformation ratio ±n (however, n
is applied to the SC transformer 2 (a positive integer or a fraction of a positive integer), and a load resistor 11 is connected in parallel with the output of the SC transformer 2. Further, a smoothing circuit using a CNIC circuit is connected between the output terminals of the SC transformer 2.
オペアンプを用いて構成したCNIC回路の基本
構成を第３図に示す。 Figure 3 shows the basic configuration of a CNIC circuit constructed using operational amplifiers.
ここで
V1；１〜1′間電位
V2；２〜2′間電位
I1；１からの電流
I2；２からの電流
とすると、V1＝V2、I1＝（Z2／Z1）I2となるこ
とが知られており、Z1＝Z2なるインピーダンスを
実現することでI1＝I2が実現できる。なお、第３
図に示すNIC回路についての詳細は「LINEAR
INTEGRATED NETWORKS Fundamentals」
に記載されている。 Here, V 1 ; potential between 1 and 1' V 2 ; potential between 2 and 2' I 1 ; current from 1 I 2 ; current from 2, then V 1 = V 2 , I 1 = (Z 2 / It is known that Z 1 )I 2 , and I 1 = I 2 can be achieved by realizing an impedance of Z 1 =Z 2 . In addition, the third
For more information about the NIC circuit shown in the figure, see LINEAR
INTEGRATED NETWORKS Fundamentals”
It is described in.
すなわち、SC変成器２の出力端子の一方と増
幅器１０の反転入力端子との間に蓄電器３が接続
されており、また、SC変成器２の出力端子の他
方と増幅器１０の非反転入力端子との間には抵抗
器６と蓄電器７との並列回路が接続されている。
さらに、増幅器１０の出力端子と反転入力端子お
よび非反転入力端子との間には各々抵抗器５と蓄
電器４との並列回路および抵抗器８と蓄電器９と
の並列回路が接続されている。蓄電器３，４，
７，９は直流分をカツトしSC変成器２の出力の
交流成分のみを通す。 That is, the capacitor 3 is connected between one of the output terminals of the SC transformer 2 and the inverting input terminal of the amplifier 10, and the capacitor 3 is connected between the other output terminal of the SC transformer 2 and the non-inverting input terminal of the amplifier 10. A parallel circuit of a resistor 6 and a capacitor 7 is connected between them.
Further, a parallel circuit of a resistor 5 and a capacitor 4 and a parallel circuit of a resistor 8 and a capacitor 9 are connected between the output terminal and the inverting input terminal and the non-inverting input terminal of the amplifier 10, respectively. Electricity storage device 3, 4,
7 and 9 cut the DC component and pass only the AC component of the output of the SC transformer 2.
ここで、クロツク周波数をｆとすると、角周波
数ωc＝2πfであり、
ωc＞１／CpR ωc＞１／CfRf …(1)
とし、増幅器１０の増幅度Ｇ＝∞（無限大）とす
ると、増幅器１０の入力電圧差ΔVはΔV０と
なる。さらに増幅器１０の入力インピーダンスＺ
をＺ＝∞（無限大）とし、蓄電器４および９の容
量値を等しくし、蓄電器３および７の容量値を等
しくすると、増幅器１０の出力電流I1およびI2は
等しく（I1＝I2＝Ｉ）なる。 Here, if the clock frequency is f, the angular frequency ω c =2π f , ω c > 1/CpR ω c > 1/C f R f (1), and the amplification degree G of the amplifier 10 = ∞ ( (infinite), the input voltage difference ΔV of the amplifier 10 becomes ΔV0. Furthermore, the input impedance Z of the amplifier 10
When Z = ∞ (infinity), the capacitance values of capacitors 4 and 9 are made equal, and the capacitance values of capacitors 3 and 7 are made equal, then the output currents I 1 and I 2 of amplifier 10 are equal (I 1 = I 2 =I) becomes.
この結果、増幅器１０の出力とSC変成器２の
各出力端子とに接続されている蓄電器３と４及び
９と７との直列回路には等しい電流Ｉ（＝I1＝I2）
が流れることになり、SC変成器２の各出力端子
は、増幅器１０の出力端に対し交流的に仮想接地
状態となり、抵抗器１１には直流成分のみが供給
される。 As a result, the series circuit of capacitors 3 and 4 and 9 and 7 connected to the output of amplifier 10 and each output terminal of SC transformer 2 has an equal current I (=I 1 =I 2 ).
will flow, and each output terminal of the SC transformer 2 will be in a virtual AC ground state with respect to the output terminal of the amplifier 10, and only a DC component will be supplied to the resistor 11.
第２図ａはクロツク信号波形、同図ｂはSC変
成器の出力側に平滑回路を設けないときの抵抗器
１１の両端の電圧波形、同図ｃは本実施例の抵抗
器１１の両端の電圧波形である。 Figure 2a shows the clock signal waveform, Figure 2b shows the voltage waveform across the resistor 11 when no smoothing circuit is provided on the output side of the SC transformer, and Figure 2c shows the voltage waveform across the resistor 11 in this embodiment. It is a voltage waveform.
このように、SC変成器の出力に負荷と並列に
CNIC回路を用いた平滑回路を接続することによ
り、等価的にSC変成器の交流負荷インピーダン
スを零にすることができ、出力には直流成分のみ
が得られる。 In this way, the output of the SC transformer is connected in parallel with the load.
By connecting a smoothing circuit using a CNIC circuit, the AC load impedance of the SC transformer can be equivalently reduced to zero, and only the DC component is obtained in the output.
以上、本発明には、小容量の蓄電器により回路
を構成でき更にインダクタンス素子を全く使用し
ていないため磁束の発生がなく集積化も容易であ
るという効果がある。 As described above, the present invention has the advantage that the circuit can be constructed using a small-capacity capacitor, and since no inductance element is used at all, no magnetic flux is generated and integration is easy.
第１図は本発明の一実施例を示す構成図、第２
図ａはクロツク信号波形、同図ｂは平滑回路を設
けないときの出力波形および同図ｃは本実施例の
出力波形である。第３図はCNICの基本構成を示
す回路図である。
図において、１……入力電源、２……SC変成
器、３……蓄電器、４……蓄電器、５……抵抗
器、６……抵抗器、７……蓄電器、８……抵抗
器、９……蓄電器、１０……増幅器、１１……抵
抗器。
FIG. 1 is a configuration diagram showing one embodiment of the present invention, and FIG.
Figure a shows the clock signal waveform, figure b shows the output waveform when no smoothing circuit is provided, and figure c shows the output waveform of this embodiment. FIG. 3 is a circuit diagram showing the basic configuration of CNIC. In the figure, 1... Input power supply, 2... SC transformer, 3... Capacitor, 4... Capacitor, 5... Resistor, 6... Resistor, 7... Capacitor, 8... Resistor, 9 ...Condenser, 10...Amplifier, 11...Resistor.
Claims (1)
タ変成器を有する電源回路において、一端が前記
変成器の一方の出力端子と接続された第１の蓄電
器と、一端が前記変成器の他方の出力端子と接続
され前記第１の蓄電器と等しい容量値を持つ第２
の蓄電器と、反転入力端子が前記第１の蓄電器の
他端と接続され非反転入力端子が前記第２の蓄電
器の他端と接続された増幅器と、該増幅器の出力
端子と前記反転入力端子との間に接続され第１の
抵抗器と第３の蓄電器との並列接続からなる第１
の並列回路と、前記増幅器の出力端子と前記非反
転入力端子との間に接続され前記第１の並列回路
と等しいインピーダンスを有し第２の抵抗器と第
４の蓄電器との並列接続からなる第２の並列回路
とを備えたことを特徴とする電源回路。1. In a power supply circuit having a switched capacitor transformer with two output terminals, a first capacitor having one end connected to one output terminal of the transformer, and one end connected to the other output terminal of the transformer. and a second capacitor having a capacitance value equal to that of the first capacitor.
an amplifier whose inverting input terminal is connected to the other end of the first capacitor and whose non-inverting input terminal is connected to the other end of the second capacitor; an output terminal of the amplifier and the inverting input terminal; a first resistor and a third capacitor connected in parallel;
a parallel circuit, a second resistor and a fourth capacitor connected between the output terminal of the amplifier and the non-inverting input terminal and having an impedance equal to that of the first parallel circuit. A power supply circuit comprising: a second parallel circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15669481A JPS5858864A (en) | 1981-10-01 | 1981-10-01 | Power source circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15669481A JPS5858864A (en) | 1981-10-01 | 1981-10-01 | Power source circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5858864A JPS5858864A (en) | 1983-04-07 |
| JPH0379950B2 true JPH0379950B2 (en) | 1991-12-20 |
Family
ID=15633291
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15669481A Granted JPS5858864A (en) | 1981-10-01 | 1981-10-01 | Power source circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5858864A (en) |
-
1981
- 1981-10-01 JP JP15669481A patent/JPS5858864A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5858864A (en) | 1983-04-07 |
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