JPS5864817A - Gyrator - Google Patents
GyratorInfo
- Publication number
- JPS5864817A JPS5864817A JP16345881A JP16345881A JPS5864817A JP S5864817 A JPS5864817 A JP S5864817A JP 16345881 A JP16345881 A JP 16345881A JP 16345881 A JP16345881 A JP 16345881A JP S5864817 A JPS5864817 A JP S5864817A
- Authority
- JP
- Japan
- Prior art keywords
- equation
- circuit
- capacitor
- operational amplifier
- equivalent inductance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/40—Impedance converters
- H03H11/42—Gyrators
Landscapes
- Networks Using Active Elements (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はダイナミックレンジの広くとれるノヤイレータ
の回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a noyerator circuit that can provide a wide dynamic range.
第1図は、構成素子数が少なく、シかもダイナミックレ
ンジが広く取れ、1個の演算増幅器により構成されるジ
ャイレータとして従来広く用いられている回路を示す。FIG. 1 shows a circuit that has been widely used as a gyrator with a small number of components, a wide dynamic range, and a single operational amplifier.
第1図の回路においてYIYzeYsは各素子のアドミ
タンス、vinハ入方端方端子1gb間の入力端子電圧
、4は演算増幅器、voutは演算増幅器4の出かを示
す。第1図の回路における入力アドミタンスYinは次
式で表わされる。In the circuit shown in FIG. 1, YIYzeYs is the admittance of each element, vin is the input terminal voltage between the input end terminal 1gb, 4 is the operational amplifier, and vout is the output of the operational amplifier 4. The input admittance Yin in the circuit of FIG. 1 is expressed by the following equation.
voutの間には次の関係がある。There is the following relationship between vout.
y、 V、 n= −y 2vout−−−−−−−=
−= (2)又、式(1)1式(2)よりYinは次式
(3)の様になる。y, V, n= −y 2vout−−−−−−=
-= (2) Also, from equations (1) and (2), Yin becomes as shown in the following equation (3).
わちYl 、Y3は各々抵抗R1# R3、y2にコン
デンサCを用いる)とすると、次式(4)に示す様なR
1yR3とL=RIR3Cで与えられるインダクタンス
Lとの並列回路となる。That is, Yl and Y3 are each resistor R1#, and capacitor C is used for R3 and y2), then R as shown in the following equation (4)
It becomes a parallel circuit of 1yR3 and inductance L given by L=RIR3C.
Y・ =±十工十
in R1R35CR1R3”’曲−(4)又、この
時の演算増幅器4の出力電圧V。utは式(2)よシ次
式で与えられる。Y=±100 in R1R35CR1R3"' (4) Also, the output voltage V.ut of the operational amplifier 4 at this time is given by the following equation from equation (2).
vout ” SCR、”in ・・
・・・・・・・・−(5)従って式(5)から明らかな
ように第1図に示す回路の演算増幅器4の出力電圧V。vout”SCR,”in...
......-(5) Therefore, as is clear from equation (5), the output voltage V of the operational amplifier 4 of the circuit shown in FIG.
utはvinに比して小さくなる。また式(4)におい
て等価インダクタンスのQ値を大きくするには実数部を
大きくしなければならず、したがってR1とR3を小さ
くしなければならない。一方L=RIR3Cで与えられ
るインダクタンスLを一定とした場合R1、R3を小さ
くしたことに伴いコンデンサCの容量が大きな値となる
。従って該回路のIC化に際しては大きな障害となる。ut is smaller than vin. Furthermore, in equation (4), in order to increase the Q value of the equivalent inductance, the real part must be increased, and therefore R1 and R3 must be decreased. On the other hand, when the inductance L given by L=RIR3C is kept constant, the capacitance of the capacitor C becomes large as R1 and R3 are made small. Therefore, it becomes a big obstacle when converting the circuit into an IC.
又、第1図に示す回路は式(4)から明らかなように、
等価インダクタンスを作る場合実数成分が必ず入ってく
る為Q値の高い等価インダクタンスは出来ないという欠
点がある。Also, as is clear from equation (4), the circuit shown in FIG.
When creating an equivalent inductance, a real number component is always included, so there is a drawback that it is impossible to create an equivalent inductance with a high Q value.
本発明の目的は、上述したように従来の回路においてコ
ンデンサの容量値が任意に設定出来ないという欠点、並
びに等価インダクタンスのQ値が高く出来ないという欠
点を除去したもやで以下詳細に説明する。The purpose of the present invention is to eliminate the disadvantages of the conventional circuit in that the capacitance value of the capacitor cannot be set arbitrarily and the Q value of the equivalent inductance cannot be set high, as described above in detail. .
第2図は本発明の回路図であって、Y、IY5 #Y6
v Y7 e Ysは各素子のアドミタンス、1
゜2.3は回路の節点、v2は節点2における電圧、v
3は節点3における電圧を示し、他の記号は第1図と同
じものを示す。第2図において、節点1゜2.3に対す
る節点方程式は次の様になる。(Ilは節点1における
電流を示す)
I 1 =(Y4+y8)Vin−y4v2−y8”o
ut ・・−・−・−・(6)o=(Y6+Y7)V
2−Y7vout ・・・・・・・−(7)o
=−Y4vin + (Y4 +Y5 )V2
−・(8)次にvinとv2#voutの関
係を式(7)、式(8)から求めると次式の通シとなる
。FIG. 2 is a circuit diagram of the present invention, Y, IY5 #Y6
v Y7 e Ys is the admittance of each element, 1
゜2.3 is the node of the circuit, v2 is the voltage at node 2, v
3 indicates the voltage at node 3, and the other symbols indicate the same as in FIG. In FIG. 2, the nodal equation for the node 1°2.3 is as follows. (Il indicates the current at node 1) I 1 = (Y4+y8) Vin-y4v2-y8”o
ut ・−・−・−・(6) o=(Y6+Y7)V
2-Y7vout ・・・・・・・-(7)o
=-Y4vin + (Y4 +Y5)V2
-.(8) Next, when the relationship between vin and v2#vout is determined from equations (7) and (8), the following equation is obtained.
従って、第2図に示す回路の入力インピーダンスzin
は(6)式よシ次の様になる。Therefore, the input impedance zin of the circuit shown in FIG.
The expression (6) is as follows.
zin=亡=π發繊蒔姶暗口 ・・・・・・・・・αp
ここで、Y5Y7=Y6Y8を満足する様にすると式Q
l)は次式の様な簡単な式となる。zin=death=π發璼璔姶安口・・・・・・・・・αp
Here, if Y5Y7=Y6Y8 is satisfied, the formula Q
l) is a simple equation as shown below.
zin =−L (t+ユ) ・・・・・・・
・・(2)ys ys
1
又、式(2)においてy、=sc、y5−6、Y、=古
(すなわちY5#Y8に各々抵抗R5#RII、Y4に
コンデンサCを用いる)とすると、次式で与えられるR
、Lの直列回路となる。−−”in = R@ (1+
5CRs ) −+++−・+・・+a
1次に、この回路のダイナミックレンジを決定する演算
増幅器4の入力、出力における電圧であるv2.vOu
tは式(9)、α0]次式で与えラレル。zin =-L (t+yu) ・・・・・・・・・
...(2) ys ys 1 Also, in equation (2), if y, = sc, y5-6, Y, = old (that is, resistors R5 #RII are used for Y5 #Y8, and capacitor C is used for Y4), R given by the following formula
, L becomes a series circuit. --”in = R@ (1+
5CRs) -++++-・+・・+a
First, v2., which is the voltage at the input and output of the operational amplifier 4, determines the dynamic range of this circuit. vOu
t is given by equation (9), α0].
(この場合節点3における電圧v3もv2と等しい) ここでY7 ”KY6 、YB ==[Ysである。(In this case, the voltage v3 at node 3 is also equal to v2) Here, Y7"KY6, YB==[Ys.
式(4)と弐α埠を比較した場合、式(4)の方は実数
部と虚数部とにR1とR3が入っており、コンデンサC
の容量値と等価インダクタンスのQ値とが密接に関係し
ており、等価インダクタンスのQ値を大キくスるとコン
デンサCも大きくなる。一方、式へ1の場合は抵抗R,
,R,が虚数部に入って針す、等価インダクタンスのQ
値にある程度無関係にコンデンサCの容量値を任意に設
定できる。従って本発明である第2図の回路図において
は、等価インダクタンスのQ値を大きくできるとともに
コンデンサCの容量値を小さくすることができる。When comparing Equation (4) and Niαbu, Equation (4) has R1 and R3 in the real part and imaginary part, and the capacitor C
The capacitance value and the Q value of the equivalent inductance are closely related, and if the Q value of the equivalent inductance is increased, the capacitor C will also become larger. On the other hand, if the equation is 1, then the resistance R,
, R, enters the imaginary part and the equivalent inductance Q
The capacitance value of the capacitor C can be set arbitrarily regardless of the value to some extent. Therefore, in the circuit diagram of FIG. 2 which is the present invention, the Q value of the equivalent inductance can be increased and the capacitance value of the capacitor C can be decreased.
次に一例として、R=1500、L=5.5mH。Next, as an example, R=1500, L=5.5mH.
C= 18000 pFのR,L、C直列共振回路の場
合について、第1図の従来回路と第2図の本発明の回路
とを比較する。In the case of an R, L, C series resonant circuit with C=18000 pF, the conventional circuit shown in FIG. 1 and the circuit according to the invention shown in FIG. 2 are compared.
第1図の回路の場合、前述のようにYl 、Ysを各々
抵抗RIFR3とし、Y2はコンデンサCとすると、抵
抗R1=Rs =300Ω、となるから、L=:CRI
R3よりコンデンサCの容量値は61000 pFとな
る。In the case of the circuit shown in Figure 1, as mentioned above, if Yl and Ys are each resistors RIFR3, and Y2 is a capacitor C, then the resistance R1 = Rs = 300Ω, so L = :CRI
The capacitance value of capacitor C is 61000 pF from R3.
一方第2図の本発明回路の場合、Y4をコンデンサC%
ys t ya l y、、YBを各々抵抗R5+
R6* R7e R8とすると、R7=R,=1500
となる。又、R,=R,=15にΩと設定するとL =
CRs RmよりコンデンサCの容量値は2443p
Fとなり、第1図に比して極めて小さくなる。On the other hand, in the case of the circuit of the present invention shown in FIG. 2, Y4 is the capacitor C%
ys t ya l y, , YB are each resistor R5+
R6* R7e R8, R7=R,=1500
becomes. Also, if R, = R, = 15 is set to Ω, L =
From CRs Rm, the capacitance value of capacitor C is 2443p
F, which is extremely small compared to that in FIG.
以上説明したように、本発明のノヤイレータ回路におい
ては、コンデンサCの容量を小さく任意に設定できると
ともに等価インダクタンスのQ値を高くすることができ
る利点を有している。従って該回路のIC化に際しても
、コンデンサの容量に原因する障害はなくなる。As explained above, the noyerator circuit of the present invention has the advantage that the capacitance of the capacitor C can be arbitrarily set to a small value and the Q value of the equivalent inductance can be increased. Therefore, even when the circuit is integrated into an IC, there is no problem caused by the capacitance of the capacitor.
第1図は従来のジャイレータ回路の回路図であシ、第2
図は本発明のジャイレータ回路の回路図である。
1.2.3・・・回路の節点、4・・・演算増幅器、1
a−1b・・・入力端子、vin・・・入力端子1a−
1b間の入力端子電圧、vout・・・演算増幅器4の
出力、y、I y5 t Y@ e y、t ys・
・・アドミタンス、v2・・・節点2における電圧、v
3・・・節点3における電圧。
特許出願人 沖電気工業株式会社Figure 1 is a circuit diagram of a conventional gyrator circuit.
The figure is a circuit diagram of a gyrator circuit according to the present invention. 1.2.3... Circuit node, 4... Operational amplifier, 1
a-1b...input terminal, vin...input terminal 1a-
Input terminal voltage between 1b, vout...output of operational amplifier 4, y, I y5 t Y@e y, tys・
... Admittance, v2 ... Voltage at node 2, v
3... Voltage at node 3. Patent applicant Oki Electric Industry Co., Ltd.
Claims (1)
を介して接続し、前記演算増幅器の反転側入力端子と前
記演算増幅器の出力端子とを第2の抵抗器を介して接続
するとともに一端を接地した第3の抵抗器の他端を前記
演算増幅器の反転側入力端子へ接続し、更に前記回路の
入力端子と前記演算増幅器の非反転側入力端子間を蓄電
器を介して接続するとともに一端を接地した第4の抵抗
器の他端を前記演算増幅器の非反転側入力端子へ接続し
た回路から成るジャイレータ。Connecting between the input terminal of the circuit and the output terminal of the operational amplifier via a first resistor, and connecting the inverting side input terminal of the operational amplifier and the output terminal of the operational amplifier via a second resistor. The other end of a third resistor whose one end is grounded is connected to the inverting input terminal of the operational amplifier, and the input terminal of the circuit and the non-inverting input terminal of the operational amplifier are connected via a capacitor. A gyrator comprising a circuit in which one end of a fourth resistor is grounded and the other end is connected to the non-inverting input terminal of the operational amplifier.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16345881A JPS5864817A (en) | 1981-10-15 | 1981-10-15 | Gyrator |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16345881A JPS5864817A (en) | 1981-10-15 | 1981-10-15 | Gyrator |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5864817A true JPS5864817A (en) | 1983-04-18 |
JPS6218090B2 JPS6218090B2 (en) | 1987-04-21 |
Family
ID=15774260
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16345881A Granted JPS5864817A (en) | 1981-10-15 | 1981-10-15 | Gyrator |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5864817A (en) |
-
1981
- 1981-10-15 JP JP16345881A patent/JPS5864817A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6218090B2 (en) | 1987-04-21 |
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