JPH0379868B2 - - Google Patents
Info
- Publication number
- JPH0379868B2 JPH0379868B2 JP4438481A JP4438481A JPH0379868B2 JP H0379868 B2 JPH0379868 B2 JP H0379868B2 JP 4438481 A JP4438481 A JP 4438481A JP 4438481 A JP4438481 A JP 4438481A JP H0379868 B2 JPH0379868 B2 JP H0379868B2
- Authority
- JP
- Japan
- Prior art keywords
- electronic functional
- functional element
- withstand voltage
- voltage
- chip package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000005540 biological transmission Effects 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 6
- 239000000919 ceramic Substances 0.000 description 5
- 238000007789 sealing Methods 0.000 description 4
- 238000001514 detection method Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000006386 memory function Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/62—Protection against overvoltage, e.g. fuses, shunts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Non-Volatile Memory (AREA)
Description
【発明の詳細な説明】
本発明は、高密度配線基板を構成する共通の支
持基体上に複数の電子的機能要素を半導体チツプ
レベルで搭載したマルチチツプパツケージの構造
に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a multi-chip package in which a plurality of electronic functional elements are mounted at the semiconductor chip level on a common support base constituting a high-density wiring board.
近年、電子部品の小型化、高信頼化の要求が高
まつて来ており従来のプリント基板上にプラスチ
ツクあるいはセラミツクモールドされた半導体素
子を搭載する実装方法では小型化の要求を満足で
きなくなつて来ている。このため電子的機能要素
である半導体素子をチツプの状態で一つの支持基
体である例えばセラミツク等からなる高密度多層
配線基板上に例えばフリツプチツプ法、ビームリ
ード法、フイルムキヤリア法、チツプアンドワイ
ヤー法等により実装し全体を気密封止するいわゆ
るマルチチツプパツケージング技術が開発されて
きた。 In recent years, there has been an increasing demand for electronic components to be smaller and more reliable, and the conventional mounting method of mounting semiconductor elements molded in plastic or ceramic on a printed circuit board is no longer able to meet the demands for miniaturization. It is coming. For this purpose, a semiconductor element, which is an electronic functional element, is placed in the form of a chip on a high-density multilayer wiring board made of ceramic, etc., which is a single supporting substrate, using a flip-chip method, a beam lead method, a film carrier method, a chip-and-wire method, etc. A so-called multi-chip packaging technology has been developed in which the entire chip is hermetically sealed.
このようなマルチチツプパツケージにおいては
全体の回路構成がシステムレベルに近づくにつれ
マルチチツプパツケージ内に例えばPROMある
いはFPROM等の、他の電子的機能要素の最大定
格電圧以上の電圧を印加しないとその機能を持ち
得ない様な高耐電圧電子的機能要素が存在する事
が多くなつてくる。この場合、全ての電子的機能
要素を共通の支持基体上に実装して単純に相互接
続すると、高耐電圧電子的機能要素の機能を保有
させるべく高電圧を印加したとき他の低耐電圧電
子的機能要素を破壊してしまうという問題が生じ
る。 In such multichip packages, as the overall circuit configuration approaches the system level, it becomes impossible to function unless a voltage higher than the maximum rated voltage of other electronic functional elements, such as PROM or FPROM, is applied inside the multichip package. Increasingly, there are electronic functional elements with high withstand voltages that cannot be maintained. In this case, if all the electronic functional elements are mounted on a common support substrate and simply interconnected, then when a high voltage is applied to retain the functionality of the high-voltage electronic functional elements, other low-voltage electronic functional elements A problem arises in that functional elements are destroyed.
そこで従来では第1図に示す如く、高耐電圧電
子的機能要素A群14と低耐電圧電子的機能要素
B群15とを分離し、低耐電圧電子的機能要素B
は半導体チツプの状態で支持基体例えばセラミツ
ク等の高密度多層配線基板12上に支持固定して
マルチチツプパツケージ化し、高耐電圧電子的機
能要素Aは半導体チツプレベルではなく、従来の
プラスチツクあるいはセラミツクモールドパツケ
ージを例えばプリント配線基板11上に直接ある
いはICソケツト16等を介して支持固定すると
し実装方法を採用していた。しかしながらこの方
法は、回路の小型化という点で充分満足のいくも
のではなかつた。しかも高耐電圧電子的機能要素
A群14と低耐電圧電子的機能要素B群15間の
配線長も長くなるため、誘導雑音及び回路の動作
速度等の点においても問題があつた。 Therefore, in the past, as shown in FIG.
is in the form of a semiconductor chip and is supported and fixed on a support base, such as a high-density multilayer wiring board 12 made of ceramic, to form a multi-chip package, and the high voltage electronic functional element A is not at the semiconductor chip level, but in a conventional plastic or ceramic molded package. For example, a mounting method has been adopted in which the IC is supported and fixed directly on the printed wiring board 11 or via an IC socket 16 or the like. However, this method was not fully satisfactory in terms of circuit miniaturization. Furthermore, since the wiring length between the high-withstand voltage electronic functional element group A 14 and the low-withstand voltage electronic functional element group B 15 becomes long, there are also problems in terms of induced noise and circuit operation speed.
本発明は、この様な事情を考慮して成されたも
ので、その目的とするところは高耐電圧および低
耐電圧の電子的機能要素をいずれもチツプの状態
で共通の支持基体上に搭載することが可能で、回
路の小型化、高速化を図るマルチチツプパツケー
ジを提供することにある。 The present invention was made in consideration of these circumstances, and its purpose is to mount both high-withstand voltage and low-withstand voltage electronic functional elements in the form of a chip on a common support base. The object of the present invention is to provide a multi-chip package that can reduce the size of the circuit and increase the speed of the circuit.
本発明は、支持基体上に配設された入出力端子
から高耐電圧および低耐電圧電子的機能要素に順
次配線された伝送路中の高耐電圧電子的機能要素
から低耐電圧電子的機能要素に到る部分に分断部
を設け、この分断部によつて高耐電圧電子的機能
要素と低耐電圧電子的機能要素を電気的に分離し
た状態で高耐電圧電子的機能要素に所定の電圧を
印加して所定の機能を保有せしめた後、分断部を
短絡して高耐電圧電子的機能要素と低耐電圧電子
的機能要素とを電気的に結合することにより、マ
ルチチツプパツケージ全体として所要の回路機能
を持たしめることを特徴としている。 The present invention provides a method for connecting a high withstand voltage electronic function element to a low withstand voltage electronic function in a transmission line which is wired sequentially from an input/output terminal disposed on a support base to a high withstand voltage and a low withstand voltage electronic function element. A dividing part is provided in the part that reaches the element, and the high withstanding voltage electronic functional element is electrically separated from the high withstanding voltage electronic functional element by the dividing part, and a predetermined voltage is applied to the high withstanding voltage electronic functional element. After applying a voltage to have a predetermined function, the divided portion is short-circuited to electrically connect the high-withstand voltage electronic functional element and the low-withstand voltage electronic functional element, thereby forming the entire multichip package. It is characterized by having the required circuit functions.
従つて、本発明によれば高耐電圧電子的機能要
素にその機能を保有させるための印加電圧による
低耐電圧電子的機能要素の破壊の問題を伴うこと
なく、これらの各電子的機能要素を共通の支持基
体上に搭載することができるので、回路をより小
型化でき、また相互の配線長が短かくなることに
よつて動作の高速化と誘導雑音の減少も図ること
が可能となる。 Therefore, according to the present invention, each of these electronic functional elements can be operated without the problem of destruction of the low withstand voltage electronic functional elements due to the applied voltage to allow the high withstand voltage electronic functional elements to retain their functions. Since they can be mounted on a common support base, the circuit can be made more compact, and by shortening the mutual wiring length, it is possible to increase the speed of operation and reduce induced noise.
以下、図面を参照して本発明の実施例を説明す
る。 Embodiments of the present invention will be described below with reference to the drawings.
第2図は本発明の一実施例に係るマルチチツプ
パツケージの構成を示す。21は支持基体であ
り、例えばセラミツク等からなる高密度多層配線
基板を構成している。22はシーリング用キヤツ
プ、23は入出力ピンである。また24は支持基
体21上に電子的機能要素A,Bをマウントすべ
く形成されたダイボンデイングパツド、25は電
子的機能要素A,Bと支持基体21上の配線とを
例えばAu線あるいはAl線等によるワイヤーボン
デイングによつて接続すべく形成されたワイヤー
ボンデイングパツド、26はシーリングキヤツプ
22の接着用の導体パターンである。 FIG. 2 shows the structure of a multi-chip package according to an embodiment of the present invention. A support base 21 constitutes a high-density multilayer wiring board made of, for example, ceramic. 22 is a sealing cap, and 23 is an input/output pin. Further, 24 is a die bonding pad formed to mount the electronic functional elements A, B on the supporting base 21, and 25 is a die bonding pad formed to mount the electronic functional elements A, B and the wiring on the supporting base 21 using, for example, Au wire or Aluminum wire. A wire bonding pad 26 formed to be connected by wire bonding with a wire or the like is a conductive pattern for bonding the sealing cap 22.
27aは例えばPROMあるいはEPROM等の
高耐電圧電子的機能要素Aと、他の低耐電圧電子
的機能要素Bとを接続する配線を一時的に分断す
るための分断部を構成する近接した端子対であ
り、この端子対27aは支持基体21上のシーリ
ングキヤツプ22内部に配線パターンの一部とし
て形成されている。また27bも同様な端子対で
あるが、27aとは異なり支持基体21の周辺部
上のシーリングキヤツプ22外部に配線パターン
の一部として形成されている。この様な構造にお
いて入出力端子28aあるいは28bよりA,B
に順次配線された伝送路を通して高耐電圧電子的
機能要素Aに所定の電圧(PROM,EPROM等
の場合は書き込み電圧)を印加し、その機能(メ
モリとしての機能)を保有すべく処理する。しか
る後端子対27aあるいは27bを短絡し、Aと
Bとを電気的に結合する事により全体として所要
の回路機能を持たしめる。このようにすれば低耐
電圧電子的機能要素Bはその定格電圧を越える様
な電圧が印加される事から免がれ破壊される事は
無い。なお、端子対27a,27bの短絡操作は
例えばAu線あるいはAl線によるワイヤーボンデ
イング、あるいはハンダボール等によるハンダブ
リツジ、あるいは導電エポキシ等により可能であ
る。 Reference numeral 27a denotes a pair of adjacent terminals constituting a disconnection section for temporarily disconnecting the wiring connecting a high-voltage electronic functional element A such as PROM or EPROM to another low-voltage electronic functional element B. This terminal pair 27a is formed inside the sealing cap 22 on the support base 21 as part of the wiring pattern. Also, 27b is a similar terminal pair, but unlike 27a, it is formed outside the sealing cap 22 on the periphery of the support base 21 as part of the wiring pattern. In such a structure, A and B are connected to the input/output terminal 28a or 28b.
A predetermined voltage (write voltage in the case of PROM, EPROM, etc.) is applied to the high-voltage electronic functional element A through the transmission line sequentially wired to the element A, and the element A is processed to maintain its function (memory function). Thereafter, the terminal pair 27a or 27b is short-circuited and A and B are electrically coupled to provide the required circuit function as a whole. In this way, the low withstand voltage electronic functional element B will be protected from the application of a voltage exceeding its rated voltage and will not be destroyed. The terminal pair 27a, 27b can be short-circuited by, for example, wire bonding using Au wire or Al wire, solder bridge using solder balls, conductive epoxy, or the like.
27c〜27eは分断部の他の構成例を示して
いる。27cは支持基体21上に支持固定された
スイツチ機能要素であつて、高耐電圧電子的機能
要素Aに所定の電圧を印加するときオフ状態とな
つて低耐電圧電子的機能要素Bにその定格電圧以
上の電圧が印加されないようにするためのもので
ある。またこのスイツチ機能要素27cの代りに
スイツチ機能を取除いた単なる中継機能要素27
dを用いてもよい。次に27eは入出力端子28
cから高耐電圧電子的機能要素Aにその機能を保
有させるべく高電圧が入力されると、その電圧を
検知し、その高電圧が高耐電圧電子的機能要素A
のみに配線29を通して印加され、高電圧が入出
力端子28cに入力されていない時は自動的に配
線29と配線30とを電気的に接続する如く、電
圧検知結果に応じて自動的に分断状態と短絡状態
とに切換わる電気回路を形成する電子的機能要素
C群である。この電圧検知機能を有する電子的機
能要素C群はA,Bと同様に半導体チツプレベル
にて支持基体21上に支持固定される。ただしこ
の場合、電子的機能要素Cの耐電圧及び入出力電
流容量の値や、電子的機能要素Cを介する事によ
り高耐電圧電子的機能要素Aに印加される電圧が
所定の電圧より低下しない様にすること等を充分
考慮して設計する必要がある。 27c to 27e show other configuration examples of the dividing portion. Reference numeral 27c is a switch functional element supported and fixed on the support base 21, and when a predetermined voltage is applied to the high withstand voltage electronic functional element A, it is turned off and the low withstand voltage electronic functional element B is switched to its rated value. This is to prevent a voltage higher than the voltage from being applied. Also, instead of this switch function element 27c, a simple relay function element 27 from which the switch function has been removed.
d may also be used. Next, 27e is the input/output terminal 28
When a high voltage is input from c to the high voltage electronic functional element A to have the function, that voltage is detected and the high voltage is applied to the high voltage electronic functional element A.
When high voltage is not input to the input/output terminal 28c, the wiring 29 and the wiring 30 are automatically connected electrically, and the wiring 29 and 30 are automatically connected to the disconnected state according to the voltage detection result. and a short circuit state. The group C of electronic functional elements having this voltage detection function is supported and fixed on the support base 21 at the semiconductor chip level similarly to A and B. However, in this case, the values of the withstand voltage and input/output current capacity of the electronic functional element C, and the voltage applied to the high withstand voltage electronic functional element A via the electronic functional element C, do not drop below a predetermined voltage. It is necessary to take into consideration the following factors when designing.
なお、この発明は上記実施例に限定されるもの
ではなく、例えば第2図中のA,Bはそれぞれ単
一の半導体チツプによる高耐電圧電子的機能要素
及び低耐電圧電子的機能要素でなく、高耐電圧電
子的機能要素群であり低耐電圧電子的機能要素群
であつても良い。また図中においては各配線を一
本の線にて示しているが、これは多くは複数の配
線を表わすものであり、その場合端子対も各配線
毎に設けられるものと考えねばならない。また第
2図は主にチツプアンドワイヤー法によるマルチ
チツプパツケージを例として示しているが、これ
に限定されるものではなく、フリツプチツプ法、
フイルムキヤリア法、ビームリード法等によるマ
ルチチツプパツケージであつてもよい。 Note that the present invention is not limited to the above-mentioned embodiments; for example, A and B in FIG. , may be a high withstand voltage electronic functional element group, or may be a low withstand voltage electronic functional element group. Furthermore, although each wiring is shown as a single line in the figure, this often represents a plurality of wirings, and in this case it must be considered that a terminal pair is also provided for each wiring. Although FIG. 2 mainly shows a multi-chip package using the chip-and-wire method as an example, the present invention is not limited to this.
It may also be a multi-chip package using a film carrier method, a beam lead method, or the like.
以上説明したように、本発明によればPROM,
EPROM等を含むようなシステムレベルの回路機
能を共通の支持基体上にマルチチツプパツケージ
ングできるようになり、回路の小型化、高速化の
要求に十分対応することが可能となる。 As explained above, according to the present invention, PROM,
It becomes possible to package system-level circuit functions, such as EPROM, etc., on a common support base in multi-chip packaging, making it possible to fully meet the demands for smaller and faster circuits.
第1図は低耐電圧電子的機能素子のみマルチチ
ツプパツケージ化した従来の技術を説明するため
の一部断面側面図、第2図a,bは本発明の一実
施例に係るマルチチツプパツケージの平面図およ
び一部断面側面図である。
21……支持基体、27a,27b……分断部
を構成する端子対、27c……分断部を構成する
スイツチ機能要素、27d……分断部を構成する
中継機能要素、27e……分断部を構成する電子
的機能要素、A……高耐電圧電子的機能要素、B
……低耐電圧電子的機能要素。
FIG. 1 is a partially sectional side view for explaining a conventional technique in which only low-voltage electronic functional elements are packaged into a multichip package, and FIGS. 2a and 2b show a multichip package according to an embodiment of the present invention. FIG. 2 is a plan view and a partially sectional side view. 21... Support base, 27a, 27b... Terminal pair forming the dividing section, 27c... Switch functional element forming the dividing section, 27d... Relay functional element forming the dividing section, 27e... forming the dividing section. Electronic functional element, A... High voltage electronic functional element, B
...Low withstand voltage electronic functional elements.
Claims (1)
をチツプの状態で搭載しかつそれらを相互接続し
て所要の回路機能を持たせたマルチチツプパツケ
ージであつて、かつ前記電子的機能要素の一部が
他の低耐電圧電子的機能要素の最大定格電圧以上
の所定の電圧が印加されることにより所定の機能
を保有する高電圧電子的機能要素であるマルチツ
プパツケージにおいて、前記支持基体上に配設さ
れた入出力端子より前記高耐電圧および低耐電圧
電子的機能要素に順次配線されている伝送路中の
高耐電圧電子的機能要素から低耐電圧機能要素に
到る部分に分断部を設け、この分断部によつて高
耐電圧電子的機能要素と低耐電圧電子的機能要素
を電気的に分離した状態で高耐電圧電子的機能要
素に所定の電圧を印加して所定の機能を保有せし
めた後、前記分断部を短絡して高耐電圧電子的機
能要素と低耐電圧電子的機能要素とを電気的に結
合することにより全体として所要の回路機能を持
たしめるように構成したことを特徴とするマルチ
チツプパツケージ。 2 分断部は支持基体上の配線パターンの一部と
して形成された近接した端子対であることを特徴
とする特許請求の範囲第1項記載のマルチチツプ
パツケージ。 3 分断部は支持基体上に支持固定されたスイツ
チ機能要素あるいは中継機能要素であることを特
徴とする特許請求の範囲第1項記載のマルチチツ
プパツケージ。 4 分断部は支持基体上の入出力端子より印加さ
れる電圧を検知し自動的に分断状態と短絡状態と
に切換わる機能を有する電子的機能要素によつて
構成されることを特徴とする特許請求の範囲第1
項記載のマルチチツプパツケージ。 5 高耐電圧電子的機能要素はPROMまたは
EPROMであることを特徴とする特許請求の範囲
第1項記載のマルチチツプパツケージ。[Scope of Claims] 1. A multi-chip package in which a plurality of electronic functional elements are mounted in the form of chips on a common support base and are interconnected to provide a required circuit function, and A multi-pack package in which some of the electronic functional elements are high-voltage electronic functional elements that possess a predetermined function by applying a predetermined voltage higher than the maximum rated voltage of other low-voltage electronic functional elements. , from the high withstand voltage electronic functional element to the low withstand voltage functional element in the transmission path, which is wired sequentially from the input/output terminal arranged on the support base to the high withstand voltage and low withstand voltage electronic functional element. A dividing portion is provided in the portion leading to the high withstand voltage electronic functional element, and the high withstand voltage electronic functional element is electrically separated from the low withstand voltage electronic functional element by the dividing portion, and a prescribed voltage is applied to the high withstand voltage electronic functional element. is applied to have a predetermined function, and then the divided portion is short-circuited to electrically connect the high withstand voltage electronic functional element and the low withstand voltage electronic functional element, thereby achieving the required circuit function as a whole. A multi-chip package characterized by being configured to have. 2. The multi-chip package according to claim 1, wherein the dividing portion is a pair of adjacent terminals formed as part of a wiring pattern on the support substrate. 3. The multi-chip package according to claim 1, wherein the dividing portion is a switch function element or a relay function element supported and fixed on the support base. 4. A patent characterized in that the dividing section is constituted by an electronic functional element that has the function of detecting the voltage applied from the input/output terminal on the support base and automatically switching between the disconnected state and the short-circuited state. Claim 1
Multi-chip package as described in section. 5 High voltage withstand electronic functional elements are PROM or
The multi-chip package according to claim 1, which is an EPROM.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4438481A JPS57159054A (en) | 1981-03-26 | 1981-03-26 | Multitip package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4438481A JPS57159054A (en) | 1981-03-26 | 1981-03-26 | Multitip package |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57159054A JPS57159054A (en) | 1982-10-01 |
JPH0379868B2 true JPH0379868B2 (en) | 1991-12-20 |
Family
ID=12690005
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4438481A Granted JPS57159054A (en) | 1981-03-26 | 1981-03-26 | Multitip package |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57159054A (en) |
-
1981
- 1981-03-26 JP JP4438481A patent/JPS57159054A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS57159054A (en) | 1982-10-01 |
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