KR100352118B1 - Semiconductor package structure - Google Patents

Semiconductor package structure Download PDF

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Publication number
KR100352118B1
KR100352118B1 KR1019960062308A KR19960062308A KR100352118B1 KR 100352118 B1 KR100352118 B1 KR 100352118B1 KR 1019960062308 A KR1019960062308 A KR 1019960062308A KR 19960062308 A KR19960062308 A KR 19960062308A KR 100352118 B1 KR100352118 B1 KR 100352118B1
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South Korea
Prior art keywords
semiconductor chip
semiconductor
lead
package
semiconductor package
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KR1019960062308A
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Korean (ko)
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KR19980044246A (en
Inventor
신원선
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앰코 테크놀로지 코리아 주식회사
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Priority to KR1019960062308A priority Critical patent/KR100352118B1/en
Publication of KR19980044246A publication Critical patent/KR19980044246A/en
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Publication of KR100352118B1 publication Critical patent/KR100352118B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE: A semiconductor package structure is provided to increase capacity and mounting density of a semiconductor package by attaching two semiconductor chips to the inside of the semiconductor package. CONSTITUTION: An electronic circuit is integrated in the first semiconductor chip(11). The second semiconductor chip(12) is attached to the upper surface of the first semiconductor chip by using epoxy(50). A plurality of leads(20) in rows and columns are placed on the lower surface of the first semiconductor chip. A plurality of bumps(31) and wires(32) electrically connect the first and second semiconductor chips with the leads. Resin encapsulant(40) protects the first semiconductor chip, the second semiconductor chip, the bump, the wire and the lead from the outer environment wherein the lower surface of the lead is exposed to the outside.

Description

반도체 패키지 구조Semiconductor package structure

본 발명은 반도체 패키지의 구조에 관한 것으로, 더욱 상세하게는 반도체 패키지의 내부에 두개의 반도체칩을 부착하여 패키지의 용량을 확대함은 물론, 실장밀도를 높이고, 패키지를 고집적화 및 고성능화 할 수 있는 반도체 패키지의 구조에 관한 것이다.The present invention relates to a structure of a semiconductor package, and more particularly, to a semiconductor package having two semiconductor chips attached to the inside of the semiconductor package to expand the capacity of the package, increase the mounting density, and increase the package density and performance. It is about the structure of the package.

최근에 다핀화의 추세에 따른 기술적 요구를 해결하기 위해서 등장한 반도체 패키지는 입출력 수단을 패키지의 일면으로 노출시켜 이를 입출력 수단으로 사용함으로서 보다 많은 수의 입출력 신호를 수용할 수 있음은 물론, 그 크기도 작게 형성한 것이다.In recent years, semiconductor packages, which have emerged to solve technical demands due to the trend of multi-pinning, are exposed to one side of a package and used as an input / output means, which can accommodate a larger number of input / output signals, as well as their size. It is formed small.

이러한 반도체 패키지의 구성은 도 1에 도시된 바와같이 전자회로가 집적되어 있는 반도체칩(1)과, 상기 반도체칩(1)을 지지함과 아울러 반도체칩(1)의 신호를 외부로 전기적 접속 경로를 이루는 리드(2)와, 상기 반도체칩(1)을 전기적으로 연결시키는 와이어(3)와, 상기의 반도체칩(1), 리드(2) 및 와이어(3)를 외부환경으로 부터 보호하기 위한 봉지수지(4)를 포함하며, 상기의 리드(2)는 내측으로 봉지수지(4)의 저면에 노출되도록 리드(2)를 절곡 형성하여서 된 것이다.As shown in FIG. 1, the semiconductor package includes a semiconductor chip 1 in which electronic circuits are integrated, a semiconductor chip 1, and a path for electrically connecting signals from the semiconductor chip 1 to the outside. A lead 2, a wire 3 electrically connecting the semiconductor chip 1, and the semiconductor chip 1, the lead 2, and the wire 3 to protect the external device from an external environment. The encapsulation resin 4 is included, and the lid 2 is formed by bending the lid 2 to be exposed to the bottom surface of the encapsulation resin 4 inward.

그러나, 이러한 반도체 패키지는 내부에 하나의 반도체칩(1)이 부착되어 있어 패키지의 용량을 확대하기 위해서는 하나 이상의 반도체 패키지를 마더보드에 실장하여야 그 용량을 확대시킬 수 있는데, 이와같이 하나 이상의 반도체 패키지를 마더보드에 실장 할 경우에는 마더보드의 표면에 각각 실장하여야 됨으로서 실장면적이 커지게 되고, 이는 소형화 추세에 역행하는 결과를 가져오는 문제점이 있었던 것이다.However, such a semiconductor package has one semiconductor chip 1 attached therein, and in order to increase the capacity of the package, at least one semiconductor package must be mounted on the motherboard to increase its capacity. In the case of mounting on the motherboard, the mounting area is increased by mounting each on the surface of the motherboard, which has a problem that results in a trend against the miniaturization trend.

본 발명의 목적은 이와같은 문제점을 해결하기 위하여 발명된 것으로서, 반도체 패키지의 내부에 두개의 반도체칩을 부착함으로서 패키지의 용량을 확대하고, 실장밀도를 높이며, 패키지를 고집적화 및 고성능화 할 수 있는 반도체 패키지의 구조를 제공함에 있다.An object of the present invention is to solve the above problems, by attaching two semiconductor chips to the inside of the semiconductor package to increase the package capacity, increase the mounting density, high integration and high performance of the package package In providing a structure.

도 1은 종래의 반도체 패키지에 대한 구조를 나타낸 단면도1 is a cross-sectional view showing a structure of a conventional semiconductor package

도 2는 본 발명에 따른 반도체 패키지의 구성을 나타낸 단면도2 is a cross-sectional view showing the configuration of a semiconductor package according to the present invention.

도 3은 본 발명에 따른 반도체 패키지의 실시예를 나타낸 단면도3 is a cross-sectional view showing an embodiment of a semiconductor package according to the present invention.

- 도면의 주요 부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawing-

11,12 - 제1,2 반도체칩 20 - 리드11,12-1,2 Semiconductor Chip 20-Lead

31- 범프 32 - 와이어31- bump 32-wire

40 - 수지봉지재 50 - 에폭시40-Resin Encapsulant 50-Epoxy

이하, 각 발명을 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, each invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명에 따른 반도체 패키지의 구성을 나타낸 단면도로서, 그 구조는 전자회로가 집적되어 있는 제1 반도체칩(11)과, 상기 제1 반도체칩(11)의 상면에 에폭시(50)에 의해 접착된 제2 반도체칩(12)과, 상기의 제1 반도체칩(11)의 신호를 전기적으로 접속시키는 범프(31)와, 상기의 제2 반도체칩(12)의 신호를 전기적으로 접속시키는 와이어(32)와, 상기의 범프(31) 및 와이어(32)에 연결되어 제1 반도체칩(11) 및 제2 반도체칩(12)의 신호를 외부로 전달하는 리드(20)와, 상기의 제1 반도체칩(11), 제2 반도체칩(12), 범프(31) 및 리드(20)를 외부환경으로 부터 보호하기 위하여 감싸진 수지봉지재(40)로 이루어지는 것을 특징으로 한다.2 is a cross-sectional view showing the configuration of a semiconductor package according to the present invention, the structure of which is a first semiconductor chip 11 in which an electronic circuit is integrated, and an epoxy 50 on the upper surface of the first semiconductor chip 11. To electrically connect the second semiconductor chip 12 bonded to each other, the bump 31 for electrically connecting the signal of the first semiconductor chip 11, and the signal of the second semiconductor chip 12. A wire 32, a lead 20 connected to the bumps 31 and the wires 32 to transfer the signals of the first semiconductor chip 11 and the second semiconductor chip 12 to the outside, and The first semiconductor chip 11, the second semiconductor chip 12, the bumps 31, and the lid 20 may be formed of a resin encapsulant 40 wrapped to protect the external environment.

상기의 제1 반도체칩(11) 및 제2 반도체칩(12)의 신호가 범프(31) 및 와이어(32)에 의해 연결되어 외부로 전달시키는 리드(20)는 수지봉지재(40)의 일면으로 다수의 열과 행을 가지면서 노출되도록 배열되는 것이다. 또한, 이러한 리드(20)는 수지봉지재(40)의 저면으로 노출됨과 동시에 수지봉지재(40)의 측면으로도 돌출될수 있는 것이다.One side of the resin encapsulant 40 may include a lead 20 to which the signals of the first semiconductor chip 11 and the second semiconductor chip 12 are connected by the bumps 31 and the wires 32 and transmitted to the outside. Are arranged to be exposed with multiple columns and rows. In addition, the lead 20 may be exposed to the bottom surface of the resin encapsulant 40 and may also protrude toward the side of the resin encapsulant 40.

또한, 도 3에 도시된 바와같이 제1 반도체칩(11)의 상부에 에폭시(50)로 부착된 제2 반도체칩(12)은 제1 반도체칩(11) 보다 작은 크기의 반도체칩을 부착시킴으로서 제1 반도체칩(11) 및 제2 반도체칩(12) 모두 와이어(32)로 리드(20)와 연결시켜 외부로 신호를 전달할 수 있는 것이다.In addition, as shown in FIG. 3, the second semiconductor chip 12 attached with the epoxy 50 on the first semiconductor chip 11 attaches a semiconductor chip having a smaller size than the first semiconductor chip 11. Both the first semiconductor chip 11 and the second semiconductor chip 12 may be connected to the lead 20 by a wire 32 to transmit a signal to the outside.

이와같이 구성된 본 발명의 반도체 패키지는 내부에 제1 반도체칩(11)과 제2 반도체칩(12)을 부착시켜 용량을 확대한 것으로, 대 용량을 요구하는 장비에 실장시에 매우 유용하다. 즉, 상기 반도체 패키지를 마더보드에 실장하면 두개의 반도체 패키지를 실장한 결과를 얻음으로서 용량을 확대할 수 있는 것으로 실장면적을 줄일 수 있는 것이다.The semiconductor package of the present invention configured as described above has an enlarged capacity by attaching the first semiconductor chip 11 and the second semiconductor chip 12 therein, and is very useful for mounting in equipment requiring large capacity. In other words, when the semiconductor package is mounted on a motherboard, a result of mounting two semiconductor packages is obtained, thereby increasing the capacity, thereby reducing the mounting area.

이상의 설명에서와 같이 본 발명에 따른 반도체 패키지는 내부에 두개의 반도체칩을 부착함으로서 패키지의 용량을 확대하고, 실장밀도를 높이며, 패키지를 고집적화 및 고성능화 할 수 있는 효과가 있다.As described above, the semiconductor package according to the present invention has an effect of expanding the package capacity, increasing the mounting density, and increasing the package density and performance by attaching two semiconductor chips therein.

Claims (4)

전자회로가 집적되어 있는 제1반도체칩과, 상기 제1반도체칩의 상면에 에폭시에 의해 접착된 제2반도체칩과, 상기 제1반도체칩의 하면에 다수의 열과 행을 가진 채 배열된 다수의 리드와, 상기 제1반도체칩 및 제2반도체칩을 상기 리드에 전기적으로 접속시키는 다수의 범프 및 와이어와, 상기 제1반도체칩, 제2반도체칩, 범프 및 와이어, 리드를 외부 환경으로부터 보호하기 위해 봉지하되 상기리드의 하면은 외부로 노출되도록 봉지하는 수지봉지재를 포함하여 이루어진 반도체패키지의 구조.A first semiconductor chip in which electronic circuits are integrated, a second semiconductor chip bonded by epoxy to an upper surface of the first semiconductor chip, and a plurality of rows and rows arranged on a lower surface of the first semiconductor chip Protecting a lead, a plurality of bumps and wires electrically connecting the first semiconductor chip and the second semiconductor chip to the lead, and protecting the first semiconductor chip, the second semiconductor chip, the bumps and wires and the leads from an external environment. The sealing of the semiconductor package structure consisting of a resin encapsulation material for encapsulating the lower surface of the lead to be exposed to the outside. 제1항에 있어서, 상기 리드는 수지봉지재의 저면으로 노출됨과 동시에 수지봉지재의 측면으로도 돌출됨을 특징으로 하는 반도체패키지의 구조.The semiconductor package structure of claim 1, wherein the lead is exposed to the bottom surface of the resin encapsulant and protrudes from the side surface of the resin encapsulant. 제1항에 있어서, 상기 제1반도체칩의 상부에 부착된 제2반도체칩은 제1반도체칩보다 작은 크기의 반도체칩인 것을 특징으로 하는 반도체패키지의 구조.The semiconductor package structure of claim 1, wherein the second semiconductor chip attached to the upper portion of the first semiconductor chip is a semiconductor chip having a smaller size than that of the first semiconductor chip. 제3항에 있어서, 상기 제1반도체칩 및 제2반도체칩은 모두 와이어로 리드에 본딩된 것을 특징으로 하는 반도체패키지의 구조.The structure of claim 3, wherein both the first semiconductor chip and the second semiconductor chip are bonded to a lead by wires.
KR1019960062308A 1996-12-06 1996-12-06 Semiconductor package structure KR100352118B1 (en)

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Cited By (2)

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KR100444168B1 (en) * 2001-12-28 2004-08-11 동부전자 주식회사 semiconductor package
KR101001207B1 (en) * 2008-11-17 2010-12-15 앰코 테크놀로지 코리아 주식회사 Lead Frame, and chip stack package and method for manufacturing the same

Families Citing this family (1)

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Publication number Priority date Publication date Assignee Title
KR100440788B1 (en) * 1999-12-20 2004-07-19 앰코 테크놀로지 코리아 주식회사 Semiconductor package and its manufacturing method

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KR100444168B1 (en) * 2001-12-28 2004-08-11 동부전자 주식회사 semiconductor package
KR101001207B1 (en) * 2008-11-17 2010-12-15 앰코 테크놀로지 코리아 주식회사 Lead Frame, and chip stack package and method for manufacturing the same

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