JPH03796B2 - - Google Patents

Info

Publication number
JPH03796B2
JPH03796B2 JP13378482A JP13378482A JPH03796B2 JP H03796 B2 JPH03796 B2 JP H03796B2 JP 13378482 A JP13378482 A JP 13378482A JP 13378482 A JP13378482 A JP 13378482A JP H03796 B2 JPH03796 B2 JP H03796B2
Authority
JP
Japan
Prior art keywords
layer
active layer
cladding layer
type inp
width
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP13378482A
Other languages
Japanese (ja)
Other versions
JPS5925290A (en
Inventor
Koichi Imanaka
Hideaki Horikawa
Yoshio Kawai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP13378482A priority Critical patent/JPS5925290A/en
Publication of JPS5925290A publication Critical patent/JPS5925290A/en
Publication of JPH03796B2 publication Critical patent/JPH03796B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/227—Buried mesa structure ; Striped active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/227—Buried mesa structure ; Striped active layer
    • H01S5/2275—Buried mesa structure ; Striped active layer mesa created by etching

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Semiconductor Lasers (AREA)

Description

【発明の詳細な説明】 この発明は埋込み型半導体レーザの製造方法に
関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a buried semiconductor laser.

従来の埋込み型半導体レーザを、ｐ型InP基板
を用いた場合を例にとり第１図に示す。第１図に
おいて、１はプラス電極、２はｐ型InP基板結
晶、３はｐ型InPクラッド層、４はInGaAsP活性
層、５はｎ型InPクラツド層、６はｎ型InPブロ
ツク層、７はＰ型InP閉じ込め層、８はマイナス
電極である。 FIG. 1 shows a conventional buried semiconductor laser using a p-type InP substrate as an example. In Fig. 1, 1 is a positive electrode, 2 is a p-type InP substrate crystal, 3 is a p-type InP cladding layer, 4 is an InGaAsP active layer, 5 is an n-type InP cladding layer, 6 is an n-type InP block layer, and 7 is a P-type InP confinement layer, 8 is a negative electrode.

このような従来の埋込み型半導体レーザにおい
て、活性層４およびクラツド層３，５からなる埋
込まれ層の作成には通常化学エツチングが用いら
れるが、活性層４の幅の制御は、各面方位へのエ
ツチングレートにより自動的に決定されるエツチ
ングマスク幅の設定によつている。 In such conventional buried semiconductor lasers, chemical etching is usually used to create the buried layer consisting of the active layer 4 and the cladding layers 3 and 5, but the width of the active layer 4 can be controlled by adjusting the width of each plane. This depends on the setting of the etching mask width, which is automatically determined based on the etching rate.

しかしながら、その方法は、ウエハー表面とマ
スクとの密着性の悪さに起因する設定外のサイド
エツチングや、エツチング液の濃度、温度の制御
の困難さなどにより、活性層４の幅を再現性よく
制御することが難しいという欠点を有していた。
また、発振閾値を低減するために活性層４の幅を
狭くすると、埋込まれ層全体の幅が小さくなり、
オーミツクがとりにくいという欠点も有してい
た。 However, this method cannot control the width of the active layer 4 with good reproducibility due to side etching outside the specified settings due to poor adhesion between the wafer surface and the mask, and difficulty in controlling the concentration and temperature of the etching solution. It had the disadvantage that it was difficult to do so.
Furthermore, when the width of the active layer 4 is narrowed in order to reduce the oscillation threshold, the width of the entire buried layer becomes smaller.
It also had the disadvantage of being difficult to remove.

この発明は上記の点に鑑みなされたもので、活
性層幅を再現性よく制御することができ、しかも
活性層幅を狭くしても上部クラツド層の幅は狭く
ならず、したがつて電極とのオーミツクも容易に
とることができる埋込み型半導体レーザの製造方
法を提供することを目的とする。 This invention was made in view of the above points, and it is possible to control the width of the active layer with good reproducibility, and even if the width of the active layer is narrowed, the width of the upper cladding layer is not narrowed, so that the width of the upper cladding layer is not narrowed. It is an object of the present invention to provide a method for manufacturing an embedded semiconductor laser, which can easily achieve ohmic control.

以下この発明の実施例を図面を参照して説明す
るが、この前にこの発明の第１の実施例により製
造された埋込み型半導体レーザを第２図に示す。
第２図において、１１はプラス電極、１２はＰ型
InP基板結晶、１３はＰ型InPクラツド層、１４
はInGaAsP活性層、１５はｎ型InPクラツド層、
１６はｎ型InPブロツク層、１７はＰ型InP閉じ
込め層、１８はマイナス電極である。ここで、活
性層１４は従来に比較し非常に狭い幅に形成され
ている。しかし、クラツド層１５は、その活性層
１４上に逆台形状に形成されて、上面においては
比較的広い幅を維持している。一方、クラツド層
１３は、活性層１４の下に垂直部１９を有するよ
うに形成されている。 Embodiments of the present invention will be described below with reference to the drawings. First, a buried semiconductor laser manufactured according to the first embodiment of the present invention is shown in FIG.
In Figure 2, 11 is a positive electrode, 12 is a P type
InP substrate crystal, 13 is P-type InP cladding layer, 14
15 is the InGaAsP active layer, 15 is the n-type InP cladding layer,
16 is an n-type InP block layer, 17 is a p-type InP confinement layer, and 18 is a negative electrode. Here, the active layer 14 is formed to have a much narrower width than conventional ones. However, the cladding layer 15 is formed on the active layer 14 in an inverted trapezoidal shape and maintains a relatively wide width at the top surface. On the other hand, the cladding layer 13 is formed to have a vertical portion 19 below the active layer 14.

以上のような埋込み型半導体レーザは第３図に
示すこの発明の第１の実施例により製造される。 The buried semiconductor laser as described above is manufactured according to the first embodiment of the present invention shown in FIG.

第３図Ａにおいて、１２はｐ型InP基板結晶で
あり、まずこの基板結晶１２上に１回目のLPE
（Liquid Phase Epitaxial：液相成長法）により
ｐ型InPクラツド層１３、InGaAsP活性層１４、
ｎ型InPクラツド層１５を順次成形する。そし
て、クラツド層１５上には適当な幅の絶縁体エツ
チングマスク２０を設ける。 In FIG. 3A, 12 is a p-type InP substrate crystal, and first, the first LPE is applied on this substrate crystal 12.
(Liquid Phase Epitaxial: liquid phase growth method) p-type InP cladding layer 13, InGaAsP active layer 14,
The n-type InP cladding layer 15 is sequentially molded. Then, an insulator etching mask 20 of an appropriate width is provided on the cladding layer 15.

しかる後、InPには活性であるがInGaAsPには
不活性である塩酸系（4HCl＋1H2O）エツチヤン
トにより、絶縁体エツチングマスク２０をマスク
としてｎ型InPクラツド層１５をエツチングし、
第３図Ｂに示すように残存クラツド層１５の両側
で活性層１４を露出させる。 Thereafter, the n-type InP cladding layer 15 is etched using the insulator etching mask 20 as a mask using a hydrochloric acid-based (4HCl + 1H 2 O) etchant that is active on InP but inactive on InGaAsP.
The active layer 14 is exposed on both sides of the remaining cladding layer 15, as shown in FIG. 3B.

続いて、InGaAsPには活性であるがInPには不
活性である硫酸系（3H2SO4＋1H2O2＋1H2O）ま
たはフエリシアン化加系（K3Fe（CN）6＋KOH＋
H2O）のエツチヤントにより、InGaAsP活性層
１４の露出部のエツチング、さらには活性層１４
のサイドエツチングを行う。このサイドエツチン
グにより、活性層１４は最終的には第３図Ｃに示
すように、クラツド層１５の中央部下のみに幅狭
に残される。 This was followed by a sulfuric acid system (3H 2 SO 4 + 1H 2 O 2 + 1H 2 O) or a ferricyanidation system (K 3 Fe(CN) 6 + KOH+), which is active on InGaAsP but inactive on InP.
The exposed portion of the InGaAsP active layer 14 is etched by the etchant (H 2 O), and the active layer 14 is etched.
Perform side etching. As a result of this side etching, the active layer 14 is ultimately left with a narrow width only under the center of the cladding layer 15, as shown in FIG. 3C.

しかる後、前記した塩酸系のエツチヤントによ
り残存活性層１４をマスクとしてＰ型InPクラツ
ド層１３およびｐ型InP基板結晶１２の厚さ方向
のエツチングを行う。このエツチングを行うと、
第３図Ｄに示すように、まずクラツド層１３が活
性層１４の下に垂直部１９として残るようにエツ
チングされ、しかる後、クラツド層１３の下部側
および基板結晶１２表面側が台形状となるように
エツチングされる。この時同時に、ｎ型InPクラ
ツド層１５に対しても活性層１４をマスクとして
下方から厚さ方向にエツチングが行われる。ただ
し、ｎ型InPクラツド層１５に関しては、垂直部
を経ることなく、即、逆台形状にエツチングされ
る。このように、２つのクラツド層１３，１５で
エツチング形状が異なる点はその理由が不明であ
る。しかし、実験をくり返したところ、いずれも
上記のようなエツチング形状となつた。 Thereafter, using the remaining active layer 14 as a mask, the p-type InP cladding layer 13 and the p-type InP substrate crystal 12 are etched in the thickness direction using the hydrochloric acid-based etchant described above. When this etching is done,
As shown in FIG. 3D, the cladding layer 13 is first etched so as to remain under the active layer 14 as a vertical portion 19, and then the lower side of the cladding layer 13 and the surface side of the substrate crystal 12 are etched so as to have a trapezoidal shape. Etched by. At the same time, the n-type InP cladding layer 15 is also etched from below in the thickness direction using the active layer 14 as a mask. However, the n-type InP cladding layer 15 is immediately etched into an inverted trapezoidal shape without passing through the vertical portion. The reason why the etching shapes of the two cladding layers 13 and 15 are different in this way is unknown. However, after repeated experiments, the etched shapes shown above were obtained in all cases.

しかる後、基板結晶１２上に、クラツド層１
３，１５および活性層１４の側方を覆うように、
第２図で示したｎ型InPブロツク層１６およびｐ
型InP閉じ込め層１７（埋込み層）を２回目の
LPEにより成長させる。 After that, a cladding layer 1 is formed on the substrate crystal 12.
3, 15 and the sides of the active layer 14,
The n-type InP block layer 16 and p
Type InP confinement layer 17 (buried layer) for the second time
Grow by LPE.

以上の説明から明らかなように、第１の実施例
では、InPには不活性のエツチヤントを用いた活
性層１４のエツチングにより、マスク２０の幅や
クラツド層１５の厚みなどに無関係に、活性層１
４の幅を再現性よく自由に制御できる。したがつ
て、半導体レーザ素子間の特性の均一化を図るこ
とができるとともに、活性層１４の幅を狭くして
発振閾値の低減を図ることができる。 As is clear from the above description, in the first embodiment, the active layer 14 is etched using an etchant that is inert to InP, so that the active layer 14 can be etched regardless of the width of the mask 20 or the thickness of the cladding layer 15. 1
The width of 4 can be freely controlled with good reproducibility. Therefore, it is possible to make the characteristics of the semiconductor laser elements uniform, and also to reduce the oscillation threshold by narrowing the width of the active layer 14.

また、活性層１４をマスクとしてクラツド層１
３と基板結晶１２をエツチングする際、同時にク
ラツド層もエツチングされるが、上記エツチング
を厚さ方向にのみ行うことによりクラツド層１５
は逆台形状にエツチングされる。したがつて、た
とえ活性層１４の幅を狭くしても、クラツド層１
５の上面は、マスク２０の幅で決まる広い幅を維
持するようになり、その結果として電極とのオー
ミツクを容易にとることができる。 Further, the cladding layer 1 is formed using the active layer 14 as a mask.
3 and the substrate crystal 12, the cladding layer 15 is also etched at the same time, but by performing the above etching only in the thickness direction, the cladding layer 15 is etched.
is etched into an inverted trapezoidal shape. Therefore, even if the width of the active layer 14 is narrowed, the width of the cladding layer 1
The upper surface of the mask 5 maintains a wide width determined by the width of the mask 20, and as a result, it is possible to easily establish ohmic contact with the electrode.

また、活性層１４をマスクとしてクラツド層１
３および基板結晶１２を厚さ方向にエツチングす
ることでクラツド層１３の垂直部１９を形成して
おり、これにより活性層１４と基板結晶１２との
間に急峻な段差を大きくとることができる。した
がって、ｐ型InP基板を用いた半導体レーザにお
いては、ブロツク層１６を成長させた際に、その
ブロツク層１６の反り上がりを活性層１４より下
の位置で止める必要があるが、それを容易に行う
ことができる。 Further, the cladding layer 1 is formed using the active layer 14 as a mask.
The vertical portion 19 of the cladding layer 13 is formed by etching the active layer 14 and the substrate crystal 12 in the thickness direction, thereby making it possible to create a large steep step between the active layer 14 and the substrate crystal 12. Therefore, in a semiconductor laser using a p-type InP substrate, when the block layer 16 is grown, it is necessary to stop the warpage of the block layer 16 at a position below the active layer 14, but this can be easily prevented. It can be carried out.

以上の説明から明らかなように、この発明の製
造方法では、活性層とクラツド層とを独立にエツ
チングし、しかも残存活性層をマスクとしてクラ
ツド層をエツチングする際、厚さ方向にエツチン
グし、下部クラツド層には残存活性層の下に垂直
部を形成する。したがつて、この発明の方法によ
れば、活性層の幅を再現性よく自由に制御でき
て、半導体レーザ素子間の特性の均一化を図るこ
とができるとともに、活性層の幅を狭くして発振
閾値の低減を図ることができ、さらには、活性層
の幅を狭くしても上部クラツド層の幅を広くとつ
て電極とのオーミツクを容易にとることができ
る。また、ｐ型InP基板を用いた半導体レーザに
おいては、ブロツク層を成長させた際に、そのブ
ロツク層の反り上がりを活性層より下の位置で止
める必要があるが、前記クラツド層の垂直部の存
在により、それを容易に行うことができるもので
ある。 As is clear from the above description, in the manufacturing method of the present invention, the active layer and the cladding layer are etched independently, and when etching the cladding layer using the remaining active layer as a mask, etching is performed in the thickness direction, and the lower part is etched. A vertical portion of the cladding layer is formed below the remaining active layer. Therefore, according to the method of the present invention, the width of the active layer can be freely controlled with good reproducibility, and the characteristics between semiconductor laser devices can be made uniform, and the width of the active layer can be narrowed. The oscillation threshold can be reduced, and furthermore, even if the width of the active layer is narrowed, the width of the upper cladding layer can be widened to easily establish ohmic contact with the electrodes. Furthermore, in a semiconductor laser using a p-type InP substrate, when a block layer is grown, it is necessary to stop the warping of the block layer at a position below the active layer. Its existence makes it easy to do so.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の埋込み型半導体レーザを示す断
面図、第２図はこの発明の第１の実施例により製
造された埋込み型半導体レーザを示す断面図、第
３図はこの発明の埋込み型半導体レーザの製造方
法の第１の実施例を示す断面図である。 １２……ｐ型InP基板結晶、１３……ｐ型InP
クラツド層、１４……InGaAsP活性層、１５…
…ｎ型InPクラツド層、１６……ｎ型InPブロツ
ク層、１７……ｐ型InP閉じ込め層、１９……垂
直部。 FIG. 1 is a cross-sectional view of a conventional buried semiconductor laser, FIG. 2 is a cross-sectional view of a buried semiconductor laser manufactured according to a first embodiment of the present invention, and FIG. 3 is a cross-sectional view of a buried semiconductor laser of the present invention. 1 is a cross-sectional view showing a first example of a method for manufacturing a laser; FIG. 12... p-type InP substrate crystal, 13... p-type InP
Cladding layer, 14... InGaAsP active layer, 15...
... n-type InP cladding layer, 16 ... n-type InP block layer, 17 ... p-type InP confinement layer, 19 ... vertical portion.

Claims (1)

【特許請求の範囲】[Claims] １ 基板上に第１のクラツド層、活性層、第２の
クラツド層を順次形成した後、第２のクラツド層
のみを選択的にエツチングして、残在第２のクラ
ツド層の両側で活性層を露出させる工程と、この
活性層の露出部をエツチングするとともに活性層
のサイドエツチングを行い、前記残存第２のクラ
ツド層の下に活性層を幅狭に残す工程と、この残
存活性層をマスクとしてクラツド層を厚さ方向に
エツチングし、残存活性層の下に第１のクラツド
層の垂直部を形成する工程と、残存クラツド層お
よび残存活性層の側方を覆うように埋込み層を形
成する工程とを具備することを特徴とする埋込み
型半導体レーザーの製造方法。1 After sequentially forming a first cladding layer, an active layer, and a second cladding layer on a substrate, only the second cladding layer is selectively etched to form an active layer on both sides of the remaining second cladding layer. a step of exposing the exposed portion of the active layer and performing side etching of the active layer to leave a narrow width of the active layer under the remaining second cladding layer; and a step of masking the remaining active layer. etching the cladding layer in the thickness direction to form a vertical portion of the first cladding layer under the remaining active layer; and forming a buried layer to cover the sides of the remaining cladding layer and the remaining active layer. A method for manufacturing an embedded semiconductor laser, comprising the steps of:
JP13378482A 1982-08-02 1982-08-02 Manufacture of buried type semiconductor laser Granted JPS5925290A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13378482A JPS5925290A (en) 1982-08-02 1982-08-02 Manufacture of buried type semiconductor laser

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13378482A JPS5925290A (en) 1982-08-02 1982-08-02 Manufacture of buried type semiconductor laser

Publications (2)

Publication Number Publication Date
JPS5925290A JPS5925290A (en) 1984-02-09
JPH03796B2 true JPH03796B2 (en) 1991-01-08

Family

ID=15112913

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13378482A Granted JPS5925290A (en) 1982-08-02 1982-08-02 Manufacture of buried type semiconductor laser

Country Status (1)

Country Link
JP (1) JPS5925290A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0810779B2 (en) * 1987-02-23 1996-01-31 アンリツ株式会社 Semiconductor laser
JPH088391B2 (en) * 1987-02-23 1996-01-29 アンリツ株式会社 Semiconductor laser

Also Published As

Publication number Publication date
JPS5925290A (en) 1984-02-09

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