JPH0377997B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a drive circuit for a conductor array in an AC (alternating current) plasma display device.

In a conventional AC plasma display device, an array of parallel conductors are arranged orthogonally facing each other on the inner surface of a panel filled with gas, and the intersections of the conductors form gas cells. A discharge voltage can be applied to selectively ionize the gas cells to produce a visual display of specific shapes or information. During discharge, the cell generates a wall charge voltage that is combined with a low level hold signal.

Plasma display devices are equipped with a circuit that generates a holding voltage consisting of a periodic voltage that maintains the gas cell discharge at a frequency sufficient to maintain the discharge. This allows certain shapes and information to remain as they are in the visual representation.
The holding voltage is also used to regulate write and erase operations. The peak of the holding voltage is about 200V.

The generation of this high voltage hold signal is controlled by a low voltage circuit that is responsive to digital logic signals from an external processor or controller, which logic signals are dependent on the operations being caused to occur in the plasma device. Since the voltage levels of the hold signal and the logic signal are different, a device for communication between them is required to operate the plasma device. For example, US Pat. No. 3,973,253,
No. 4097856 and others use a pulse transformer to transmit signals while maintaining insulation between low-voltage and high-voltage circuits. It is desired to replace this pulse transformer with a low-cost semiconductor circuit.

One problem in plasma equipment is controlling the displacement time of a switching waveform such as a holding voltage. Although techniques already exist to control displacement time at low rates of change, this becomes exponentially more difficult as rates and voltages increase. High-power vertical field effect transistor (VFET) used in plasma equipment drive circuits
This becomes especially difficult when using high output
VFETs exhibit wide bandwidth characteristics and tend to oscillate unless their gate drive circuits have higher frequency characteristics. VFETs also have higher input capacitance (eg 1200pF), requiring the use of low impedance driver circuits. There are also differences in gain between devices, and each device requires different gate-to-source inputs in order to obtain the same rate of change in output.

Conventional plasma device drive circuits have not paid much attention to the change time, ie, the control of the rise and fall of the switch waveform, such as the holding voltage. I was only thinking about speeding up the displacement time. In large plasma devices, fast displacement times cause large currents within the device. It is desirable to control the displacement time of the switch waveform to a fixed time or a fixed rate of change.

An object of the present invention is to control the displacement time of a switch waveform to a constant time or a constant rate of change using a low-cost semiconductor circuit, and to isolate a high voltage pulse circuit from a low voltage control circuit without using a transformer. An object of the present invention is to provide an improved plasma display device drive circuit that transmits signals across its floating boundaries to a low voltage control circuit.

[Essentials of the present invention]

The present invention provides a plasma device drive circuit in which the displacement of the holding voltage waveform is controlled to be constant over a certain period of time. The displacement time is defined as a constant time independent of voltage changes that occur during operation of the circuit.
A VFET is used as an output switch to create a holding voltage to the gas cell. Some sources of the VFET float up and down when the VFET is not used, and its gate remains connected to those sources when the VFET is not used. [VFET
The low voltage circuitry used to drive the source also floats with the source potential.

The transformers traditionally used to route digital logic signals from external controllers and processors to floating, low-voltage drive circuits have been replaced by lower-cost semiconductor circuits. With this method,
Logic signals are sent across the boundary of the high voltage section to the low voltage drive circuit without a transformer.

Another form of the present invention is a form in which the displacement time of the holding voltage waveform is controlled to a constant rate of change.

[Explanation of Examples]

In FIG. 1, a drive circuit 20 of the present invention is connected to an external controller 11 or another processor (not shown).
to digital logic signals (mainly TTL level)
It has a switch circuit 12 for receiving. These logic circuits are used only to control the holding operation of the plasma device. It does not provide information to be displayed on a plasma device.

The switch circuit 12 receives the logic signal and sends the information to the control circuit 13. The control circuit 13 determines the displacement time of the holding waveform applied from the VFET 14 to the cell 16. The control circuit 13 includes a low voltage gate drive circuit that drives the gate of the VFET 14, a current source, and a gate isolation circuit that isolates the low voltage gate drive circuit from the voltage source 15. These functions will be explained in detail later with reference to FIGS. 3 to 7.

An example of a hold waveform sent from VFET output 14 to cell 16 can be seen in FIG. US Patent No.
As shown in No. 4263534, plasma
It is difficult to obtain a 200V VFET with characteristics that can be used in panels. So from peak to peak
2 with 100V VFET in each stage to obtain 200V waveform
The circuit must be designed in stages. The first stage has the waveform shown in FIG. 2 and moves from point 17 to point 18 with a width of 100 from peak to peak. The output of the first stage is connected to the input of the second stage, which provides a range of 100V to 200V from point 18 to point 19 in FIG. In total, this two-stage circuit is peak to peak.
Create a 200V shape.

Displacement time here means rise time or fall time. The rise time controlled by the invention is the rise time of each stage, i.e. 0 at the first stage.
~100V and a rise time of 100-200V in the second stage. This rise time is the time from 100% of the maximum value to 90% of the maximum value in the waveform. Similarly, the descending time referred to in the present application is the descending time of each stage, and is the time from 90% to 10% of the maximum amplitude value.

The rising edge and falling edge refer to the rising portion at the front end and the falling portion at the rear end of the signal, respectively. The rising edge is the portion of the waveform from the lowest point to the highest point, and the falling edge is the portion from the highest point to the lowest point. The rising edge has a positive slope, and the falling edge has a negative slope.

FIG. 3 is a schematic diagram of a circuit that controls the falling time of the switching waveform to a constant time. The source of the VFET 26 is connected to the ground potential, and the drain is connected to the output terminal 28. When the base of transistor 25 is at a low voltage, transistor 23 is turned on;
Drive the gate of VFET 26 to turn on the device. When the base of transistor 25 goes high, it is turned on, and the base of transistor 23 is lowered to approximately ground potential, turning it off, removing the drive current to the gate of VFET 26, which is also turned off. Switch 27 will be discussed later in connection to the circuit of FIG.

The current used to drive the gate of VFET 26 is obtained from a current source consisting of resistor 21 connected between a high voltage power supply V _S (eg 100V) and approximately ground potential. Since the value of the high voltage power supply V _S often fluctuates, the value of the current source also fluctuates. The second terminal of resistor 21 is connected to the base of transistor 23, so that this terminal is connected to the base-emitter voltage of transistor 23 and the transconductance of VFET 26.
The potential becomes higher than the ground potential by the sum of a certain value depending on gm. If the gm of VFET26 changes, the gate-source voltage will also change. gm is the gain of VFET26,
Contains terms that depend on gate-source voltage. When the gate-source voltage changes, the voltage across the resistor 21 changes, and the current that changes it also changes. This fluctuation can be ignored compared to a high voltage source such as 100V.

The current from this current source is divided between the base of transistor 23 and capacitor 22. As it approaches output point 28 and ground, capacitor 22 draws more current from the base of transistor 23. Thus, the current flowing through the capacitor 22 is
It functions as a feedback control that regulates the amount of drive current sent to the gate of VFET 26. This feedback current is equal to the value C of the capacitor 22 multiplied by the time rate of change of the voltage, i.e. I=
Cdv/dt.

The value C of capacitor 22 is constant. The supplied current is a function of the power supply voltage V _S and is V _S /R, where R is the value of the resistor 21 . Since the gain of transistor 23 is chosen to be extremely high, the base current value sent to transistor 23 is equal to that of capacitor 22.
It is small compared to the current flowed by. A shape that can be well approximated is one in which the current in the resistor 21 is equal to the current flowing in the capacitor 22. In the above formula, resistance 21
If the current value is replaced, V _S /R=Cdv/dt.

Here, if d _V represents the displacement over the entire range of V _S , then
d _V =V _S and dt = R×C. The rise time of the output voltage is now set to a constant time independent of the voltage fluctuations experienced by the circuit.

FIG. 4 is a modified form of the fall time control circuit of FIG. 3, which includes a switching circuit 12 which receives digital logic signals from an external processor or the like via a terminal 31. Transistors 34 and 35 have the same function as transistors 23 and 25 in FIG. 3, and resistor 46 and capacitor 42 have the same function as resistor 21 and capacitor 22. transistor 3
Since the gain of 4 tends to be small, transistor 36 is added to boost the gain. In this manner, sufficient current is provided to the gate of VFET 30 to turn on the device.
The source of VFET 30 is output terminal 45. Capacitor 44 and resistor 46 having approximately the supply voltage V _S create a current source with a value of V _S divided by the value of resistor 46 . In reality, resistor 46 is one of the terminals.
One terminal is connected to the capacitor 4, and the other terminal is connected to the base of the transistor 36, which base becomes the reference point for the voltage of the resistor 46. switch 2
9 is for connection to other circuits, which will be added later to the 8th
Explanation will be given regarding the figure.

The switching circuit 12 in FIG. 4 consists of an inverter 32 and a transistor 33 connected in a common base manner, and when the device is not in use, a VFET 30 is connected.
The source of is floating. This floating is 0 volts and V _S
volts, and at this time the control circuit driving VFET 30 also floats. Therefore, digital logic signals must be transmitted across floating boundaries.
Although an inverter is used in this example, any logic gate may be used to receive the digital signal at input 31.

Transistor 33 acts as a switching current source to send a digital logic signal (eg, a TTL level referenced to ground) to a floating rise time control circuit. When a high level signal is applied to terminal 31 of inverter 32, transistor 33 is turned on. This in turn turns off transistor 35 and directs sufficient current in resistor 39 to the base of transistor 34 to turn on the device. This provides sufficient drive current to the gate of VFET 30 to turn on the device.

FIG. 5 is a schematic diagram of a circuit that controls the falling edge of the switch waveform to a constant rate of change. The source of the VFET 51 is connected to ground potential, and the drain serves as an output terminal 57. When the base of transistor 55 is held low, transistor 54
is turned on, driving the gate of VFET 51 and turning it on. When the base of transistor 55 goes high, it turns on. As a result, the base of the transistor 54 is pulled down to approximately the ground potential, the transistor 54 is turned off, and the drive current to the gate of the VFET 51 is eliminated. The rate of change dv/dt is the change in output voltage at terminal 57 over time and is equal to the feedback current to the gate drive circuit of VFET 51 divided by the value of capacitor 53. A drive current to the VFET 51 is given from a constant current source 52. The value of capacitor 53 is fixed. Since the value of the current applied to the gate control circuit of the VFET 51 is constant, the rate of change dv/dt is constant.

This means that the falling edge of the output voltage, ie the holding voltage, is controlled at a constant rate of change. In this way, the falling edge is also fixed at a constant rate of change and has a constant slope even if the output voltage value changes. The increment in dv is offset by the increment in dt to maintain a constant dv/dt value.

FIG. 6 shows a modification of the falling edge control circuit of FIG. 5, which includes a switching circuit 12 that receives a digital logic signal from an external processor or the like. The transistors 73 and 78 are the transistors 54 and 54 in FIG.
It works in the same way as VFET 61, allowing sufficient current to flow through the gate of VFET 61 to turn it on. The source of VFET 61 is output terminal 62. The function of the switching circuit 12 in FIG. 6 is the same as that described in connection with FIG.

The circuit of FIG. 6 has a constant current source (Vcc) different from the current source used in FIG. When transistor 78 is turned on (keeping VFET 61 off), the source of VFET 61 is grounded, so capacitor 68 is connected through diodes 67 and 72 to
It is charged to a DC level of a value obtained by subtracting the potential drop of the diodes 67 and 72 and the saturation voltage of the transistor 78 from Vcc. When transistor 73 is turned on, the charge in capacitor 68 is driven by the emitter of transistor 73, and the current in resistor 69 is equal to the voltage of capacitor 68 minus the base-emitter voltage of transistor 77 plus the base-emitter voltage of transistor 73 divided by the value of resistor 69. becomes. Since the base-emitter voltages of transistors 73 and 77 are approximately equal, this is the voltage across capacitor 68 divided by the value across resistor 69. In this way a constant current source is created.

The circuit of FIG. 7 is a variation of the circuit of FIG. 3 and has a gate control isolation circuit that isolates the low voltage gate control circuit from the high voltage power supply. The drain of VFET 82 is output terminal 93. When switch 92 is in the V _S position, diode 87 is reverse biased;
High voltage V _S , low voltage drive circuit consisting of transistors 83, 84, 85, power supply V _S and transistor 8
4 and a current source consisting of a resistor 81 connected between the bases of the resistor 81. At this time, it is desirable to keep VFET 82 off, which requires keeping the gate of VFET 82 from a voltage that would turn it on. The gate voltage of VFET 82 is the sum of the voltage at its source, the base-emitter voltage of transistor 89, and the voltage across resistor 91. Among these, the item that can be controlled is the voltage of the resistor 91. By lowering the voltage across the resistor with low resistance value, VFET8
It is next to impossible to do it well enough to keep 2 off. Since diode 88 is reverse biased, the current in resistor 91 is almost entirely the base current of transistor 89. Since the emitter current is the product of the gain and the base current, the voltage across the resistor 91 is the emitter current of the transistor 89 x the value of the resistor 91 ÷ the gain. If the gain of transistor 89 is made large enough, its voltage can be kept at a low level without making the value of resistor 91 impossibly small.

When switch 92 is in the ground position, diodes 87 and 88 are forward biased and transistor 89
is turned off. At this time, this circuit works like the circuit shown in FIG.

FIG. 8 shows a drive system that provides a constant rise time from peak to peak holding voltage of 200V. This system includes the circuits shown in FIGS. 3, 4, and 7.

Initially, circuits 110 and 130 are off and circuit 12
0,140 is on. At this time, line 96 is pulled down to ground. Both ends of the capacitor 94
At 100 volts, line 97 is at 100 volts. Line 95, the output to the plasma cell, is at ground potential. When circuit 120 is off and circuit 110 is on, line 96 goes to 100 volts and line 97 above capacitor 94 goes up to 200 volts. Line 97 provides the 200 volt power supply to circuit 130. Line 95 then provides 100 volts to the cell. When circuit 140 is off and circuit 130 is on, line 95 provides 200 volts to the cell. In this way, the circuit of FIG.
It has a first stage that provides an output signal of ~100 volts, and a second stage that provides an output signal of 0 to 100 volts, referenced to the output of this stage, and has a 0 to 100 volt output signal on output line 95.
Generates a voltage referenced to 200 volts and applies it to the gas cell.

[Brief explanation of drawings]

FIG. 1 is a plan diagram of the plasma panel display driving device of the present invention, FIG. 2 is a diagram of waveforms obtained by the present invention, and FIGS. 3 to 8 are rises of plasma cell drive waveforms of the present invention. It is a diagram showing an example of a circuit for controlling the fall time. 11... External processor, 12... Switching circuit, 13... Control circuit, 14... VFET output, 15... Voltage source, 16... Plasma cell,
22, 44, 53, 68... Capacitor, 21,
39,69,81,91...Resistance, 30,51,
61, 82...VFET, 23, 25, 33, 3
4, 35, 36, 54, 55, 63, 73, 7
7, 78, 83, 84, 85, 89...transistor.

Claims (1)

[Scope of Claims] 1. A drive circuit for supplying a holding voltage to a display device having a plurality of discharge cells, comprising: (a) a drain connected to a voltage source V _S and a source connected to an output terminal for the display device; (b) a first switch circuit having a first FET which can be connected to the first FET and has a gate;
A second FET, which can be connected to the source of the FET, has a second FET whose source is grounded, and has a gate.
(c) a third switch having a source connected to the output terminal, a drain connectable to the voltage source V _S via a second connection point, and a third FET having a gate; (d) a fourth switch circuit having a gate, the drain being connected to the output terminal, the source being connected to the first connection point, and (e) the anode being connected to the first connection point; (f) a _capacitor connected between the first connection point and the second connection point; (g) The above drive circuit can be put into the following three states, namely: (g-1) The above voltage source V _S is applied to the above capacitor.
One end of the capacitor is grounded in order to charge the voltage of
a first state in which _the FET is brought into a non- _conducting state; a second state in which the first and fourth FETs are brought into conduction and the second and third FETs are brought into non-conduction in order to form a conduction path leading to the output terminal; (g-3) Applying the voltage of the voltage source V _S in series with the capacitor charged to the voltage of the voltage source V _S in the first state,
In order to form a conduction path that applies a voltage twice the voltage of the voltage source V _S to the output terminal, the first and third FETs are brought into conduction, and the second and fourth FETs are brought into conduction. of
A drive circuit, comprising: a third state in which the FET is rendered non-conductive; and a control means for setting the drive circuit in one of the following states.