JPH0377701B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates generally to the field of data communications, and in particular to communication between multiple terminals via a common data communications medium, and where the terminal communicates with all other terminals. The present invention relates to a terminal device that autonomously accesses a data communication medium independently of a terminal or device.

[Prior Art] U.S. Pat. No. 4,199,663, Autonomous Terminal Data Communication System (by Herzog, Assigned to the Assignee of the Invention on April 22, 1980) describes a system in which each of a plurality of terminals communicates data such as a data bus. A data communication system is described in which messages can be sent periodically over a medium and in which the sending of messages by each terminal is autonomous with respect to the sending of messages by all other terminals. Message transmission by a certain terminal is only possible when certain protocols are satisfied. This protocol requires that no message be present on the data communication medium for a time approximately equal to the "terminal" gap between messages specific to that terminal, and that a predetermined transmission interval has elapsed since the previous message transmission by the terminal. It is required that the The transmission intervals of all terminals have approximately the same length, which is greater than the sum of all terminal gaps and the lengths of all messages sent by the terminals since the last message sent by a terminal.

Such systems rely on a central bus, as each connected terminal autonomously accesses the data communication medium for the purpose of sending messages
This eliminates the need for a controller to control the transmission of messages, significantly reduces the need for wiring between connected terminals, and significantly increases the reliability of the data communication system. One drawback is that messages must be sent periodically. For example, once a message is sent on the data communication medium, the terminal must wait until its transmission interval has elapsed before initiating another message communication. When a data communication system is designed for a very large number of connected terminals,
When only a small number of connected terminals are transmitting messages, a fixed fixed transmission interval must elapse, so the rate at which any terminal can continuously transmit messages is limited, It is clear that this also makes the data communication medium idle, thus wasting a considerable amount of time.

In addition, the protocol of US Pat. No. 4,199,663 requires that the lengths of consecutive messages from any terminal be approximately equal to preserve periodic message transmission by that terminal.
Therefore, when transmitting a large amount of data from one terminal to another, a fixed message length is required, so only a portion of the data can be transmitted in a given time, and the data It is clear that the next part of can not be sent until the next interval has elapsed.

In the application of data communications systems to modern aircraft, the requirement to periodically transmit messages of substantially fixed length is ideally suited to the requirements of aeronautical systems employing data communications systems. For example, an aviation system is a closed-loop system in which a transmitting terminal transmits data obtained from a sensor, and a utilization device connected to a receiving terminal operates based on the data sent out by the transmitting terminal and performs a certain control function. It forms a servo system. Such applications require periodic message transmission, so that the control actions performed by the utilization device have a predetermined time relationship with the data from the sensors. However, there are other types of aviation systems, such as surveillance and display systems, that require the transmission of periodic messages, thereby reducing the functionality of the system. In a typical monitoring and display system, a subsystem connected to multiple transmitting terminals is each connected as a unit.
Central monitoring and display capabilities are obtained by accumulating large blocks of data to be transmitted to receiving terminals connected to the utilization device. Furthermore, the period of time that data is accumulated by such systems and the amount of data in such data blocks may be variable. Therefore, if the data communication system only allows to carry out periodic communications of essentially fixed-length messages to the terminals, and if one of the subsystems also has variable blocks of data ready for transfer at a time, state), but if other subsystems are not ready for data transmission at that time, data blocks from the "data ready" subsystem cannot be transmitted as a unit, and data transmission is disabled. Obviously, this results in limiting the speed of data communication and leaving the data communication medium idle for a considerable period of time.

Accordingly, it is an object of the present invention to provide a terminal device for use in an improved autonomous terminal data communication system.

Furthermore, the invention aims to provide a terminal device in a communication system that allows each terminal to periodically send messages on a data communication medium.

Furthermore, the invention aims to provide a terminal device in a communication system that allows each terminal to transmit variable length messages on a data communication medium.

A further object of the present invention is to provide a terminal device in a data communication system in which each terminal can periodically transmit data on a data communication medium.

Furthermore, the present invention provides a terminal device in a data communication system in which each terminal is capable of transmitting messages on a data communication medium aperiodically or periodically according to the status of message transmission by other terminals in the system. The purpose is to

Furthermore, it is an object of the invention to provide an autonomous terminal for a data communication system in which optimal utilization of the data communication medium is obtained based on all the conditions of message transmission by a particular terminal of the system.

SUMMARY OF THE INVENTION The above objects and other objects, as well as advantages apparent to those skilled in the art, are obtained by using a method in which a plurality of terminals are enabled to autonomously transmit data over a data communication medium. achieved.
Each terminal detects the absence of a message on the data communication medium. Sending of a message by a terminal is only possible when the following occur in succession: (i) the period of absence of the message on the data transmission medium is approximately equal to the synchronization gap common to all the plurality of terminals, and (ii) the period of absence of the message on the data transmission medium is terminal-specific; This is when it becomes substantially equal to the length of the terminal gap, which is shorter than the length of the synchronous gap (the length (period) of the synchronous gap is longer than the length (period) of the terminal gap).

In many cases, this method results in all terminals sending messages periodically, and the rate at which messages are sent from all terminals depends on the number of terminals sending messages, and It depends on the length of these messages. If only some terminals can actually send messages, the speed at which terminals can send messages is limited, so that the sending of a message by a terminal is substantially different from the terminal's previous message sending to all of the terminals. It is only additionally possible when a transmission interval of a predetermined length, which is the same as , has elapsed.

[Embodiments of the Invention] Referring to FIG. 1, the data communication system shown therein includes a plurality of utilization devices UD1.
-Data communication is performed between UD5. Actually, the devices used UD1 to UD5 are:
It consists of a plurality of aircraft systems, subsystems or computer-related devices such as a central processing unit (CPU), input/output (I/O) devices, displays, memory, etc. Each of the utilization devices UD1 to UD5 includes a device for transmitting data, a device for receiving data, or both. The data communication system is the device used.
It includes a plurality of terminals (devices) TL1 to TL5 connected to corresponding ones of UD1 to UD5, and also includes a common data communication medium to which the plurality of terminals TL1 to TL5 are connected. In the embodiment shown in FIG. 1 and described below, the data communication medium can take many forms, such as one or more electrical conductors, magnetic materials, waveguides, or fiber optic members.
Consists of bus DB. However, data communication media
There is no need to limit it to a physical device such as a data bus DB. Thus, the data communication medium may be any suitable carrier wave capable of carrying information by modulating it, such as waves or pulses of audio, radio, or optical frequencies.

In FIG. 1, each terminal connects to a data bus via a data communication link 10 and a bus coupler 13 for exchanging data with connected devices.
It has an output 12 connected to the data bus DB for conducting outgoing data and an input 14 connected to the data bus DB by a bus coupler 15 and receiving data present on the data bus DB. For example, data
The bus DB consists of a single twisted pair of wires reaching the physical locations of the utilized devices UD1 to UD5, and the bus couplers 13 and 14 are removable, each adapted to be inserted into a loop adjacent to the twisted pair of wires. It has a core member. These are described in Current Mode Data or Power Bus by Herzog, commonly assigned US Patent Application No. 957,746, filed November 6, 1978. In the embodiment shown in FIG. 1 (described below), the data bus DB
The data to be transmitted and received using the .DELTA. is in the form of a message consisting of one or more consecutive serial digital words.

Referring to FIG. 2, each terminal has a demodulator 16 which demodulates the messages received on data bus DB via coupler 15 and input 14 and provides the demodulated messages to receiver 18. The demodulated message is temporarily stored in the receiver 18,
Under the control of the terminal control unit 20, the data is sent in an appropriate format to the connected device. The terminal control unit 20 exchanges "interface connection" information with the device being used,
Provide the received data indicator to the utilizing device. Again, the terminal control unit 20 causes the transmitter 22 to receive the data in the form of a message consisting of one or more consecutive serial digital words at a time determined by the terminal control unit 20. Output the data received. Demodulator 24 modulates the message in the desired manner and outputs 12 and coupler 13.
The modulated message is supplied to the data bus DB via the data bus DB.

Typically, the receiver 18 of each terminal is enabled and the transmitter 22 is disabled. The terminal control units 20 of the plurality of terminals TL1-TL5 use the same and unique terminal control routine or protocol. This protocol allows only one terminal to transmit at a given time.

From this point of view, the data communication system described above is substantially the same as that described in US Pat. No. 4,199,663. The special protocol in the above-mentioned patent (hereinafter referred to as the A-mode protocol) also ensures that in steady state transmissions by all terminals occur at periodic transmission intervals.

Specifically, the A-mode protocol requires the following:

(a) The transmission interval of each terminal is the nominal time interval between the start of periodic data transmission by the terminal, and the length of the transmission interval of all terminals is substantially the same. (b) Each transmitting terminal is capable of transmitting one message containing appropriate synchronization, label, parity, and other information along with one or more data words at each communication interval. (c) when periodic transmissions by terminals are required, as long as the transmission period is fixed, and the duration of the messages of all terminals and the gaps between all messages and any expansion gaps necessary to accommodate additional terminals; Each message can be of any desired length, as long as the sum does not exceed the duration of each transmission interval. (d) interruptions in messages on the data bus specific to the transmitting terminal, i.e., "terminal gaps";
Each transmitting terminal begins transmitting a message only when a certain amount of time, approximately equal to the transmission interval, has elapsed since the terminal's previous message transmission. (e) The interword gap in every message is less than the length of the shortest terminal gap.

Since the A-mode protocol is specifically designed for periodic message transmission, its use in a data communication system of the type shown in FIG. 1 limits the ways in which message transmission can be performed. For example, the rate at which a terminal can send successive messages is limited by the transmission interval length. A small number of terminals (i.e. terminals TL1 and TL
2) is performing message transmission, the data bus DB will be idle for a considerable time (e.g., terminals TL3 to TL5 may be performing message transmission during that time);
It is clear that DBs are not being used in an optimal manner. Furthermore, the requirement that the sum of all terminal messages, terminal gaps, and extended gap periods do not exceed the length of all transmission intervals is a requirement that cannot be added to a data communication system unless the extended gap period is sufficiently long. Limit the number of sending terminals. If the duration of the extended gap is not long enough, the rate at which each terminal can send successive messages is further limited. Finally, the requirement that successive messages by each terminal be of constant duration, or length, limits the amount of data that any terminal can transmit at any given time.

To avoid these limitations when applied to data communication systems that do not require periodic message transmission, each terminal control unit 20 may also implement a second, or B-mode, protocol. This protocol requires: (a) Each transmitting terminal receives (i) the absence of a message on the data bus approximately equal to the length of the synchronization gap common to all terminals; and (ii) approximately the length of the terminal gap unique to that terminal. Message transmission is initiated only upon consecutive occurrences of the absence of a message on the equal data bus. (b) The length of the synchronous gap must be longer than that of all terminal gaps. (c) The intergap length of each message is shorter than that of the smallest terminal gap.

The need for a B-mode protocol can be included in each terminal control unit 20 by using circuitry as shown in FIG. Gap detector 3
2 receives demodulated messages from receiver 18 and provides an output signal only when no such message is present. Synchronous gap timer 34
is arranged to measure the length of the output signal from the gap detector 32, and only when the length of the output signal from the gap detector 32 becomes approximately equal to the synchronous gap common to all terminals, is the instantaneous timing detected. Outputs an output signal. If the output signal from gap detector 32 ends before the synchronization signal ends, timer 34 is reset internally. The output signal from synchronous gap 34 sets latch 36, which in turn enables AND gate 38 to pass the output signal of gap detector 32 to terminal gap timer 40. Therefore, when AND gate 38 is enabled, condition (i) of the B-mode protocol is satisfied, after which terminal gap timer 40 times the length of each output signal of gap detector 32. Thereafter, when the length of the output signal of the gap detector 32 exceeds the unique terminal gap assigned to the terminal, conditions (i) and (ii) of the B-mode protocol are satisfied.
are both satisfied, terminal gap timer 40 provides an instantaneous transmitter enable signal to transmitter 22, which allows transmitter 22 to transmit a message on data bus DB. . Gap detector 3
If the second output signal ends before the end gap ends, the end gap detector 40 is internally reset. The transmitter enable signal also resets latch 36, thus disabling AND gate 38. As a result, terminal gap detector 40 will thereafter detect the output signal of gap detector 32 until the absence of a message on data bus DB exceeds the synchronous gap and synchronous gap timer 34 again provides an output signal. It is never entered.

For a more detailed understanding of the operation of the data communication system in the B-mode protocol, reference should also be made to FIG. FIG. 3 is a timing diagram illustrating continuous multiple cycle operation of the data communication system.

Each terminal TL1-TL5 is capable of transmitting messages, each message containing one or more data words, each data word being of variable length and prefixed with a label identifying the data. There is. In the case of multiple data words, the data words are separated by inter gaps.
The cycle of operation shown in FIG. 3 includes consecutive cycles T11 and T12. Cycle T1
1, each terminal TL1-TL5 sends one message. That is, terminals TL1 to TL2,
TL3, TL4 and TL5 transmit messages M11, M21, M31, M41 and M51, respectively. Messages M11, M21, M41 and M51 each contain a single data word. The data words are of variable length and message M31 is separated by an inter-word gap and contains two data words of equal length. In cycle T12, only terminals TL1, TL2 and TL5 send messages, namely messages M12, M22 and M52, respectively. Each message of cycle T12 contains a single data word of variable length. Additionally, note that the lengths of messages M12 and M22 are different from the lengths of corresponding messages M11 and M21. As shown, cycle T11 is the terminal
It follows the message M50 of TL5,
Cycle T12 is message M13 of terminal TL1
is followed by

The terminal control unit 20 of each terminal TL1-TL5 establishes (via its terminal gap timer 40) a gap specific to the connected terminal. That is, gaps TG1, TG2, TG3, TG4 and TG5
correspond to terminals TL1, TL2, TL3, TL4 and TL5, respectively (however, tg1<tg2<tg3<
tg4<tg5). The terminal control unit 20 of each terminal TL1-TL5 also establishes (through its synchronization gap timer 34) a synchronization gap common to all terminals. Assume that all latches 36 have been reset at the end of message M50. Then, due to the absence of messages on the data bus DB,
Synchronous gap timer 34 of each terminal TL1 to TL5
starts timing. When a time equal to the synchronous gap has elapsed, each synchronous gap timer 34 provides an output signal to the latch 36 connected to it.
Reset. As a result, each and gate 3
8 is enabled, so each terminal gap timer 40 begins timer operation and cycles T11.
Start. When a time equal to terminal gap tg1 has elapsed, terminal gap timer 4 of terminal TL1
0 provides a transmission enable signal which causes the transmitter of terminal TL1 to begin transmitting message M11 and resets latch 36 of terminal TL1, thereby disabling AND gate 38 of terminal TL1 and its activation. Disable terminal gap timer 40. Therefore, continuous message transmission of terminal TL1 cannot be carried out until the next synchronization gap is detected. At terminals TL2-TL5, latch 36 remains set, indicating that a synchronization gap has been detected and no message has yet been transmitted by these terminals. moreover,
Since the start of message M11 causes each terminal's gap detector 32 to stop supplying its output signal, all synchronous gap timers 34 and terminal gap timers 40 stop timer operation;
(reset internally).

At the end of message M11, terminals TL2 to TL5
starts the timer operation again. terminal gap tg2
, terminal gap timer 40 of terminal TL2 provides a transmitter enable signal to cause the transmitter of terminal TL2 to begin transmitting message M21, causing message M21 to reset latch 36 of terminal TL2. . It is clear that the terminal gap timers 40 of terminals TL3-TL5 stop running (reset) at the start of message M21, but latch 36 remains set.

As shown, the terminal gap tg3, tg4 and
If there are no messages for a period equal to tg5, terminals TL3, TL4 and TL5 continuously transmit messages M31, M41 and M51. Continuous data in message M31
Since the inter-word gap is chosen to be shorter than any of the terminal gaps,
Terminal gap timer 4 for terminals TL4 and TL5
0 ends the transmission of the first data word of message M31 and starts the second data word of message M31.
It can also be seen that the timer operation does not end even if word transmission is started.

At the end of message M51, terminals TL1 to TL5
latches 36 are reset, which disables each AND gate 38, so that each terminal gap timer 40 does not start its timer operation. When a time equal to the sync gap has elapsed, each sync gap timer 34 provides an output signal to set the latch 36 connected to it. As a result, all AND gates 38 are enabled and all terminal gap timers 40 begin timer operation, terminating cycle T11 and beginning cycle T12. In cycle T12, terminals TL1 and
TL2 sends messages M12 and M22 in a manner similar to that described above after successive terminal gaps tg1 and tg2 have elapsed. Message M2
2, the latches 36 of terminals TL1 and TL2 are reset and the latches 36 of terminals TL3-TL5 remain set. As a result, the terminal
The AND gates 38 of TL3-TL5 remain enabled and their terminal gap timers 40 begin timer operation at the conclusion of message M22. After a time equal to the terminal gap tg2,
Terminal gap timer 40 of terminal TL3 provides a transmitter enable signal (which resets latch 36). However, terminal TL3 does not actually perform any transmission in response to this transmitter enable signal. As a result, the terminal
AND gates 38 of TL4 and TL5 remain enabled. After a time (from the end of message M22) equal to the terminal gap tg4,
Terminal gap timer 40 of terminal TL4 provides a transmitter enable signal (which resets latch 36). However, terminal TL4 does not transmit a message in response to this transmitter enable signal. As a result, the terminal
TL5's AND gate 38 remains enabled and its terminal gap timer 40 continues to time. After a time (from the end of message M22) equal to terminal gap tg5, terminal gap timer 40 of terminal TL5 provides a transmitter enable signal (which resets latch 36). As a result, the transmitter of terminal TL5 starts transmitting message M52. At the end of message M52, all latches 36 are reset, and when a time equal to the sync gap has elapsed, each sync gap timer 34 provides an output signal that causes the connected latch 36 to be set. , each AND gate 38 is re-enabled. Therefore, the cycle T12 ends and the next cycle starts (during this period, the terminal TL1 is in the terminal gap).
After passing TG1, message M13 is sent, and so on).

As is clear from FIG. 3, the B-mode protocol allows each terminal to transmit messages continuously as long as the same terminal or terminals are transmitting messages consecutively and the lengths of consecutive messages from the terminals are approximately equal. It transmits continuous messages almost periodically. However, as shown in FIG. 3, the B-mode protocol is more likely to send messages aperiodically. In this case, the interval between messages M11 and M12 (for example, the interval of cycle T11) is equal to the interval between messages M12 and M12.
13 (interval of cycle T12). Based on the B-mode protocol, the rate at which a terminal sends a message depends on the number of terminals sending the message and the length of the message. As the number of sending terminals and message length increases, the transmission rate decreases.
Similarly, as the number of transmitting terminals and/or message length decreases, the transmission rate increases. Optimal utilization of the data bus DB is obtained by the B-mode protocol, which requires at least one
Synchronization gap and longest terminal gap (i.e., assuming one terminal is transmitting)
It is clear that the data bus is free for a maximum time equal to the sum of the synchronization gap and the longest terminal gap (eg tg1). Since the B-mode protocol imposes only the condition that there are no messages on the data bus, the length of consecutive messages from each terminal can be arbitrary. Finally, a data communication system operating based on a B-mode protocol cannot provide an expansion gap in an A-mode protocol without resetting the transmission interval or causing a reduction in the message transmission rate as described above. It is applicable to any number of transmitting terminals.

In some situations, FIGS. 7, 8, 9A
It is desirable to implement an A-mode protocol, a B-mode protocol, or a combination thereof, which are specifically referenced in connection with the description of the protocol control unit of FIG. 9B.

It is clear that since the receiver 18 of each terminal TL1-TL5 is enabled successively, messages on the data bus DB can be detected by the connected terminal and forwarded with appropriate identification to the utilizing device of the connection thereto.

It is important that the B-mode protocol is strictly adhered to so that only one terminal is in transmit mode at each time. Therefore, the synchronous gap timer 34 and the terminal gap timer at all terminals
Since timer 40 has a stable time reference, the synchronization gap cannot be shorter than the terminal gap of each terminal, and it is necessary that the terminal gap of each terminal not be close to that of the other terminals. Finally, the time base establishing the intergap for each terminal must be stable so that the intergap for all terminals is the same or does not exceed all terminals.

For monitoring according to the B-mode protocol, each terminal has a terminal monitor 40 (FIG. 2);
Signals are inputted to this from a receiver 18, a terminal control unit 20, and a transmitter 22.
Each terminal monitor 40 has an independent time base that establishes the desired interword gaps, terminal gaps, and synchronization gaps for its attached terminals. Additionally, the terminal monitor 40 monitors the connected terminal's control unit (e.g., synchronous gap timer 34).
and the desired interword gap established by the actual interword gap, terminal gap and synchronization gap provided by the timers of terminal gap timer 40) and their independent time references.
It has a circuit that compares the gap, the terminal gap and the synchronous gap. If these comparisons do not match, the terminal monitor 40
A signal is provided to enable switch 42, which powers down modulator 24 and inhibits further transmission by the connected terminal.

To further explain the operation of the data communication system, the configuration and operation of simplified terminals TL1 to TL5 will be explained.

In FIG. 5, the data bus DB consists of a twisted pair of wires 100 reaching all terminals, and the ends of the twisted pair wires (not shown) are shorted so that the data bus DB is a single continuous wire. Configure the current loop. The messages on the data bus DB have a current form and are connected to each sending terminal via the connected bus coupler 102,
Bus coupler 102 includes a core 104 having a separable core member, the ends of which are twisted.
inserted into two adjacent loops formed by wire pairs 100, so that each wire is connected to the bus
It forms one turn of the primary winding of coupler 102. A secondary winding 106 is also wound around the core 104 and includes a terminal stub 10 of twisted wire pairs.
8 is correspondingly connected to the transmitting terminal.

The terminal stub 108 is connected to the demodulator 11 within the terminal.
The input of 0 and the output of demodulator 112 are commonly connected. The signal of demodulator 110 represents the demodulated message and is the signal DMR applied to the input of receiver 114. The configuration and operation of receiver 114 will be explained below with reference to FIG. The output of the receiver 114 is derived from the signal ADA, which occurs when no message is present on the data bus DB, and the output signal DR, which represents the data in the valid message received by the receiver addressing the terminal (by the labels already described). Become. The output signal DR may be in parallel or serial digital form. The interface unit 116 is provided for exchanging data between the terminal and the utilization device 118 connected thereto. In response to the interface receive control signal of receiver 114, the received data represented by output signal DR is sent to interface unit 116.
is memorized. This received data is converted into a desired format within the interface unit 116 and then transferred to the utilization device 118.

The usage device 118 is an interface
Provides data to be transmitted to unit 116 in an appropriate format. The data to be transmitted is stored in the interface unit 116, converted to parallel or serial form as appropriate, and transmitted to the interface transmit control signal ITC of the transmitter 120.
Output signal DT to transmitter 120 in response to
will be transferred as The transmitter 120 is responsive to the signal ADA of the receiver 114 and outputs outputs representing the data to be transmitted of the terminal, labels or addresses, and other data such as synchronization and parity information at times determined by the protocol in use. Outputs the signal DM in serial digital format. The signals DM and T of the transmitter 120 are applied to a modulator 112 which has three states at its output. During periods when signal T is not present, the output of modulator 112 has a high impedance so as to disconnect the modulator from data bus DB. During the period in which signal T is present, establishing transmission of a message from the terminal, the output of modulator 112 provides an output signal that alternates between first and second levels in response to signal DM. The first and second levels are positive and negative, respectively. The output signal of modulator 112 is fed directly to the input of demodulator 110 and also to terminal stub 1.
08 and bus coupler 102.
Supplied to bus DB.

As detailed in U.S. Pat. No. 4,199,663, the transmission format of each message may be Manchester-by-phase level modulation.
In this modulation, consecutive positive and negative levels in the output signal of modulator 112 represent a "1", and consecutive negative and positive levels in the output signal of modulator 112 represent a "0".

Referring to FIG. 6, modulator 110 and receiver 114 include an amplifier 130. Referring to FIG. Amplifier 130 provides a POS(+) output during each positive level of the signal on data bus DB, and also provides a POS(+) output during each positive level of the signal on data bus DB.
NEG (-) during each negative level period of the signal on bus DB
Provides output. Amplifier 140 in all other periods
does not derive any output. The POS and NEG outputs of amplifier 130 are fed to corresponding inputs of OR gate 132, and the output of OR gate 132 is connected to the signal
It is ADA. POS or NEG output is amplifier 13
When supplied from 0, signal ADA is at a high logic level, meaning that a message is present on data bus DB. of amplifier 130
When neither POS output nor NEG output exists, the signal
ADA goes to low logic level and data bus DB
Indicates that there is no message above.

Referring now to the embodiment of modulator 112 and transmitter 120 in FIG.
ADA is supplied to a protocol control unit 140 which also receives a transmit clock signal XXL from a transmit clock 142. The protocol control unit 140 (a particular embodiment is described below with reference to FIG. 8) controls the protocol in use (which is
mode protocol, B-mode protocol, or a combination thereof) and, if so, output to data buffer, encoder and interface control circuitry 144 and line driver 146. The terminal outputs a signal T and starts sending a message. Before this time, the circuit 144 activates the connection via the interface unit 116 by providing the signal IRC to the interface unit 116 and by receiving the data to be sent on the output signal DT. It obtains the data to be transmitted from device 118 and encodes the data with synchronization, labels, parity, and other information into the appropriate message format. The message encoded in response to the output signal T is the signal
Provided as DM to line driver 146. This signal DM has successive first and second logic levels corresponding to encoded information. During periods when signal T is not present, line driver 146
The output of the modulator (consisting of modulator 112 of FIG. 5) is tri-state or high impedance.
When signal T is present, line driver 14
6 converts each first logic level of the signal DM of the data buffer, encoder and interface control circuit 144 into a corresponding positive level, and also converts each second logic level of the signal DM into a corresponding negative level. . At the end of the message transmission, circuit 144 controls protocol control unit 1.
40, and protocol control unit 140 responds by terminating signal T to return the output of line driver 146 to its tri-state level. Data buffer, encoder and interface control circuit 144
Although it can take many forms, one particular embodiment useful for generating fixed length messages having a predetermined message format can be seen in FIG. 7 of U.S. Pat. No. 4,199,663.

Referring again to FIG. 6, the signal of receiver 114
ADA is applied to the input of a clock control circuit 150 consisting of an R/S flip-flop. signal
When ADA goes to a low logic level meaning there is no message on data bus DB, clock control circuit 150 is set to the first state and its output signal R goes to a high logic level. Signal R is provided to receiver clock 152, and when signal R is at a high logic level, receiver clock 152 operates to output a receiver clock signal RCL. Signal RCL and amplifier 1
30 are both provided to corresponding inputs of a data buffer, decoder and interface control circuit 154, and in response, the data buffer, decoder and interface control circuit 154 adjusts the continuous level of the signal at the POS output. Stores message information represented by . The circuit 154 decodes the information of the stored message and also performs certain tests for synchronization, label and parity information, and when the tests are satisfied, outputs a signal via the output signal DR under the control of the signal IRC. Message data is provided to interface unit 116. When a valid and properly addressed message is detected by circuit 154, signal SPD is output and clock control circuit 1
50 to its second state. This causes signal R to go to a low logic level, disabling receiver clock 152 and terminating further transfers of information to circuit 154. Although the data buffer, decoder and interface control circuit 154 can take many forms, one particular embodiment useful for fixed length messages having a predetermined message format is shown in FIG. 6 of U.S. Pat. No. 4,199,663. I can do it.

Referring to FIG. 8, one particular embodiment of protocol control unit 140 (FIG. 7) includes a synchronous gap timer, a transmission interval timer, and a terminal gap timer. The synchronous gap timer includes a comparator 160, a counter 162, a plurality of select switches 164, an inverting amplifier 166, and an AND gate 168. Transmission interval/
The timer includes a comparator 170, a counter 172, a plurality of select switches 174, an inverting amplifier 176, an AND gate 178, an AND gate 180, and a switch 182. Also, the terminal gap
The timer includes a comparator 190, a counter 192, an inverting amplifier 196 and an AND gate 198.

Turning to the synchronous gap timer, counter 162 is a multi-bit (eg, 8-bit) digital counter. The counter in counter 162 is cleared and remains in that state when signal ADA (applied to the CLR input of counter 162) is at a high logic level (meaning a message is present on the data bus). , is incremented by the output of AND gate 168 (applied to the clock or C input of counter 162). The comparator 160 is a multi-bit (for example, 8-bit) comparator, and has a plurality of first inputs connected to each stage of the counter 162 and one of the plurality of selection switches 164, respectively. and a plurality of second inputs. Comparator 160
serves to compare the count value in counter 162 with a desired count value representing the length of the synchronization gap determined by setting the plurality of selection switches 164. The output signal of comparator 160 is passed through inverting amplifier 166 to AND gate 1.
68 and also the OR gate 1
67 (the function of which will be explained below) is applied to the set input of latch 169, and the transmit clock signal XXL is applied to the second input of AND gate 168.

Assume that the absence of a message on the data bus occurs and signal ADA goes to a low logic level. Since counter 162 has already been cleared, the count value in counter 162 does not correspond to the desired count value set on selection switch 164. Therefore, the output of comparator 160 will be a low logic level, thereby enabling AND gate 168 (via inverting amplifier 166). Thereafter, the count value in counter 162 is incremented at a rate determined by successive pulses of signal XXL. If the absence of a message on the data bus continues, that is, if signal ADA remains at a low logic level, the count value in counter 162 will change to the desired count value set by selection switch 164 at a time corresponding to the desired synchronization gap. , the output signal of comparator 160 is at a high logic level, and AND gate 168
Disable. Therefore, the comparator 160
The output signal of is held at a high logic level. In response to the high logic level of the output signal of comparator 160, latch 169 is set and its output signal BIU goes to a high logic level, indicating that a synchronization gap for the terminal has been detected. If a message appears on the data bus before the synchronization gap is removed, the result is that latch 169 is set because the high logic level of signal ADA clears counter 162 before performing the comparison described above.

Referring now to the terminal gap timer, counter 192 is a multi-bit (e.g., 8-bit) digital counter whose count value is cleared when signal ADA (supplied to the counter's CLR input) goes to a high logic level. is,
It is incremented by the output of AND gate 198 (which is fed to the clock or C input of counter 192). Comparator 190 is a multi-bit (e.g., 8-bit) comparator, and counter 192
and a desired count value representing the terminal gap for the terminal determined by the settings of the plurality of selection switches 194. When these two count values match, the output signal TGU of the comparator 190 becomes a high logic level. output signal
TGU is provided through an inverting amplifier 196 to a first input of an AND gate 198 (latch 169
) signal BIU is the second of AND gate 198
The transmitter clock signal is supplied to the input
XXL is provided to the third input of AND gate 198.

Assume that the message on data bus DB has disappeared and signal ADA has just gone to a low logic level. Counter 192 is already cleared by the high logic level of signal ADA, so it can count, but AND gate 198
It is disabled until the BIU goes to a high logic level, indicating that the aforementioned synchronization gap has been detected. Therefore, when a synchronous gap has not yet been detected, counter 192 will output a signal
Remains cleared even when ADA goes to a low logic level. Since the count in counter 192 does not match the desired count value for the terminal gap set by selection switch 194, signal TGU
holds a low logic level. Assuming that a synchronization gap is detected and therefore signal BIU goes to a high logic level, when signal ADA is at a low logic level, the count in counter 192 is
It is clear that it increases at a rate determined by successive pulses of XXL. When no message is present on the data bus DB for a time equal to the terminal gap, that is, when signal ADA holds a low logic level for a period equal to the terminal gap, the count value in counter 192 is equal to the desired count value representing the terminal gap. In response to the signal
Since TGU goes to a high logic level, closing AND gate 198, signal TGU remains at a high logic level, indicating that a terminal gap for the terminal has been detected. However, if a message appears on data bus DB before a terminal gap is detected, counter 192 is cleared in response to a high logic level on signal ADA and the message on data bus DB is Repeat the counting operation explained in .

Transmission interval timer signals BIU, TGU
and AIU are each provided to corresponding inputs of AND gate 200. Assuming only the B-mode protocol of the protocol control unit is being executed, the signal AIU remains at a high logic level, as will be apparent from the following description. Therefore, the synchronization gap and the terminal gap for the terminal in question are detected and the signals BIU and
When indicated by a high logic level on TGU, the output signal STX of AND gate 200 will be at a high logic level. Output signal STX is provided to the set input of latch 202 and the reset input of latch 169. When the protocol in operation is satisfied by the protocol control unit (e.g., B-mode protocol), the result is that a high logic level on signal STX sets latch 202 to output signal T, which sends the message as described above. enable the transmission of A high logic level on signal STX also resets latch 169, so
Signal BIU goes to a low logic level, disabling the terminal gap timer AND gate 198 and returning signal STX to a low logic level. Therefore, once the B-mode protocol (signal T) allows a message to be sent,
Other message transmissions by the terminal are disabled until a synchronization gap and a terminal gap for the terminal are consecutively detected. When a message is sent by the terminal in response to signal T, the beginning of the message causes signal ADA to go to a high logic level, so counters 162 and 192 are cleared, and then signal ADA (e.g., at the end of the message) Remains cleared until it reaches a low logic level. When the message transmission by the terminal is completed, the data buffer, encoder and interface circuit 144 (FIG. 7)
Signal SPX resets latch 202 and outputs signal T.
goes to a low logic level, causing line driver 146 (FIG. 7) to return to the tri-state level.

In some applications, the A-mode protocol,
Alternatively, various combinations of A-mode and B-mode protocols are preferably implemented. For this reason, the transmission interval timer includes a counter 172 with a large number of bits (for example, 8 bits), and the count value is (counter 17
is cleared when the output of AND gate 180 (supplied to the CLR input of counter 172) goes to a high logic level, and by the output of AND gate 178 (supplied to the clock or C input of counter 172). will be increased. The input to AND gate 180 is signal STX, which is provided by switch 182. Comparator 170 is a multi-bit (e.g., 8-bit) comparator that compares the count value of counter 172 to a desired count value representing a desired transmission interval determined by the settings of a plurality of selection switches 174. When the counts do not match, the output signal of comparator 170 goes to a low logic level, enabling AND gate 178 via inverting amplifier 176. When both count values match, the output signal of comparator 170 becomes a high logic level. The output signal of comparator 170 is provided to the input of AND gate 200 via OR gate 177 (the function of which will be explained below) as signal AIU.

Assume that an A-mode protocol or a combination of A-mode and B-mode protocols is implemented. In this case, switch 1
82 is left open. Once the message transmission is enabled by the terminal, the signal STX
is at a high logic level, counter 172 is cleared. Shortly after signal STX goes to a low logic level, counter 172 is enabled. When the count value of counter 172 does not match the desired count value representing the transmission interval set in selection switch 174, comparator 170
Since the output signal of is at a low logic level,
AND gate 178 is enabled so that the count value of counter 172 is then
Increase at a rate determined by successive pulses of XXL. It should be noted that the count value of counter 172 is incremented regardless of the presence or absence of a message on data bus DB. Once the transmit interval has elapsed, the output signal of comparator 170 and signal AIU both go to a high logic level, disabling AND gate 178 and keeping signal AIU at a high logic level, since the two count values match. Ru. Assuming that signals BIU and TGI were at a high logic level when signal AIU was at a high logic level, AND gate 20
It is apparent that since the zero signal STX goes to a high logic level, latch 202 enables the terminal to send a message (via signal T) and also clears counter 172 (via AND gate 180).

It is clear that the embodiment of protocol control unit 140 of FIG. 8 can be used to execute only A-mode protocols, only B-mode protocols, or a combination of A-mode and B-mode protocols. be. To run only the A-mode protocol, all selection switches 164 are closed (the desired count value representing the synchronization gap is 0), counter 182 is open, and selection switches 174 and 194 are closed during the transmit interval (this (length is approximately the same for all terminals) and terminal gap (whose length is terminal specific) to represent the desired count value. Since the count value set by selection switch 164 is now zero, it is clear that the output signal of comparator 160 will always remain at a high logic level and therefore latch 169 will remain set at all times. Therefore, the signal
Since the BIU holds a high logic level (signal
The message transmission (by the high logic level of STX) is determined by the elapse of the transmission interval from the terminal's previous transmission (represented by the high logic level of signal AIU) and the elapse of the synchronization gap (represented by the high logic level of signal TGU). This is possible only when both are satisfied.

To run only the B-mode protocol, close switch 182 or close selection switch 174 and set the desired synchronization gap (common to all terminals) and the desired terminal gap for the terminal (terminal-specific). Select switch 16 as shown
4 and 194. Selection switch 17
Since the desired count value set to 4 is now 0, or because counter 172 cannot be cleared by signal STX (because AND gate 180 is disabled), signal AIU is held at a high logic level, but Thus, the transmission of a message follows the passage of a synchronization gap (represented by a high logic level on signal BIU), followed by a synchronization gap (represented by a high logic level on signal BIU)
It is only possible to start when a terminal gap has passed (represented by a high logic level on TGU).

To perform a combination of A-mode and B-mode protocols, counter 18
2 open and selection switches 164, 174, and 194 set to represent the desired terminal gap, desired transmit interval, and desired terminal gap, respectively. In this combination protocol, the terminal gap assigned to each unit must be unique, and the synchronization gap and transmission interval length must be common to all terminals. The number of transmitting terminals and the message length of such transmitting terminals, together with the synchronization gap and the length of the transmission interval, are such that the successive message transmissions of the terminals are
As is clear from the timing diagram in the figure, it is determined whether the periodicity (A mode) or aperiodic (B mode) is used.

The data communication system is connected to terminals TL1 to TL5 (first
(see figure) and the terminal gap related to the terminal.
tg1 to tg5 have a predetermined relationship (tg1<tg2<tg3<tg4<
tg5) and the synchronous gap is longer than the longest terminal gap, e.g. tg5, the length of the transmission interval is longer than the synchronous gap, and all terminals are sending messages, then all messages, terminal gaps and synchronous gaps Assume that it is shorter than the sum of .

In FIG. 9A, terminals TL1 and TL2 are the only "active" terminals transmitting messages;
Assume that the remaining terminals TL3-TL5 are "inactive" and de-energized. Message M11
At the beginning of , latch 169 of terminal TL1 is reset, disabling its terminal gap timer and also disabling its transmit interval timer (by clearing counter 172 as described above).
It is reset and starts the transmission interval T11. At the beginning of message M21, latch 169 is reset, disabling its terminal gap timer, and its transmit interval timer is also reset (by clearing counter 172, as described above), causing transmit interval T21 to be reset.
Start. For each message M11 and M21, the terminal's synchronization gap timer is reset.

After the termination of message M21, there are no messages on the data bus for a time approximately equal to the synchronization gap. When the synchronous gap has elapsed, the output signal of each synchronous gap timer goes to a high logic level, so that the latch 169 of terminals TL1 and TL2
is set. As a result, the signal BIU at each terminal will be at a high logic level (the corresponding AND).
gate 198) enables each terminal gap timer. After this, there is still no message on the data bus. When the terminal gap tg1 passes (after passing the synchronization gap), the terminal
The signal TGU of TL1 goes to a high logic level. However, since the transmission interval T11 has not yet ended, the signal AIU of the terminal TL1 remains at a low logic level. When the terminal gap TG2 has elapsed (after the synchronous gap has elapsed), the signal at the terminal TL2
TGU also goes to high logic level. However, since the transmission interval T21 has not yet ended, the signal at the terminal TL2 remains at a low logic level. The transmission interval T11 ends at the next time, and the terminal
Signals BIU, AIU and TGU of TL1 go to high logic level. Meanwhile, signal STX goes to a high logic level, setting latch 202 and locking latch 169.
and resets the transmission interval timer to start transmission interval T12. In response to signal T12, terminal TL1 sends message M1
2, the synchronous gap timer and the terminal gap timers of terminals TL1 and TL2 are reset. At the end of message M12, the terminal gap timer of terminal TL1 is
Since signal BIU is at a low logic level (due to the reset of latch 169), it is disabled. However, the terminal gap timer of terminal TL2 remains enabled. data bus
If there is no message on the DB for a period approximately equal to the terminal gap tg2, the signal TGU at the terminal TL2 goes to a high logic level. At this point, the transmission interval T21 has also elapsed, so the terminal TL2
The signal AIU also goes to a high logic level. At this point, signals BIU, AIU, and TGU at terminal TL2 are each at a high logic level, so signal STX goes to a high logic level, setting latch 202, resetting latch 169, and resetting the transmit interval timer. transmission interval T2
Start 2.

After the end of message M22, the operation of the device proceeds in a similar manner to that described above. After the synchronous gap has elapsed, latch 1 of terminals TL1 and TL2
69 is set, and when the terminal gap tg1 and the transmission interval T12 have elapsed (transmission interval T13 has started), the terminal TL1 starts transmitting the message M13. Also, the terminal gap TG
2 and transmission interval T22 have elapsed (transmission interval T23 has started), the terminal TL
2 starts sending the message M23.

While message M23 is being sent, terminal TL3 is activated, so terminal TL3 transmits message M2.
It is waiting so that it can start sending messages at the end of step 3. Referring again to FIG. 8, the output signals of latches 204 and 206 are connected to OR gate 1.
67 and 177, respectively. The latches 204 and 206 are connected to the input signal.
It is set in response to a high logic level on PU (bringing its output signal to a high logic level) and reset in response to a high logic level on signal STX (bringing its output signal to a low logic level). When the terminal is energized, signal PU is brought to a high logic level for a short period (by means not shown), so that latch 2
04 and 206 are set. Latch 204
A high logic level on the output signal of , thereby setting latch 169 (by OR gate 167) to indicate that a synchronous gap has been "detected";
Also enables the terminal gap timer in the terminal. The high logic level of the output signal of latch 206 causes the signal AIU (via OR gate 177) to
is set to a high logic level to indicate "detection" of a transmission interval for the terminal.

Returning to the explanation of FIG. 9A. At the end of message M23, latches 169 of terminals TL1 and TL2 are reset and latch 169 of terminal TL3 is set, so that the terminal gap timers of terminals TL1 and TL2 are disabled and the terminal gap timer of terminal TL3 is enabled. I can see that. The transmission interval timers of terminals TL1 and TL2 are (transmission intervals T13 and T
23 has not yet expired), it operates a timer and "detects" the passage of the transmission interval for terminal TL3, for example the signal AIU of terminal TL3 goes to a high logic level. After the end of message M23, no message is present on the data bus DB. When terminal gap tg3 ends, terminal TL3
The signal TGU becomes a high logic level. At this point, the signals BIU, AIU and TGU of terminal TL3 are each at a high logic level, which causes the signal
STX goes to a high logic level, setting latch 202 and setting each latch 169, 204 and 206.
and resets the transmission interval timer to start transmission interval T33.
In response to signal T, terminal TL3 sends message M33
will start sending, so terminals TL1, TL2 and
The TL3 synchronous gap timer and terminal gap timer are reset. Message M33
At the end, the latches 169 of terminals TL1, TL2 and TL3 are reset so that their terminal gap timers are disabled. After message M33 ends, the message is
It does not exist on the bus DB. After the end of message M33, communication intervals T13 and T2
3 has elapsed, the signals of terminals TL1 and TL2
The AIU goes to a high logic level and remains there.
However, since latch 169 has been reset, indicating that a synchronization gap has not yet been detected, terminals TL1 and TL2 are unable to send messages at this time. (Message M3
When the synchronous gap has elapsed (after the end of 3), the output signal of each synchronous gap timer goes to a high logic level, so that the latch 169 of each terminal TL1, TL2 and TL3 is set. As a result, each terminal's signal BIU goes to a high logic level, thereby enabling each terminal gap timer. When the terminal gap tg1 has elapsed (after the synchronization gap has elapsed), the signal TGU at the terminal TL1 goes to a high logic level. At this point, the signals BIU, AIU and TGU of terminal TL1 are at high logic level, so
Terminal TL1 starts sending message M14,
This action resets latch 169 and resets the transmit interval timer to begin the next transmit interval. Message M14 ends after terminal gap tg2 has elapsed, so terminal TL
2 begins transmitting message M24 and operates as described above to reset latch 169, reset the transmit interval timer, and begin the next transmit interval. When it comes time to start message M24, transmission interval T33 has elapsed. Therefore, the signals BIU of terminal TL3 and
Even though AIU is at a high logic level, the signal TGU is not present because the terminal gap tg3 has not yet elapsed, and therefore the terminal TL3 cannot send a message at this point. When terminal gap tg3 has elapsed following the end of message M24, each signal BIU, AIU and TGU of terminal TL3
goes to a high logic level, terminal TL3 starts transmitting message M34, and this action resets latch 169 and sets the transmission interval.
Reset the timer and start the next transmit interval timer. Thereafter, the operation of the device proceeds in the same way.

Reference is now made to FIG. 9B. It is assumed that the device operates in a similar manner as already described with reference to FIG. 9A until the end of message M23.
Also, when terminal TL3 is energized (instead of being set by latch 204 as described above, it is set by means not shown in FIG.
69 is reset and latch 206 is set as described above. As a result, the signal of terminal TL3
BIU and TGU each go to a low logic level, the terminal gap timer of terminal TL3 is disabled, and its signal AIU goes to a high logic level. After the message M23 ends, there is no message on the data bus DB. Once the synchronization gap has elapsed, the terminal's latch 169 is set so that the terminal gap timers are respectively enabled. (after the sync gap has passed)
After the terminal gap tg1 has elapsed, the signal TGU at the terminal TL1 goes to a high logic level. However, since the transmission interval T13 has not yet passed,
The signal AIU of terminal TL1 maintains a low logic level. When the terminal gap tg2 has elapsed (after the synchronous gap has elapsed), the terminal gap of terminal TL2 is
TGU also becomes high logic level. However, since the transmission interval T23 has not yet elapsed, the signal AIU of the terminal TL2 remains at a low logic level. When the terminal gap tg3 has elapsed (after the synchronization gap has elapsed), the signal TGU at the terminal TL3 goes to a high logic level. At this point, terminal TL3's signals BIU, AIU, and TGU are logic high, so terminal TL3 begins transmitting message M34, which resets latch 169 and disables its terminal gap timer. Reset the latch 206 and reset the transmit interval timer to set the transmit interval T.
Start 34.

In the transmission of message M34, transmission intervals T13 and T23 end one after another.
However, terminals TL1 and TL2 receive message M3
4, and terminals TL1 and TL2 are unable to send messages at this time. At the end of message M34, the latches 169 of terminals TL1 and TL2 remain set, so their terminal gap timers are enabled. When the terminal gap tg1 elapses, the terminal TL
1's signals BIU, AIU and TGU go to a high logic level, terminal TL1 starts transmitting message M14, and this action causes its latch 16 to
9 and resets its transmission interval timer to begin transmission interval T14. After message M14 ends, the terminal gap
After tg2 elapses, each signal TIU of terminal TL2,
AIU and TGU will be at high logic level, so
Terminal TL2 starts sending message M24,
This action resets the latch 169 and resets the transmit interval timer to begin transmit interval T24.

After message M24 ends, there are no messages on the data bus. (Message M24
(after the end of ) at which point the synchronous gap has not elapsed,
Although the transmission interval T34 ends, the terminal TL
Since the latch 169 of TL3 has been reset, terminal TL3 does not send a message. After the synchronization gap has elapsed, terminals TL1, TL2 and TL
3 latches 169 are set so that each terminal gap timer is enabled. When the terminal gap tg1 has elapsed (after the synchronization gap has elapsed), the signal TGU at the terminal TL1 goes to a high logic level. However, since the transmission interval T14 has not yet elapsed, the signal AIU of the terminal TL1 remains at a low logic level. (after the sync gap has elapsed)
When the terminal gap tg2 has elapsed, the signal TGU of the terminal TL2 also goes to a high logic level. However, since the transmission interval T24 has not yet passed,
The signal AIU at terminal TL2 holds a low logic level (after the synchronization gap has elapsed) when terminal gap tg3
When , the signal TGU at terminal TL3 goes to a high logic level. At this point, terminal TL3 has each signal
Since BIU, AIU, and TGU go to a high logic level, terminal TL3 begins transmitting message M35, which action resets latch 179 and resets its transmission interval timer to begin successive transmission intervals. . Transmission intervals T14 and T24 are message M3
5, the terminal gap tg1 elapses after the end of the message M35, the terminal TL
1 starts sending message M15. Also,
When a terminal gap tg2 has elapsed after the termination of message M15, terminal TL2 starts transmitting message M25.

From FIG. 9A it can be seen that the initial message transmission by terminals TL1 and TL2 is periodic. That is, the lengths of the interval between messages M11 and M12, the interval between messages M12 and M13, and the interval between messages M22 and M23 are approximately equal. Therefore,
The first portion of the timing diagram of FIGS. 9A and 9B shows that message communication is using an A-mode protocol controlled data communication system. However, messages M13, M2
Since the terminal TL3 sends the message M33 after the message M33, it can be seen that the messages after the terminals TL1 and TL2 are asynchronous with respect to the initial message. That is, message M13,M
The interval between 14 is the message M12, M1
3, and the interval between messages M23 and M24 is greater than the interval between messages M23 and M24.
22, which is larger than the interval between M23. Accordingly, the final portion of the timing diagram of FIG. 9A shows that message transmission is using a data communication system controlled by the B-mode protocol.

Comparing Figures 9A and 9B, it can be seen that ``detecting'' a synchronous gap (Figure 9A) or ``detecting'' a synchronous gap (Figure 9B) of a terminal that has just been energized. It can also be seen that it affects not only the actual time at which the first message of a newly active terminal is allowed, but also the order and rate of successive message transmissions by all subsequently active terminals. It can be seen that in both situations, the transmission interval timer of each terminal is no longer able to control the rate at which messages are sent by that timer, so that continuous message transmission can only be performed when the synchronization gap and terminal gap of that terminal have elapsed. Using such a combination of protocols limits the rate at which messages are sent by each terminal to the rate determined by the communication interval, but allows the data communication system to handle variable length messages and/or message transmission by additional terminals. It is also clear that this can be done.

As described above, according to the present invention, a new transmission cycle is entered when there is no continuous data on the data transmission medium for a time interval commonly determined for each terminal, that is, a "synchronization gap"; The configuration is such that the corresponding terminal can transmit data when a "terminal gap" unique to each terminal has elapsed in a new transmission cycle, and the length of the synchronization gap is set as the "terminal gap".
Because the length is longer than the length of the Since the cable length is also long, terminals can be easily added, making it possible to build a highly flexible system.

Although the invention has been described with reference to a preferred embodiment, it will be obvious to those skilled in the art that the invention is not limited thereto. Rather, the scope of the invention should be construed only in conjunction with the claims below.

[Brief explanation of drawings]

Figure 1 shows how this data is transferred using a data bus.
1 is a block diagram showing the configuration of a conventional data communication system having a plurality of subscriber terminals on a bus; FIG. FIG. 2 is a block diagram showing the configuration of a typical conventional subscriber terminal. FIG. 3 is a timing diagram showing the operation of a data communication system controlled by an aperiodic variable length message protocol. Figure 4 is the third
3 is a block diagram illustrating the configuration of a portion of the terminal control unit shown in FIG. 2 that is specifically used to execute the protocol shown; FIG. FIG. 5 is a block diagram schematically showing the configuration of the subscriber terminal, related utilization devices, and interface unit. FIG. 6 is a block diagram showing the structure of the demodulator and receiver shown in FIG. 5. Figure 7 is the 5th
FIG. 2 is a block diagram showing the configuration of the transmitter and modulator shown in the figure. FIG. 8 shows a configuration of the protocol control unit shown in FIG. 7 used specifically for executing the aperiodic protocol shown in FIG. 3, the periodic protocol, and the combination of aperiodic and periodic protocols. FIG. 9A and 9B are timing diagrams showing the operation of a data communication system in which each connected terminal is provided with the protocol control unit shown in FIG. 7. In the figure, 16 is a demodulator, 18 is a receiver,
20 is a terminal control unit, 22 is a transmitter, 24 is a modulator, 32 is a gap detector, 34
is a synchronous gap timer, 36 is a latch, 40 is a terminal gap timer, 42 is a modulator enable switch, 100 is a twisted pair wire, 110 is a demodulator, 112 is a modulator, 114 is a receiver, 11
6 is an interface unit, 120 is a transmitter, 140 is a protocol control unit,
142 is a transmitter clock; 144 is a data buffer, encoder and interface control unit; 150 is a clock control unit; 152 is a receive clock generator; 154 is a data buffer, decoder and interface control unit; 160, 170, 190 are comparator,
162, 172, 192 are counters, 169, 2
02, 204, and 206 are latches, and TL1 to TL5 are terminals. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] 1. A terminal capable of autonomously accessing a data bus in order to send and receive messages on the data bus together with a plurality of other terminals, the terminal being capable of: (a) transmitting messages on the data bus; (b) receiving means coupled to said data bus to receive a message, said receiving means providing a message absent signal during the absence of a message on said data bus; (c) a protocol control unit coupled to the receiving means and the transmitting means, the protocol control unit configured to clock the message absent signal; and providing a synchronization gap detection signal when the message absence signal has a predetermined length substantially equal to a synchronization gap common to each of the terminals accessing the data bus; a resettable synchronous gap timer that is reset when the signal terminates; latching means for temporarily storing the synchronous gap detection signal; and a resettable terminal gap that is enabled in response to the synchronous gap detection signal. , the resettable terminal gap timer times the message-not-present signal when enabled and when the message-not-present signal persists for a predetermined period of time substantially equal to a terminal gap specific to the terminal. gating means for providing a terminal gap detection signal to a terminal gap detection signal and resetting the latching means and enabling the transmitting means in response to the synchronous gap detection signal and the terminal gap detection signal; and the synchronous gap detection signal is simultaneously latched into the latching means of each of the terminals, and further the resettable terminal gap timer is latched to the latching means of each of the terminals simultaneously. Terminal equipment enabled by synchronous gap detection signal. 2. The protocol control unit further comprises a resettable transmission interval timer, the resettable transmission interval timer providing a transmission interval detection signal when a predetermined transmission interval has elapsed after resetting the transmission interval timer; the transmission interval has substantially the same duration for each of the terminals accessing the data bus, and the gating means further detects the synchronization gap detection signal, the terminal gap detection signal and the transmission interval detection signal. 2. A terminal device according to claim 1, wherein said terminal device enables said transmitting means, resets said latching means, and resets said transmitting interval timer only in response to a. 3. The terminal device according to claim 1 or 2, wherein the synchronous gap timer further comprises means for selectively adjusting the length of the synchronous gap. 4. The terminal device according to claim 1 or 2, wherein the terminal gap timer includes means for selectively adjusting the length of the terminal gap. 5. The terminal is particularly adapted to use a data bus consisting of a long twisted pair of conductors with shorted ends, and the terminal further inductively couples the receiving means and the transmitting means to the twisted pair of conductors. 3. The terminal device according to claim 1 or 2, further comprising means for causing the terminal device to perform the operation. 6. The terminal device according to claim 2, wherein the transmission interval timer includes means for selectively adjusting the length of the transmission interval. 7. The protocol control unit further comprises means for selectively disabling reset of the transmit interval timer and causing the transmit interval timer to provide the interval detection signal when the reset is disabled. Terminal device according to item 2. 8. The terminal device according to claim 2, wherein the protocol control unit further comprises means for causing the transmission interval timer to supply the transmission interval detection signal when power is supplied to the terminal. 9. The terminal device according to claim 2 or 8, wherein the protocol control unit further comprises means for causing the synchronous gap timer to supply the synchronous gap detection signal when power is supplied to the terminal.