JPH0377420A - Automatic frequency controller - Google Patents

Abstract

PURPOSE:To stabilize the transmission frequency without use of a contact temperature oven by applying feedback control to a voltage controlled oscillator VCO in using a clock pulse frequency as a reference. CONSTITUTION:A CPU 8 measures a multiple of a 1st intermediate frequency f1 of a receiver and a reference frequency fs of a transmitter with respect to a clock frequency fk by using it that the clock signal frequency fk is being kept accurate, and when the multiple is deviated from a pre-stored regular value, VCOs 2, 11 are subject to feedback control based on the deviation. Thus, the 1st local oscillating frequency of the receiver and the reference frequency of the transmitter are made simultaneously stable with a simple circuit and the locking of the frequency is realized surely with less malfunction by digital control.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an automatic frequency control device for stabilizing frequencies in satellite communications and the like.

[Prior Art] In satellite communications, due to the nature of satellite repeaters, a frequency offset occurs in the reception frequency on the ground, and the offset amount is approximately ±40 kHz.

Therefore, it is necessary to correct this offset at the ground receiver. A conventional offset correction circuit that corrects such an offset includes a frequency conversion circuit, a frequency discrimination circuit, and a VC.
The oscillation frequency of the first local oscillation circuit of the receiver is automatically changed and corrected according to the offset amount of the reception frequency.

In order to stabilize the transmission frequency, conventionally, a crystal oscillator equipped with a constant temperature oven is generally used.

"Problems to be Solved by the Invention" As described above, the conventional offset correction circuit as described above has a sophisticated analog circuit, has a large number of components, and lacks reliability.

Further, the constant temperature bath used in the transmitter has problems such as high manufacturing cost, large volume, and large power consumption.

This invention was made to solve such problems, and provides an automatic frequency control device that can easily correct the offset of the reception frequency and stabilize the transmission frequency without using a thermostatic oven. It is an object.

[Means for Solving the Problems] This automatic frequency control device utilizes the fact that the frequency fk of a clock signal is accurately maintained when transmitting a digital signal. f of the intermediate frequency fs and the reference frequency fs of the transmitting device, respectively.
The multiples for k are measured, and if these multiples deviate from the normal values stored in advance, each VCO is feedback-controlled using the value of the deviation, and the oscillation frequency of the first local oscillation circuit is set to the receiving frequency. By sweeping the entire range and passing the output of the first frequency conversion circuit of the receiving device through a narrow band bandpass filter, the receiving frequency is searched and frequency pull-in is ensured, and the frequency of the receiving device is also transmitted. CPU with same frequency of device
It was decided that the system would be digitally controlled by a central processing unit.

[Operation] Since the frequency fk of the clock pulse can be accurately reproduced, fs and fs can be easily controlled to accurate frequencies.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
The figure is a block diagram showing an embodiment of the present invention. In the figure, (1) is a frequency conversion circuit, and (2) is a first VCOl (
3) is a band pass filter (hereinafter abbreviated as BPF),
(=1> is the carrier detection circuit, (5) is the carrier regeneration circuit, (6) is the signal demodulation circuit, (7) is the clock regeneration circuit, (8) is the control CPU, (9) is the first digital analog Converter (hereinafter abbreviated as /A), (10
) indicates the second D/A, (11) indicates the second VCO, and CD indicates the detection signal from the carrier detection circuit (4).

If the carrier frequency of the received PSK signal is fr, its clock frequency is fk, and the output frequency of V CO (2) is fv, then the intermediate frequency carrier f+, which is the output of the frequency conversion circuit (1), is, for example, fs 2fs-fv.

CPU (8) passes through D , , /' A (9) and then V
The oscillation frequency fv of CO(2) is swept, and B
P F (3) has a narrow band pass characteristic with the center frequency fio, but when fv is swept and therefore fi becomes fi”fio, f
S passes through B P F (3). The carrier detection circuit (4) detects this and sends a detection signal C to the CPU (8).
Output D. In the CPU (8,), this detection signal CD
The sweep of V CO (2) is stopped.

Then, an intermediate frequency carrier is regenerated from the output of B P F (3) by a carrier regeneration circuit (5), and a signal is regenerated from the output of B P F (3) by a signal demodulation circuit (6) using this regenerated carrier. demodulated. A clock pulse is then extracted from the demodulated signal by a clock recovery circuit (7).

FIG. 2 is a block diagram explaining the operation of the CPU (8) shown in FIG. 1, where the same reference numerals as in FIG. 1 indicate the same parts, (81) is a sawtooth wave generating circuit, and (82) is fi.

/f Memory that stores the value of k, (83) is 1 of fk
A counter that measures the wave number of fi during a period, (84) a latch that latches the value when the counter (83) finishes counting, (85) a first subtraction circuit, <86
) indicates a selector.

While CD is below a predetermined value, the selector (81) gives the output of the sawtooth wave generating circuit (81) to the D/A (9) to sweep the oscillation frequency of the V CO (2). As fi approaches fiO, the output of B P F (3) increases and therefore the CD from carrier detection circuit (4)
increases, and the selector (86〉) gives the output from the subtraction circuit (85) to D/A (9). That is, D/A (
9) -VC○〈2)-Frequency conversion circuit (1)-BPF
(3) - Carrier regeneration circuit (5) - Counter (83) -
Latch (84) - Subtraction circuit (85) - Selector (86)
-D ,,/A (by the circuit of 9>, f+=f+o
Feedback control is performed so that

Also, (87) is f −o/ f k (however, fs. is fs
(88) is 1 of fk.
A counter that measures the wave number of fi during a period, (89) indicates a latch that latches the value when the counter (88) finishes counting, and this circuit operates in the same way as the previous fs case. Accordingly, feedback control is performed so that fs=fs.

As described above, the first local oscillation frequency of the receiving device and the reference frequency of the transmitting device can be simultaneously stabilized by a single CP tJ (8).

[Effects of the Invention] As explained above, the present invention simultaneously stabilizes the first local oscillation frequency of the receiving device and the reference frequency of the transmitting device using a simple circuit, and enables reliable frequency pull-in with fewer malfunctions through digital control. The effect is that it can be achieved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram explaining the operation of the CPU shown in FIG. 1. (1) is the frequency conversion circuit, (2> is the first vC○, (3
) is the BPF, (4) is the carrier detection circuit, (5) is the carrier recovery circuit, (6> is the signal demodulation circuit, (7) is the clock recovery circuit, (8) is the CPU, and (9) is the first D /A,
(10) is the second D/A, and (11) is the second VC9. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] In an automatic frequency control device used in a communication device that modulates and transmits a carrier wave using a digital signal that can reproduce a clock frequency, a frequency that converts a reception frequency to an intermediate frequency (this frequency is referred to as f_i) a conversion circuit; a first voltage controlled oscillator (VCO) that supplies a local oscillation voltage to the frequency conversion circuit; connected to the output of the frequency conversion circuit, having a center frequency at a prescribed intermediate frequency f_i_0 and having a narrow pass frequency band; A band pass filter (BPF), a carrier regeneration circuit that regenerates the intermediate frequency f_i that has passed through this BPF from the output of this BPF, a signal demodulation circuit that demodulates a signal from the output of this carrier regeneration circuit and the output of the BPF; A clock regeneration circuit that extracts a clock pulse (this frequency is f_k) from the output of the signal demodulation circuit, a carrier detection circuit that detects whether the output of the BPF is above a predetermined value, and a reference frequency used in the transmitter. The second oscillating f_s
VCO, input each frequency of f_i, f_k, f_s, f_i/
Calculate the values of f_k and f_s/f_k, and use these values and pre-stored values of f_i_0/f_k and f_s_0/
Difference Δf from the value of f_k (f_s_0 is the specified value of f_s)
A CPU that calculates _i, Δf_s, and a first digital-to-analog converter (D/A
), and when the output of the carrier detection circuit exceeds the predetermined value, input the value of Δf_i to the first D/A, and use the output to means for feedback controlling the first VCO;
An automatic frequency control device comprising means for feedback controlling CO.