JPH0376251A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0376251A
JPH0376251A JP1213598A JP21359889A JPH0376251A JP H0376251 A JPH0376251 A JP H0376251A JP 1213598 A JP1213598 A JP 1213598A JP 21359889 A JP21359889 A JP 21359889A JP H0376251 A JPH0376251 A JP H0376251A
Authority
JP
Japan
Prior art keywords
semiconductor wafer
semiconductor
thermal
wafer
grooves
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1213598A
Other languages
Japanese (ja)
Inventor
Masao Sumiyoshi
住吉 政夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1213598A priority Critical patent/JPH0376251A/en
Publication of JPH0376251A publication Critical patent/JPH0376251A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To surely split a wafer into chips at a high yield by a method wherein grooves are provided between adjacent semiconductor devices on the semiconductor wafer as scribing lines, the wafer provided with the grooves is subjected to a first thermal treatment, and a material whose thermal expansion coefficient is larger than that of the wafer is formed in the grooves, which is subjected to a second thermal treatment. CONSTITUTION:Grooves are provided between adjacent semiconductor devices 2 on a semiconductor wafer 1 as scribing lines 4. Then, the semiconductor wafer 1 is thermally expanded by a first heat treatment, whereby a first thermal strain 8 is induced in the semiconductor wafer 1 under the scribing line 4 through thermal expansion. Then, material such as metal 9 whose thermal expansion coefficient is larger than that of the semiconductor wafer 1 is formed in the scribing lines 4. Then, when the semiconductor wafer 1 is subjected to a second thermal treatment, as the metal 9 is larger than the semiconductor wafer 1 in thermal expansion coefficient, thermal strains 5a and 5b are caused in the semiconductor wafer 1, and thermal strain 5 as the net of them is generated in the semiconductor wafer 1. Then, when a mechanical force 6 is applied, the semiconductor wafer 1 is split into semiconductor chips 1a along the lines under which the second thermal strain 5 exists.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体ウェハ上の半導体チップを確実に分
割することができる半導体装置の製造方法に関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device that can reliably divide semiconductor chips on a semiconductor wafer.

〔従来の技術〕[Conventional technology]

従来、半導体ウニへ上に多数形成された半導体チップを
スクライブラインより分割する場合は、第3図に示すよ
うに、半導体ウェハ1上の多数の半導体装置2と半導体
装置2の間を、第4図(a)に示すように、ダイヤモン
ドカッタ3を図中矢印Aの方向に移動させることで、ケ
ガキ線をスクライブライン4として入れる。この時、ダ
イヤモンドカッタ3には適当な荷重がかかっているので
、乙のスクライブライン4の形状は、第4図(b)のよ
うになり、スクライブライン4の直下の半導体ウェハ1
に熱歪5を生じさせる。次に外部よりローラ式のブレイ
カ等(図示せず)により機械的な力6を加えると、半導
体ウェハ1は第4図(e)のように歪5の部分より割れ
て半導体チップ1aに分割される。
Conventionally, when dividing a large number of semiconductor chips formed on a semiconductor wafer 1 from a scribe line, as shown in FIG. As shown in Figure (a), by moving the diamond cutter 3 in the direction of arrow A in the figure, a scribe line is inserted as a scribe line 4. At this time, since an appropriate load is applied to the diamond cutter 3, the shape of the scribe line 4 becomes as shown in FIG.
Thermal strain 5 is caused. Next, when a mechanical force 6 is applied from the outside using a roller-type breaker or the like (not shown), the semiconductor wafer 1 is broken at the strain 5 and divided into semiconductor chips 1a as shown in FIG. 4(e). Ru.

ここで、これら第4図(a)〜(C)の作業は通常、接
着材の付いた塩化ビニル等のフィルムに半導体ウニへ1
を貼り付けた状態で行われている。
The operations shown in Figures 4(a) to (C) are usually performed by attaching a film such as vinyl chloride with an adhesive to a semiconductor urchin.
This is done with the .

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上記のような半導体ウェハ1のチップ分割方法における
ダイヤモンドカッタ3は、第5図(a)に示すように、
本体3aと先端のダイヤモンドチップ3bから構成され
ており、このダイヤモンドチップ3bの先端角度θ1と
形状、第5図(b)に示すように、半導体ウェハ1とダ
イヤモンドカッタ3の角度θ2.およびダイヤモンドカ
ッタ3に加える荷重、すなわち第5図(C)に示すよう
に、半導体ウェハ1に入れるスクライブライン4の切り
込み深さDのパラメータによって半導体チップ1aのチ
ップ分割状態が決まる。ここで、例えば第6図(a)に
示すようなダイヤモンドチップ3bの先端角度θ1が摩
擦のため丸くなったり、第5図(b)に示した半導体ウ
ェハ1とダイヤモンドカッタ3の角度が不適当であった
り、ダイヤモンドカッタ3の荷重が大きすぎると、スク
ライブライン4は、第6図(b)に示すように、ひび割
れ7が生じたり、熱歪5が多方向に入るため、この状態
で半導体ウェハ1と半導体チップ1aに分割しようとす
ると、第7図(a)に示すように、分割された半導体チ
ップ1a上の半導体装置2の部分が割れたり、第7図(
b)に示すように、半導体チップ1aが斜めに割れたり
する。また、第4図(a)に示したダイヤモンドカッタ
3の移動速度を早くしすぎると、スクライブライン4に
飛びが生じ、半導体ウェハ1上にスクライブライン4の
ない部分ができるため、分割の全くできない部分が生じ
る等の不都合が生じていた。
As shown in FIG. 5(a), the diamond cutter 3 in the method for dividing the semiconductor wafer 1 into chips as described above has the following features:
It is composed of a main body 3a and a diamond tip 3b at the tip, and as shown in FIG. The chip division state of the semiconductor chip 1a is determined by the load applied to the diamond cutter 3, that is, the cutting depth D of the scribe line 4 inserted into the semiconductor wafer 1, as shown in FIG. 5(C). Here, for example, the tip angle θ1 of the diamond tip 3b as shown in FIG. 6(a) becomes rounded due to friction, or the angle between the semiconductor wafer 1 and the diamond cutter 3 as shown in FIG. 5(b) is inappropriate. If the load of the diamond cutter 3 is too large, cracks 7 will occur in the scribe line 4 and thermal strain 5 will occur in multiple directions, as shown in FIG. 6(b). If an attempt is made to divide the wafer 1 and the semiconductor chip 1a, the portion of the semiconductor device 2 on the divided semiconductor chip 1a may break, as shown in FIG.
As shown in b), the semiconductor chip 1a may be diagonally broken. Furthermore, if the moving speed of the diamond cutter 3 shown in FIG. 4(a) is made too fast, the scribe line 4 will jump and a portion without the scribe line 4 will be created on the semiconductor wafer 1, making it impossible to divide it at all. Inconveniences such as the formation of parts occurred.

このように従来の半導体ウェハ1のチップ分割方法は、
ダイヤモンドカッタ3の先端のダイヤモンドチップ3b
の摩擦状態や、半導体ウェハ1に対する角度θ2および
ダイヤモンドカッタ3に加える荷重や、その移動速度等
の多くの項目を調整する必要があり、さらに、半導体ウ
ェハ1上に形成されている半導体装置2と、隣接する半
導体装置2との間隔は、通常80μm程度と非常に小さ
いため、この間の中央にダイヤモンドカッタ3でスクラ
イブライン4を精度良く入れる作業は、かなりの熟練が
必要であった。また、ダイヤモンドカッタ3を使用しな
いチップ分割方法として、ダイサーを用いる方法がある
が、ダイサーを用いる場合、半導体装置2と隣接する半
導体装置2の間を200μ+n程度以上に広くする必要
がある。この場合、半導体ウェハ1の材料にGaAsを
用いている超高周波帯で用いる半導体装置の場合、半導
体装置2の寸法そのものが200μm角であるため、半
導体ウェハ1の1枚当たりの半導体装置2の個数が半減
してしまうなどの不都合が生じていた。
In this way, the conventional method of dividing the semiconductor wafer 1 into chips is as follows:
Diamond tip 3b at the tip of diamond cutter 3
It is necessary to adjust many items, such as the friction state of Since the distance between adjacent semiconductor devices 2 is usually very small, about 80 .mu.m, considerable skill is required to accurately cut a scribe line 4 in the center between them using a diamond cutter 3. Further, as a chip dividing method that does not use the diamond cutter 3, there is a method using a dicer, but when a dicer is used, it is necessary to widen the space between two adjacent semiconductor devices 2 to about 200μ+n or more. In this case, in the case of a semiconductor device used in an ultra-high frequency band in which GaAs is used as the material of the semiconductor wafer 1, the dimensions of the semiconductor device 2 itself are 200 μm square, so the number of semiconductor devices 2 per semiconductor wafer 1 is There were some inconveniences such as the amount being reduced by half.

この発明は、上記のような従来の問題点を解決するため
になされたもので、確実に、かつ歩留りよくチップに分
割することができる半導体装置の製造方法を得ることを
目的としている。
The present invention was made to solve the above-mentioned conventional problems, and aims to provide a method for manufacturing a semiconductor device that can be divided into chips reliably and with a high yield.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係る半導体装置の製造方法は、半導体ウェハ
上に形成した多数の隣接する半導体装置間の前記半導体
ウェハにスクライブラインとしてエツチングにより溝を
形成し、第1の熱処理をした後、その溝の部分に前記半
導体ウニへの材料より熱膨張率の大きな材料を形成し、
その後、第2の熱処理を行った後、各半導体チップに分
割する工程を有するものである。
In the method for manufacturing a semiconductor device according to the present invention, grooves are formed by etching as scribe lines in the semiconductor wafer between a number of adjacent semiconductor devices formed on the semiconductor wafer, and after a first heat treatment, the grooves are removed. Forming a material having a larger coefficient of thermal expansion than the material for the semiconductor sea urchin in the part,
Thereafter, after performing a second heat treatment, there is a step of dividing into each semiconductor chip.

〔作用〕[Effect]

この発明においては、半導体ウェハ上に形成した多数の
隣接する半導体装置間の前記半導体ウェハにスクライブ
ラインとしてエツチングにより溝を形成し、第2の熱処
理を行った後にその溝の部分に半導体ウニへの材料より
熱膨張率の大きな材料を形成し、第2の熱処理を行うこ
とにより、スクライブライン直下の半導体ウェハに熱に
よる機械的歪が加わり、前記各半導体装置はスクライブ
ラインより確実に分割される。
In this invention, grooves are formed by etching as scribe lines in the semiconductor wafer between a large number of adjacent semiconductor devices formed on the semiconductor wafer, and after the second heat treatment is performed, the grooves are filled with the semiconductor wafer. By forming a material with a larger coefficient of thermal expansion than the other material and performing the second heat treatment, mechanical strain due to heat is applied to the semiconductor wafer directly below the scribe line, and each of the semiconductor devices is reliably divided from the scribe line.

〔実施例] 以下、この発明の一実施例を図面について説明する。〔Example] An embodiment of the present invention will be described below with reference to the drawings.

第1図(a)〜(g)はこの発明の半導体装置の製造方
法の一実施例の製造工程を示す図である。
FIGS. 1(a) to 1(g) are diagrams showing manufacturing steps of an embodiment of the method for manufacturing a semiconductor device of the present invention.

まず、第1図(a)に示すように、半導体ウェハ1上の
半導体装置2と隣接する半導体装置2の間にスクライブ
ライン4として溝を公知の写真製版技術およびエツチン
グ技術により形成する。次に第1の熱処理を行う。この
熱処理により半導体ウェハ1は熱膨張をするが、第1図
(b)に示すように、スクライブライン4直下の半導体
ウェハ1に熱l!張による第1の熱歪8が生じる。次に
第1図(C)に示すように、スクライブライン4の部分
に半導体ウェハ1より熱膨張率の大きな材料、例えば金
WA9を公知の真空蒸着法等により形成す。
First, as shown in FIG. 1(a), grooves are formed as scribe lines 4 between semiconductor devices 2 on a semiconductor wafer 1 and adjacent semiconductor devices 2 by known photolithography and etching techniques. Next, a first heat treatment is performed. The semiconductor wafer 1 undergoes thermal expansion due to this heat treatment, but as shown in FIG. 1(b), the semiconductor wafer 1 directly below the scribe line 4 is heated! A first thermal strain 8 occurs due to tension. Next, as shown in FIG. 1C, a material having a higher coefficient of thermal expansion than the semiconductor wafer 1, such as gold WA9, is formed on the scribe line 4 by a known vacuum evaporation method or the like.

る。その後、第2の熱処理を行うと、半導体ウェハ1お
よび金属9は熱膨張する。ここで、金属9は半導体ウェ
ハ1に対して熱膨張率が大きいため、第1図(d)に示
すように、半導体ウェハ1に対して熱歪5aおよび5b
が加わるため、それらの合力である熱歪5(以下、第2
の熱歪5という)が半導体ウェハ1に加わることになる
。ここで、第1図(b)のように半導体ウェハ1には第
1の熱処理により第1の熱歪8が生じているため、第2
の熱歪5は、第1図(el)に示すように、本来の大き
さ以上に半導体ウェハ1の中に入っていく。
Ru. After that, when a second heat treatment is performed, the semiconductor wafer 1 and the metal 9 thermally expand. Here, since the metal 9 has a large coefficient of thermal expansion relative to the semiconductor wafer 1, as shown in FIG. 1(d), the thermal strain 5a and 5b
is added, the resultant force of these is thermal strain 5 (hereinafter referred to as the second
thermal strain 5) is applied to the semiconductor wafer 1. Here, as shown in FIG. 1(b), since the first thermal strain 8 has occurred in the semiconductor wafer 1 due to the first heat treatment, the second
As shown in FIG. 1 (el), the thermal strain 5 enters into the semiconductor wafer 1 in a larger amount than the original size.

次に第1図(f)に示すように、公知の写真製版技術と
エツチング技術を用いて金属9を除去した後に、従来と
同様の方法で外部よりローラ式のブレイカ等(図示せず
)により機械的な力6を加えると、半導体ウェハ1は第
1図(g)に示すように、第2の熱歪5の部分より割れ
て、半導体チップ1aに分割される。ここで、第1図(
’ L (g )の工程は、従来と同様に接着材の付い
た塩化ビニル等のフィルムに半導体ウェハを貼り付けた
状態で行えば良い。
Next, as shown in FIG. 1(f), after removing the metal 9 using known photolithography and etching techniques, the metal 9 is etched from the outside using a roller-type breaker (not shown) in the same manner as before. When mechanical force 6 is applied, semiconductor wafer 1 is broken at the second thermal strain 5 and divided into semiconductor chips 1a, as shown in FIG. 1(g). Here, Figure 1 (
The process 'L(g) may be performed with the semiconductor wafer attached to a film made of vinyl chloride or the like with an adhesive, as in the conventional method.

第2図はこの発明の他の実施例を示す図で、隣接する半
導体装置2間の半導体ウェハ1に形成する溝の形状を凹
形状としたもので、同様な効果が期待される。
FIG. 2 shows another embodiment of the present invention, in which the grooves formed in the semiconductor wafer 1 between adjacent semiconductor devices 2 have a concave shape, and similar effects are expected.

なお、上記実施例では半導体ウェハ1にGaAs、スク
ライブラインに金属9を形成した場合について説明した
が、半導体ウェハ1に対して熱膨張率が大きければ、各
種絶縁物や合成樹脂等を用いてもよい。
In the above embodiment, a case was explained in which GaAs was formed on the semiconductor wafer 1 and metal 9 was formed on the scribe line, but various insulators, synthetic resins, etc. may be used as long as the coefficient of thermal expansion is large with respect to the semiconductor wafer 1. good.

さらに、スクライブラインの幅や深さ、形状およびスク
ライブライン上に形成する金属材料および熱処理の温度
、昇温速度等は半導体ウェハ1の材質、厚さ等により適
宜選べば良い。
Further, the width, depth, and shape of the scribe line, the metal material formed on the scribe line, the temperature of heat treatment, the temperature increase rate, etc. may be appropriately selected depending on the material, thickness, etc. of the semiconductor wafer 1.

また、上記実施例では、半導体ウェハ1の分割について
説明したが、半導体ウェハ以外にも応用できることはい
うまでもない。
Further, in the above embodiment, the division of the semiconductor wafer 1 has been described, but it goes without saying that the present invention can be applied to other than semiconductor wafers.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、この発明は、多数の半導体装置か
らなる半導体ウニへ上の隣接する半導体装置間にエツチ
ングにより、溝を形成した後、第1の熱処理を行い、溝
の直下に第1の熱歪を発生させる工程、前記溝の上に半
導体ウェハより熱膨張率の大きな材料を付着させた後、
第2の熱処理を行い、前記溝の直下に第2の熱歪を発生
させる工程、前記溝の上に付着された材料を除去した後
、各半導体チップに分割する工程を含むので、確実にチ
ップ分割ができる効果がある。
As explained above, in the present invention, a groove is formed by etching between adjacent semiconductor devices in a semiconductor unit made up of a large number of semiconductor devices, and then a first heat treatment is performed, and a first groove is formed directly below the groove. In the step of generating thermal strain, after attaching a material with a larger coefficient of thermal expansion than the semiconductor wafer onto the groove,
The process includes a step of performing a second heat treatment to generate a second thermal strain directly under the groove, and a step of dividing into each semiconductor chip after removing the material attached to the groove. It has the effect of being able to divide.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例による半導体装置の製造工
程を示す断面図、第2図はこの発明の他の実施例を示す
断面図、第3図は半導体ウェハを示す斜視図、第4図は
従来の半導体ウニへのチップ分割方法の工程を説明する
図、第5図はダイヤモンドカッタを示す図、第6図は従
来のスクライブ不良状態を説明するための図、第7図は
チップ分割不良時の半導体チップの状態を示す図である
。 図において、1は半導体ウェハ、2は半導体装置、5,
8は第1.第2の熱歪、6は外部からの機械的な力、9
は金属である。 なお、各図中の同一符号は同一または相当部分を示す。
FIG. 1 is a sectional view showing the manufacturing process of a semiconductor device according to one embodiment of the present invention, FIG. 2 is a sectional view showing another embodiment of the invention, FIG. 3 is a perspective view showing a semiconductor wafer, and FIG. The figure is a diagram explaining the steps of the conventional chip dividing method for semiconductor urchins, Figure 5 is a diagram showing a diamond cutter, Figure 6 is a diagram explaining a conventional scribe failure state, and Figure 7 is a diagram showing chip division. FIG. 3 is a diagram showing the state of a semiconductor chip when it is defective. In the figure, 1 is a semiconductor wafer, 2 is a semiconductor device, 5,
8 is the first. Second thermal strain, 6 is external mechanical force, 9
is metal. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] 多数の半導体装置が形成された半導体ウェハ上の隣接す
る前記半導体装置間にエッチングにより溝を形成した後
、第1の熱処理を行い、前記溝の直下に第1の熱歪を発
生させる工程、前記溝の上に前記半導体ウェハより熱膨
張率の大きな材料を付着させた後、第2の熱処理を行い
、前記溝の直下に第2の熱歪を発生させる工程、前記溝
の上に付着された材料を除去した後、各半導体チップに
分割する工程を含むことを特徴とする半導体装置の製造
方法。
forming grooves by etching between adjacent semiconductor devices on a semiconductor wafer on which a large number of semiconductor devices are formed, and then performing a first heat treatment to generate a first thermal strain directly under the grooves; After depositing a material having a larger coefficient of thermal expansion than the semiconductor wafer on the groove, performing a second heat treatment to generate a second thermal strain directly under the groove; 1. A method of manufacturing a semiconductor device, comprising the step of removing material and then dividing into semiconductor chips.
JP1213598A 1989-08-18 1989-08-18 Manufacture of semiconductor device Pending JPH0376251A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1213598A JPH0376251A (en) 1989-08-18 1989-08-18 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1213598A JPH0376251A (en) 1989-08-18 1989-08-18 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0376251A true JPH0376251A (en) 1991-04-02

Family

ID=16641841

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1213598A Pending JPH0376251A (en) 1989-08-18 1989-08-18 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0376251A (en)

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