JPH0376060B2 - - Google Patents

Description

[Detailed Description of the Invention] Using a counter based on the logic circuit of the present invention
Regarding FSK demodulation circuit.

The FSK communication system, which uses frequency modulation and demodulation, is the most commonly used for data communications, and there are high expectations for FSK modulation and demodulation equipment (MODEM). But FSK
Conventional modems have used analog methods such as frequency discrimination and PLL methods, which require a large number of individual parts and adjustment points, making it difficult to downsize, maintain long-term stability, and lower prices. On the other hand, the frequency corresponding to the digital binary signal is modulated by changing the frequency division ratio of the highly stable signal generated by crystal oscillation, and during demodulation, the zero crossing of the signal that has passed through the filter is detected and its period is A method has been considered in which the original binary signal is obtained by counting the number of signals using a counter and determining the magnitude of the count value, and the idea is to integrate these circuits to realize miniaturization, improved reliability, lower price, and lower power consumption. It is being However, with regard to demodulation, the counter method is sensitive to errors in the zero-cross period due to noise, and has the disadvantage that demodulation of a signal with a small S/N ratio increases code distortion and makes demodulation impossible. This problem occurs when the full-duplex communication function of a low-speed modem is susceptible to leakage of the frequency-divided band to the opposite band, that is, the influence of the transmitting carrier on the receiving carrier. In an acoustic coupler modem, the transmitting carrier is more susceptible to sidetone noise returning through the telephone to its own receiving microphone. It is also necessary to pay strict attention to line characteristics and noise, as well as external noise.

The present invention improves the above-mentioned drawbacks and makes it possible to demodulate signals with a large noise level even when using a counter method. The present invention makes it easy to integrate a modulation/demodulation circuit into an IC, which has a very large effect. Also, regarding filters, operational amplifiers have recently been introduced.
It consists of a capacitor and a semiconductor switch, and its characteristics are
A filter that can be fabricated into an IC with extremely high precision determined by the highly accurate capacitance ratio inside the IC and the switching clock frequency has been put into practical use and is called a switched capacitor filter (SOF), in which the filter is housed in the same IC as the modulation/demodulation section. It is becoming possible to integrate into a single chip.

The present invention will be explained in detail below with reference to the drawings.
FIG. 1 is a block diagram of an FSK demodulation circuit according to the present invention.

It consists of a receiving amplifier 1, a bandpass filter 2, a limiter 3, a comparator 4, and a demodulation circuit 5. The received signal is amplified to the extent that its amplitude does not exceed the clip level, then a band-pass filter removes the signal of the opposite band and other noises, the amplitude is limited by a limiter to avoid saturation of the operational amplifier, etc., and the amplitude is limited by a comparator. It becomes a digital value that includes FSK information in the period value. Zero cross information is obtained from the point of change in the level of the comparator, and is digitally demodulated by a value obtained by counting the basic clock during the zero cross period by a counter in the demodulation circuit. Therefore, compared to conventional analog demodulation methods, it is easier to integrate into an IC, requires no adjustment, and does not cause fluctuations over the long term.

FIG. 2 is a timing chart of zero-cross period detection according to the present invention. The received FSK signal FS is converted into a digital value ZC1 by a comparator. Furthermore, the counter is reset by obtaining a signal ZC2 differentiated from the rising and falling points of ZC1.
Used for reading.

FIG. 3 shows an embodiment of the counter selection circuit of the present invention. It consists of D-type FFs 6, 7, 9, and 10, an exclusive OR gate 8, a quarter frequency divider circuit 11, and AND gates 12 to 15, and 6 to 8 provide a differential signal ZC2 for zero-cross cycle detection. A signal ZC3 obtained by shaping and delaying ZC2 is selectively output in sequence as outputs S1, S2, S3, and S4 by a frequency dividing circuit 11. Further, reset signals R1 to R4 for each counter are generated by logically multiplying the signal R obtained by further delaying ZC3 by the main clock and the previous signals S1 to S4.
FIG. 4 is a timing chart of an embodiment of the counter selection circuit of the present invention.

In synchronization with the zero-cross period signal ZC3 and its delayed signal R, selection outputs are obtained in the order of S1→S2, and respective reset and read signals R1 and R2 are obtained. The reason why R1 to R4 are delayed by the main clock period with respect to the selection outputs of S1 to S4 is to take account of delays in the circuit and reset and read out the counters after the selection outputs have become sufficiently stable.

FIG. 5 is a circuit diagram of a counter according to an embodiment of the present invention, which is composed of N counters (N=4).
Each counter 16 to 19 receives a demodulated binary signal "1"
It has a "0" discrimination circuit. Focusing on the counter 16, there is a gate 20 that detects thresholds of "1" and "0" from a ripple counter of a predetermined number of bits;
OR gate 21 that stores the output, D type FF
22 and an AND gate 23. The counter value is counted up according to the resolution of the main clock φ, and when it exceeds the threshold value of "1" or "0", it is determined that it is a signal on the low frequency side of the FSK signal and is stored. The reason why the clock φ is in phase is that the counter selection circuit operates and outputs S1 and R1, and since it is also the clock of the FF 22, the phase is shifted from when the counter changes to prevent malfunction. The FFs and AND gates 24 to 29 function similarly to 22 and 23. Returning to the operation of the counter 16, the selection of the counter 16 is made at the time of S1 output, and is reset by R1 immediately after S1, so the output of FF22 is S1 of one cycle before the counter 16 is reset.
It is held whether the period value of +S2+S3+S4 exceeds the threshold value of the gate 20. Therefore, the output of the FF 22 is selected as a read signal by the AND gate 23 and S1 and sent to the OR gate 30.
is sent to the output processing circuit. The output of the FF 22 indicates the discrimination result during S1, but when it is not selected, it is reset by R2 in S2 and waits to store the next count value. counter 17
~19 performs exactly the same operation as 16, but counter 17 has S2+S3+S4+S1, counter 18 has S3+S4+S1+S2, and counter 19 has S4+.
Although the time span S1+S2+S3 is four times the zero-crossing detection period, each is counted one zero-crossing period at a time, and the results are read out anew for each zero-crossing period.

The output of the OR gate 30 is D type FF31,3
2, 33, exclusive or gate 34, or gate 3
The signal is input to an output processing circuit consisting of 5. FF31,
32 and 33 take in data in accordance with the clock every time a zero-cross cycle is detected. If the outputs of FF31 and FF33 are different, the exclusive OR gate 34 outputs "H", and the OR gate 35 changes the clock to FF31.
prohibited from being entered. FF31 during the ban period
The output of is fixed, but the output depends on FF3
Since the output of the exclusive OR gate 34 becomes "L", the inhibition of is released. Output processing circuit outputs when noise increases extremely.
The data of FF31 is set to 2 so that OUT does not change suddenly.
At the same time as the previous data, the clock is inhibited for two clocks of the signal, and the output from the OR gate 30 is not accepted and the output from OUT is held. The output OUT outputs an "H" level when the FSK signal has a higher frequency, and outputs a demodulated binary signal as a "L" level when a lower frequency signal is present. Also, the output change point of OUT is R
This is obtained by the falling edge of R, but since the counting operation of each counter continues until the rising edge of R, after being reset by R, each 22, 2
The outputs of 4, 26, and 28 are taken in to obtain a stable output.

As described above, the present invention performs demodulation based on the value of the four zero-crossing periods. To explain the effects of the present invention in detail, the original signal and noise are added at the zero-crossing detection point, resulting in a zero-crossing detection period error, and the code is This results in distortion and sign errors. It goes without saying that the periodic error due to this noise is determined by the ratio of the noise to the high level of the signal, and as the noise level increases, the periodic error also increases. However, since this error is the same at each zero-crossing point, the S/N ratio can be relatively improved by accumulating the period value of the count C signal over a plurality of zero-crossing periods. In other words, the frequency that we want to determine in the counter value is N times larger, but the error due to noise is the same as one zero-cross detection period, and it is an error due to the start point and stop point of the counter, so the S/N is improved by N times. If it is 4 times
It also improves by 12dB. A further advantage of the present invention is that by accumulating multiple zero-cross detection periods using multiple counters for discrimination, it is possible to increase the difference when the FSK signal changes, thereby improving the S/N ratio and the discrimination accuracy. It is. In other words, the FSK signal changes relatively slowly and continuously due to the influence of the filter and line.If this is T1→T2→T3→T4→T5 and T1>T2>T3>T4>T5, the counter output of the counter is T1+T2+T3+T4. The change from T2+T3+T4+T5 is taken in the next Xerox detection cycle. Then, the difference in the change in the counter value due to zero-sloss detection becomes T1-T5, which is larger than the difference between adjacent T1 and T2, and the detection accuracy increases.

Another advantage of the present invention is that since the plurality of counters are an even number, if one focuses on a particular counter, it always operates with the zero cross comparator output in the same trigger direction. This is to correct the point where it is difficult to set the zero-crossing point of the comparator perfectly at the midpoint between the + side and the - side, which tends to cause some unbalance. Furthermore, since it is not easy to maintain a balance between the + side and the - side and limit the amplitude of the limiter, counting only with the trigger in the same direction according to the present invention is extremely effective.

As described above, according to the present invention, since discrimination results can be obtained at many zero-crossing points, phase distortion (phase shift) of the demodulated output can be improved, and discrimination can be performed based on the results counted between multiple zero-crossing points. Therefore, the noise margin increases at the threshold for discrimination, and the S/N ratio is improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an FSK demodulation circuit according to an embodiment of the present invention. FIG. 2 is a timing chart of the zero-cross detection method of the present invention. FIG. 3 is a circuit diagram of a counter selection circuit in an embodiment of the FSK demodulation circuit of the present invention. Figure 4 shows the present invention.
3 is a timing chart of a counter selection circuit in an embodiment of an FSK demodulation circuit. FIG. 5 is a circuit diagram around the counter of the demodulation circuit in an embodiment of the FSK demodulation circuit of the present invention. 1...Reception amplifier, 2...Band pass filter, 3...Limiter, 4...Comparator, 5...
...Demodulation circuit, FS...FSK signal, ZC1...Zero cross comparator output signal, 11...1/4 frequency divider circuit, 16, 17, 18, 19...Demodulation counter and discrimination circuit.

Claims (1)

[Claims] 1 Consists of different frequencies corresponding to the original binary signal
A detection circuit that detects a zero crossing point included in an FSK signal and a clock signal count during the period between the consecutive zero crossing points detected by the detection circuit are counted at consecutive N+1 (N is a plurality of constant values) times. N period counters that operate for N periods between the zero crossing points; and a period counter that starts counting from among the N period counters in response to the detection circuit detecting the zero crossing point. A selection circuit that sequentially selects the zero crossing points, and a circuit that outputs a determination result from the count value of the period counter that has finished counting in response to the detection circuit detecting the zero crossing points, Two period counters among the N period counters that sequentially start counting in response to detection overlap and count for N-1 periods between the zero crossings,
An FSK demodulation circuit characterized in that a demodulated signal of the original binary signal is obtained based on the determination result.