JPH018046Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital frequency discrimination circuit used in a frequency modulation type modulation/demodulation device and the like.

When demodulating frequency-modulated signals such as frequency-shifted (hereinafter referred to as FS) signals, DPLL (Digital
A Phase Lock Loop.) type frequency discrimination circuit is used, and this has the configuration as shown in the block diagram of FIG.

The principles and operating conditions of the DPLL type frequency discrimination circuit are described in detail in Chapters 8.3 and 9.2 of ``How to Use PLL-IC'' (Sanpo Publishing Co., Ltd., first edition published November 20, 1976). This is a well-known method, and its outline is as follows.

In other words, Fig. 1 shows the configuration shown in Figs. 9 and 17 in the above-mentioned "How to use PLL-IC" by replacing the gate control circuit shown in the same figure with a variable frequency divider VD, which is programmable. A variable frequency divider VD using a counter etc. divides the frequency of the clock pulse from the clock terminal CL, and also divides the frequency of the clock pulse from the clock terminal _CL .
The _frequency division ratio is set according to the setting signal applied to the control terminal C, and the frequency division ratio is sequentially switched according to the control signal applied to the control terminal C. The output is further frequency-divided by a fixed frequency divider FV consisting of flip-flop circuits (hereinafter referred to as FFC) FF ₁ to FF _o , and then provided to the input of an exclusive OR (hereinafter referred to as EXOR) gate G ₁ .

Furthermore, the other input of the EXOR gate G ₁ is given an FS signal from the input terminal IN, which is shifted to frequencies _a and _b , and the EXOR gate G ₁
, the phase difference between both input signals is detected, and this detection output becomes a pulse signal with an average value proportional to each cycle of frequencies _a and _b in the FS signal, so this is averaged by a reduction filter LPF. Furthermore, it is sent to the output terminal OUT as demodulated output.

Note that the detection output of EXOR gate _G1 is applied as a control signal to variable frequency divider VD, whereby the frequency division ratio of frequency divider VD is successively switched.

However, if the frequency of the FS signal is two waves _a and _b , the frequency division ratio of the variable frequency divider VD is 1/N ₁ , 1/
When the detection output is set to " _H " (high level), the frequency division ratio becomes 1/N ₁ and an output of frequency ₁ is sent out, and the detection output is "L" (low level). When , the frequency division ratio is 1/N ₂ and output with frequency g ₁ is sent out, so the fixed frequency divider is
If the frequency division ratio of FD is 1/N, the frequency divider FD changes its output every time it counts N/2 outputs of the variable frequency divider VD.

Furthermore, in order to ensure reliable frequency division operation, the variable frequency divider VD is configured so that the frequency division ratio is not switched by the control signal while counting clock pulses, but after a predetermined count has finished. ing.

FIG. 2 is a time chart showing the waveforms of each part in FIG. 1, and the time axis is enlarged to focus on the clock pulse.
is divided by the variable frequency divider VD and output b is _obtained . The frequency division ratio of VD is switched, and the frequency of output b changes between _1/1 and 1/ _g1 .

However, since the clock pulse a and the FS signal d are asynchronous, switching is not necessarily performed when the variable frequency divider VD finishes counting and the output b pulse is generated; If the output e changes, the frequency division ratio is switched after a predetermined count is completed, so there is a time t ₁ or t ₂ between the change point of the detected output e and the switching of the frequency division ratio. This causes a delay, which affects the detection output e and appears as a jitter (source movement on the time axis) at the change point in the detection output e, the maximum value of which is equivalent to one cycle of the output b. .

Note that if this jitter is expressed in terms of time, the maximum is ±1/2 ( _1/1 +1/g ₁ ) (sec) (1). However, ₁ and g ₁ are often close in frequency, and equation (1) can be approximated as ±1/g ₁ (sec) (2).

Jitter expressed by equation (2) is generally a low frequency component and appears as low frequency noise, but it cannot be removed by the reduction filter LPF, and the output terminal
Since the signal is sent directly to the OUT, this becomes a noise component in the demodulated output and becomes a major factor in deteriorating the functions of the modulator and demodulator.

As a countermeasure for this, it is possible to increase the frequency division ratio of the fixed frequency divider FD while increasing the frequency of the output b obtained from the variable frequency divider VD.
Increasing the number of counting stages using FFC, FF ₁ to FF _o becomes expensive, and changing the frequency division ratio
This results in the disadvantage that the response characteristics of the DPLL circuit change.

Further, in order to increase the frequency of the output b, the frequency of the clock pulse a must also be increased, and there is a limit due to the structure of the clock pulse generation source, and both of these are disadvantageous in terms of manufacturing cost.

The present invention has the purpose of fundamentally resolving these conventional drawbacks, and makes a particularly large change in the configuration by forcibly resetting the variable frequency divider when the detection output of the EXOR gate changes. The present invention provides an extremely effective digital frequency discriminator circuit that significantly reduces the occurrence of jitter.

The details of the present invention will be explained below with reference to FIG. 3 and subsequent figures showing embodiments.

In the block diagram of Fig. 3, the waveforms of each part are shown in the time chart of Fig. 4. A clock pulse a of frequency _c is applied to the clock terminal CL, which is divided by a variable frequency divider VD and output. The phase difference between the FS signal c as an input signal given to the input terminal IN and the output d of the fixed frequency divider FD is given as b to the fixed frequency divider FD.
It is detected by the EXOR gate _G1 , and this detection output e is given as a control signal to the variable frequency divider VD to control its frequency division ratio.

The detection output e is sent to the output terminal OUT via the reduction filter LPF, and is also given to the pulse generator PG, and is connected between the EXOR gate G ₂ and the resistor R ₁ connected between its input. and capacitor
The pulse generator PG, which is composed of an integrator circuit based on _C1 , generates a reset pulse f based on a change in the detection output e, and thereby
The VD is being reset.

However, in this case as well, the frequency division ratio of the variable frequency divider VD can be changed to 1/1 by applying the setting signal to the setting terminals _t1 to _tn .
It is assumed that two types are set: N ₁ and 1/N ₂ .

Therefore, due to a change in the detection output e, the variable frequency divider VD starts a new counting operation immediately after being reset, and the frequency division ratio when the detection output e is "H" is set to 1/ If the frequency division ratio when the output e is "L" is 1/N ₂ , the output b of the variable frequency divider VD is as follows while the detection output _e is "H".
Depending on the frequency of ( _c /N ₁ ) = ₁ , the detection output e
While is "L", the output b has a frequency of ( _c / _N2 )= _g1 , and this is applied to the fixed frequency divider FV.

However, since the FS signal c and the clock pulse a are asynchronous, when the variable frequency divider VD is reset and the frequency division ratio is switched, the output b becomes irregular and some jitter occurs in the detection output e.

However, this jitter is ±1/2 _c (sec) at the change point of the detection output e, and
Just before the change, ±1/2g ₁ (sec),
When g ₁ < ₁ , the maximum jitter is ±(1/2 _c + 1/2 _g1 ) (sec) ...(3) However, since generally f _c ≫ ₁ , g ₁ , the maximum jitter is approximately , ±1/2 _g1 (sec) ...(4), which is 1/2 of equation (2), and the jitter is significantly reduced compared to the conventional one.

FIG. 5 is a block diagram showing another embodiment, and as the waveforms of each part are shown in the time chart of FIG. 6, it operates in the same manner as in FIG. 3.

However, the pulse generator PG has an EXOR gate
A two-stage cascade connected between G ₂ and its input and triggered sequentially by clock pulse a.
It is composed of FFC・FF ₁₁ and FF ₁₂ , and assuming that FFC・FF ₁₁ and FF ₁₂ are initially in the set state, since the output Q of FFC・FF ₁₂ is “H”,
When the detection output e changes to "L", the output of EXOR gate _G2 becomes "H", and this is sent out as a reset pulse f.

Then, due to the rise of the clock pulse a following the time when the reset pulse f becomes "H",
FFC/FF ₁₁ is triggered and enters the reset state to set the output Q to "L". When FFC/FF ₁₂ is triggered by the falling edge of clock pulse a inverted by inverter IN ₁ , _FF12
also enters the reset state, and by turning its output Q to “L”, the output of EXOR gate _G2 becomes “L”.
Then, the sending of the reset pulse f is completed.

In addition, if the detection output e becomes "H" when FFC・FF ₁₁ and FF ₁₂ are in the reset state, the same
Since FFC・FF ₁₁ and FF ₁₂ are sequentially triggered and enter the set state, the reset pulse f is also applied at this time.
occurs.

In addition, in FIG. 5, the frequency dividing operation of the variable frequency divider VD is stopped during the period of the reset pulse f, and the frequency dividing operation is started when the reset pulse f ends, but the occurrence of jitter is shown in FIG. This is the same as, and the result is given by equation (4).

Note that the number of frequency division ratio settings of the variable frequency divider VD can be set according to the frequency type of the input signal, and the same can be done even if a differentiating circuit is used as the pulse generator PG. Various modifications can be made. be.

As is clear from the above explanation, according to the present invention, the amount of jitter generated is significantly reduced, and the noise component of the demodulated output is also reduced accordingly, thereby improving the functionality of modulation and demodulation devices, etc. Great effects can be obtained as a frequency discrimination circuit.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the conventional example, Fig. 2 is a time chart showing waveforms of each part in Fig. 1, and Fig. 3 is a time chart showing the waveforms of each part in Fig. 1.
The figure is a block diagram showing an embodiment of the present invention, FIG. 4 is a time chart showing waveforms of each part in FIG. 3, FIG. 5 is a block diagram showing another embodiment, and FIG.
The figure is a time chart showing the waveforms of various parts in FIG. VD...Variable frequency divider, FV...Fixed frequency divider, _G1 ,
G ₂ ...EXOR gate (exclusive OR gate),
PG...Pulse generator, _R1 ...Resistor, _C1 ...Capacitor, _FF11 , _FF12 ...FFC (flip-flop circuit).

Claims (1)

[Claims for Utility Model Registration] (1) Variable frequency division in which a clock pulse is frequency-divided, a plurality of frequency division ratios are set according to a setting signal, and the frequency division ratios are switched according to a control signal. a fixed frequency divider that divides the output of the variable frequency divider according to a predetermined frequency division ratio; a phase difference between the output of the fixed frequency divider and the input signal is detected, and the detected output is used as the control signal; and a pulse generator that generates a reset pulse based on a change in the detected output of the exclusive OR gate to reset the variable frequency divider. A digital frequency discrimination circuit featuring: (2) A utility model characterized by using a pulse generator consisting of an exclusive OR gate and an integrating circuit connected between one input and the other input of the exclusive OR gate. Scope of registration claims 1st
The digital frequency discrimination circuit described in Section 1. (3) A pulse generator consisting of an exclusive OR gate and a two-stage cascaded flip-flop circuit connected between one input and the other input of the exclusive OR gate and sequentially triggered by a clock pulse. A digital frequency discrimination circuit according to claim 1, characterized in that the digital frequency discrimination circuit uses: