JPH0376057B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a bit synchronization device for obtaining sampling pulses necessary for extracting the contents of each bit from an input NRZ signal.

Conventional configuration and its problems Traditionally, this type of bit synchronizer
The timing of the signal change point is compared with the timing of the sampling pulse generated by the sampling pulse generator, and based on the results, the timing of the sampling pulse is adjusted to the optimal sampling point for each bit of the input NRZ signal. This is achieved by controlling the phase so that it is located approximately at the center.

Specifically, a timing comparison device that compares the timings and a sampling pulse generator that generates the sampling pulses and whose output phase can be controlled externally are realized using dedicated hardware, and further, based on the output results of the timing comparison device, A phase control device that supplies a signal for controlling the phase of the sampling pulse to the sampling pulse generator is realized by dedicated hardware or a microcomputer programmed to perform an equivalent function. In particular, when the above-mentioned phase control device is realized by a microcomputer, it is rare that only the functions of the above unit are realized by the microcomputer. Rather, the above-mentioned phase control device is In many cases, the functions of the device are realized together with other processing functions on the same microcomputer.

Furthermore, for example, in systems that require equipment to be compact, lightweight, and low in power consumption, such as in decoders for pager receivers, the entire system may be implemented on a microcomputer.
In many cases, it is configured as a single-chip LSI with dedicated hardware added, and in such cases, by minimizing the amount of dedicated hardware added, it is possible to reduce the power consumption of the LSI, and to reduce the power consumption of the LSI itself. By reducing the chip area of
It is necessary to improve the yield rate during LSI manufacturing.

However, in the above-mentioned bit synchronizer, which is a conventional phase control device configured using a microcomputer, it has two separate functions, a timing comparator and a sampling pulse generator, in addition to the microcomputer. A device with dedicated hardware was required, resulting in a large LSI chip area and high power consumption.

Purpose of the Invention In view of the above points, the present invention reduces the amount of hardware added to a microcomputer, reduces the chip area of an LSI, reduces power consumption, and further improves the yield during LSI manufacturing. Its purpose is to provide a bit synchronizer.

Structure of the Invention The present invention comprises a pulse generating means for generating a first sampling pulse for sampling a digital input signal a plurality of times in one bit time; a storage means for storing an input signal; a pulse number increase/decrease means for inputting the first sampling pulse and increasing or decreasing the number of pulses per unit time of the first sampling pulse based on an increase/decrease control signal; and the number of pulses. a frequency divider that divides the frequency of the pulse signal sent from the increase/decrease means and generates a second sampling pulse for data extraction; and when the frequency divider generates the second sampling pulse, as an interrupt process, the memory The means starts referring to the stored input signal, determines the phase relationship between the input signal and the second sampling pulse, and outputs the increase/decrease control signal to the pulse number increase/decrease means based on the determination result. A control means is provided.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail.

FIG. 1 shows a specific embodiment of a bit synchronizer according to the present invention. 1 in the figure is a pulse generator that generates a sampling pulse A, and the output B of the high-order pulse generation circuit 2 is divided into a frequency dividing circuit 3.
Sampling pulse A is obtained by dividing the frequency by . Note that the frequency dividing ratio of the frequency dividing circuit 3 in this embodiment is 8. The other input C input to the frequency dividing circuit 3 is a control signal for controlling the phase of the sampling pulse A, which will be described later.

4 is a microcomputer (for example, MN-1500 series manufactured by Matsushita Electronics Co., Ltd.) having an interrupt function and a parallel/serial interface function, and the timing of the change point of the input NRZ signal D,
It is programmed to have the function of comparing the timings of the sampling pulses A and supplying the phase control signal C to the frequency dividing circuit 3 based on the result to control the phase of the sampling pulses A. In the figure, for convenience of explanation, the microcomputer 4 is shown divided into a serial interface section 5 consisting of a shift register and a processing and control section 6.

In the serial interface section 5 of the microcomputer 4, the input NRZ signal D is sampled by the high-order pulse B and stored over at least one bit time length.

FIG. 2 is a flowchart for explaining the operation of the microcomputer 4 of FIG. 1, and the operation of the circuit configuration of FIG. 1 will be explained together with this flowchart. When the sampling pulse A is input to the interrupt terminal 61 of the processing and control unit 6 of the microcomputer 4, the NRZ signal stored in the shift register of the serial interface unit 5 is changed to The contents of the NRZ signal over one bit time length sampled and stored by the sampling pulse B before the time point are taken into the processing unit 6,
Based on the content, it is determined whether the timing of the sampling pulse A was appropriate. For example, as shown in FIG. 3, if the data read from the shift register 5 is in the state a, the timing of the sampling pulse A is too early; if it is in the state b, the timing of the sampling pulse A is too slow; If the state is d, it is appropriate; if the state is d, it is unknown."

Based on the result of the above judgment, the control and processing section 6 controls the phase of the sampling pulse A by supplying the phase control signal C from the output interface terminal 63 to the frequency dividing circuit 3.

Phase control is performed, for example, as described below. FIG. 4 shows a detailed example of the frequency dividing circuit 3, and FIG. 5 shows a timing diagram. In FIG. 4, when phase control is not performed, the state of the phase control signal C is always "High", so the high-order clock pulse B is supplied to the divide-by-8 circuit 32 through the NAND gate circuit 31. A signal obtained by dividing pulse B by eight is obtained as sampling pulse A.
To advance the phase of sampling pulse A, as shown in Figure 5a, when the state of high-order clock pulse B is "High", the phase control signal C is temporarily set to "Low", and the frequency is divided by eight. This is achieved by making the input signal E of the circuit 32 appear to have a predetermined number of new pulses added to the high-order clock pulse B, thereby accelerating the generation of the sampling pulse A. In order to delay the phase, as shown in FIG. This is carried out by apparently removing a predetermined number of pulses, reducing the number of pulses of the input signal to the divide-by-8 circuit 32, and delaying the generation of the sampling pulse A.

The timing for turning the control signal C to "Low" can be determined, for example, by monitoring the state of the high-order clock pulse B by inputting it to the input interface terminal 62 of the control and processing section, as shown in FIG. I'll do it.

Effects of the Invention As explained above, the present invention includes a pulse generating means for generating a first sampling pulse for sampling a digital input signal a plurality of times in one bit time, and a pulse generating means for generating a first sampling pulse for sampling a digital input signal a plurality of times in one bit time; a storage means for storing an input signal having a length of 1 bit time as a signal; and a pulse number for inputting the first sampling pulse and changing the number of pulses per unit time of the first sampling pulse based on an increase/decrease control signal. a frequency divider that divides the frequency of the pulse signal sent from the pulse number increase/decrease means and generates a second sampling pulse for data extraction; and when the frequency divider generates the second sampling pulse. , as an interrupt process, start referring to the input signal stored in the storage means, determine the phase relationship between the input signal and the second sampling pulse, and, based on the determination result, cause the pulse increase/decrease means to By providing a control means for outputting an increase/decrease control signal, it becomes possible to realize a bit synchronizer with a simple hardware configuration. In particular, by using a microcomputer, the present invention not only makes it possible to use the serial interface function built into a general-purpose microcomputer as the storage means, but also allows the control signal for phase control to have a simple structure. Because it has a waveform of Therefore, when the bit synchronizer according to the present invention is incorporated as part of a signal processing system in digital communication intended for use in a general-purpose microcomputer, the number of necessary external components can be kept to an extremely small number.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the bit synchronizer according to the present invention, FIG. 2 is a flowchart illustrating an overview of the operation of the microcomputer section in the block diagram of FIG. 1, and FIG. 3 is a flow chart of the timing comparison device. A diagram showing an example of the contents of the shift register of the serial interface section of the microcomputer used as a part, FIG. 4 is a detailed circuit diagram of the frequency dividing circuit section of FIG. 1, and FIGS. 5 a and b are sampling pulse A FIG. 3 is a timing diagram illustrating the phase control process of FIG. DESCRIPTION OF SYMBOLS 1... Pulse generator, 2... High-order pulse generation circuit, 3... Frequency dividing circuit, 4... Microcomputer, 5... Serial interface section, 6... Processing and control section, 61... Interrupt terminal , 62...
Input interface terminal, 63...Output interface terminal, 31...NAND gate, 32
...8 frequency divider circuit.

Claims (1)

[Claims] 1. Pulse generating means for generating a first sampling pulse for sampling a digital input signal a plurality of times during one bit time, and a pulse generating means for generating the first sampling pulse generated by the pulse generating means. storage means for storing the input signal having a length of 1 bit time as an input signal, and the first sampling pulse generated by the pulse generation means, and the unit time of the first sampling pulse is input based on the increase/decrease control signal. a frequency divider that divides the frequency of the pulse signal sent from the pulse number increase/decrease means to generate a second sampling pulse for data extraction; and the frequency divider. generates the second sampling pulse, as an interrupt process, it starts referring to the input signal stored in the storage means, determines the phase relationship between the input signal and the second sampling pulse, and processes the input signal. A bit synchronizer comprising: control means for outputting the increase/decrease control signal to the pulse number increase/decrease means based on a determination result.