JPH0374536B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a differential PCM transmission method (DPCM) in which the difference between a sample value of an input signal and its predicted value is quantized and encoded and transmitted. The present invention relates to a differential PCM code decoder that performs adaptive quantization and adaptive prediction with a small number of encoded bits and a large prediction effect on an analog input signal that has a wide range of level changes and non-stationary parts like a signal.

(b) Conventional technology and problems In the PCM method, analog signals are sampled, and the sample values are quantized and encoded before being transmitted.
In the DPCM method, the sample value of the next signal is predicted from the past sample value, and only the difference (prediction error) between the predicted value and the actual sample value is quantized, encoded, and transmitted.

Regarding the circuit configuration of the conventional DPCM system, the encoder side is shown in FIG. 1a, and the decoder side is shown in FIG. 1b.

In the figure, Q is a quantizer, Q ^-1 and Q ^-1 ' are inverse quantizers, SA and SA' are quantization step adaptation circuits,
P, P' are predictors, SPL is sampling circuit, A1, A
2. A5 is adder, C is PCM modulator, D is PCM
Demodulator, LPF indicates low pass filter.

In FIG. 1a showing the encoder side, the analog input signal Sin(t) is sampled by the sampling circuit SPL at time ti (where i=1, 2, 3, . . . ), and the sampled value is designated as Xi. Predictor P is X1, X2, X3...Xn
−1 is stored, and the predicted value X^n of the input sample value Xn at the next sample time tn is predicted according to a predetermined rule. Adder A1 (operates as a differential circuit) takes the difference between Xn and X^n and generates a prediction error En. The prediction error En is quantized by a step width Δn in a quantizer Q, and the output is a binary code In.
occurs. The output binary code In of the quantizer Q is modulated by the next-stage PCM demodulator C and output to the transmission line, but on the other hand, it is decoded into an analog quantity E^n by the inverse quantizer Q ^-1 and sent to the predictor P. Feedback will be sent to you. That is, the decoded error E^n is added to the predicted value X^n of the sample value Xn in the adder A2 to form the decoded sample value X〓n, which is added to the predictor P to predict the next input sample value X _o+1. is memorized.

On the other hand, on the decoder side, input Pin is demodulated by PCM demodulator D, then input to inverse quantizer Q ^-1 , and its output
En' and the output of the predictor P' are added together in an adder A5,
Input to the low-pass filter LPF as X〓n. The step width of the inverse quantizer Q ^-1 is determined by the quantization step adaptation circuit.
Determined by SA′ output.

Here, the non-stationarity of the level change of the analog input signal Sin(t) increases, the amplitude change of the prediction error increases, and the quantization step Δn of the quantizer Q is too small, resulting in the possibility of slope overload. When I came,
Adaptive quantization is performed by the quantization step adaptive circuits SA, SA', which increases the quantization step Δn to make the scale coarser, and when it is smaller, the quantization scale becomes denser. However, in the case of a signal input having a wide level change range, such as an audio signal, there is a problem in that the encoding cannot follow the input level change and large slope overload distortion remains.

Quantization noise (coding distortion) of PCM code decoder
In addition to slope overload distortion caused by the tracking characteristic for changes in the input signal, there is particle noise caused by encoding when the input signal level is small.
There is also the problem that particle noise increases when the adaptation speed is increased by increasing the quantization step Δn for input signals with large changes. Furthermore, since the predictor P having the configuration shown in the figure is included in the feedback system, there is also the problem that if the adaptation speed is too high, the system will become unstable due to a slight transmission bit error.

(c) Object of the Invention The object of the present invention is to provide a differential PCM code that can particularly reduce slope overload distortion for analog signals with unsteady parts without increasing quantization noise or increasing system instability. The purpose is to provide a device decoder.

(d) Configuration of the Invention In the present invention, the encoder side of the differential PCM code decoder includes a first quantizer circuit that encodes a difference value between an input signal and a prediction signal for the input signal, and the first quantizer circuit. a second quantizer circuit that encodes a quantization error obtained by taking a difference between an input value to the quantizer circuit and a dequantized value of the output value of the first quantizer circuit; The decoder side includes the first and second
comprising first and second decoders that respectively decode the code values of the quantizer circuits, and transmit the code values obtained by the first and second quantizer circuits to the decoder side, respectively; The decoder side is configured to reproduce the input signal by decoding the received code values by the first and second decoders and adding them.

(e) Embodiments of the invention An embodiment of the invention will be described with reference to FIG. FIG. 2 is a block diagram showing only the encoder and decoder portions that are particularly relevant to the present invention, where a represents the circuit configuration on the encoder side and b represents the circuit configuration on the decoder side. In FIG. 2, the same letters as in FIG. 1 indicate circuits with the same function. As shown in Figure 2, the new characters COD1 and COD1 are the first and second differential encoders, DEC1 and EC2 are the first and second differential encoders, respectively.
second differential decoder, L21, L22, L21',
L22' is a logic circuit, S21, S22, S21',
S22' is a selector circuit, Z ^-1 is a delay circuit, M1~
M5 is a multiplier, and A3, A4, A6, and A7 are added adders. Note that the encoder in FIG. 2a has a total number of encoded bits per sample of the input signal of 4 bits, and the first differential encoder COD
This shows an example of a circuit in which 3 bits are allocated to code 1 and 1 bit is allocated to second differential encoder COD2. Also
COD1 is a conventional differential PCM encoder (adaptive type)
Although 3-bit quantization is performed using the same configuration as shown in FIG. 1, COD2 is a 1-bit differential encoder, so it is a so-called delta modulation encoder (adaptive type).

The sample value Xn of the input signal is first input to the first differential encoder
COD1 undergoes conventional differential quantization and outputs the quantization error as a 3-bit binary code I ₁ (n). At this time, the difference signal Q^n between the prediction error signal En generated at the input of the quantizer Q of COD1 and the decoded value E^n of the inverse quantizer Q ^-1 is input to the second differential encoder COD2. 1 bit delta modulated code I ₂ (n)
It is output separately as .

In COD2, selectors S21 and S22
is controlled by the logic circuit L21, and the logic circuit L
21 generates a signal e which becomes "1" when the output I ₁ (n) of COD 1 exhibits the maximum amplitude, and which becomes "0" at other times. The selector S21 selects the signal S1 when the signal e is "1", and selects the signal S1 when the signal e is "0".
Select the value 0 when . Selector S22 receives signal e
When e is "1", signal S2 is selected, and when e is "0", signal S3 is selected. Signal S3 is the first encoder
Equal to the quantization step value Δn in COD1.
The quantizer Q2 encodes whether the polarity of the difference between the quantization error component Q^En of COD1 and the output value of the selector S21 (the difference value in the adder A4) is positive or negative, and generates a 1-bit code I ₂ (n). Output. Similar to the step size companding control circuit in the adaptive delta modulation encoder, the logic circuit L22 outputs the output I ₂ (n) and the previous sample value.
If the output I ₂ (n-1) for Xn _-1 is the same code word, a coefficient S4 is generated which has a value of 1 or more, and if they are different, a value of 1 or less. Therefore, the signal S2 is the selector S2
2 multiplied by the coefficient S4. More than
This is the configuration and operation of COD2.

When the input signal Xn is stationary and COD1 can follow Xn, the output I ₁ ((n) becomes an intermediate code word, so the output e of the logic circuit L21 in COD2 becomes "0" and Q2 is simple. In this case, only positive or negative values of Q^En are encoded, and equivalently 4-bit quantization is performed.When the input signal Xn becomes non-stationary and COD1 cannot follow it, the output I ₁ (n) continues to send out the maximum codeword. In this case, the logic circuit L
The output e of 21 becomes 1. That is, the signal S2 is a value obtained by multiplying the initial value by the coefficient S4 by the multiplier M1, with the initial value immediately before the signal e becomes 1, and the signal S2 is the value obtained by multiplying the coefficient S4 by the multiplier M1.
COD2 becomes an adaptive delta modulation circuit that follows the value of the quantization error Q^En of the first encoder.
Until COD1 can follow the input signal and the output I ₁ (n) takes a value other than the maximum code word, COD2 functions to correct the slope distortion generated in COD1.

Next, on the decoder side, the differential encoder circuit
Differential decoder circuit DEC corresponding to COD1 and COD2
1 and DEC2 are configured, but DEC1 is the same as a conventional adaptive differential decoder. DEC2 inverse quantizer
Q ₂ ^-1 generates values of +0.5 and -0.5 depending on the sign of the decoder input I ₂ '(n). Logic circuit L'21 controls selectors S'21 and S'22, and when input _I'1 (n) is less than the maximum value, multiplier M2 multiplies the step size Δn in DEC1 by 0.5.
The output of Q ₂ ^-1 multiplied by 3 is Q^En′
The adder A6 adds the output X^'n of the DEC1 to obtain the final decoded value X〓n. When the decoder input _I1 '(n) reaches the maximum value, the step size Δn of DEC1 immediately before the maximum value is taken as the initial value, and the output of the logic circuit L'22 is used as the multiplier M5, similar to the encoder side. Adder A7 adds the output of multiplier M4 to the value S5 multiplied by
is added to the value Q^En', and added to the output X^'n of the DEC1 in the adder A6. At this time, actually, a value obtained by multiplying S5 by a value of 1.5 or a value obtained by multiplying by 0.5 is added in adder A6 depending on the input I ₂ '(n).

(f) Effects of the Invention As detailed in the present invention, the quantization error in the non-stationary portion of the input signal is reduced, and the circuit configuration of the present invention, that is, the prediction circuit of the subsequent quantization encoder, has a feedback Since it is not a system, it has the effect of not becoming unstable even if there is a transmission bit error.

[Brief explanation of drawings]

FIG. 1 is an overall block diagram of a conventional differential PCM code decoder, and FIG. 2 is a block diagram of an encoder/decoder related to the present invention. In the figure, COD1 and COD2 are differential encoders,
DEC1 and DEC2 are differential decoders, Q is a quantizer,
Q ^-1 is an inverse quantizer, SA is a quantization step adaptation circuit, P is a predictor, L21 and L22 are logic circuits, and S
21, S22 is a selector, SPL is a sampling circuit, C
is a PCM modulator, D is a PCM demodulator, LPF is a low-pass filter, A1 to A7 are adders, M1 to M5 are multipliers, and ZQ ^-1 is a delay circuit.

Claims (1)

[Claims] 1. A differential PCM code decoder that predicts the next sample value from past sample values of an input signal, quantizes and encodes the difference value between the predicted value and the actual sample value, and transmits it. and the encoder side includes: a first quantizer circuit that encodes a difference value between an input signal and a prediction signal for the input signal; and an input value to the first quantizer circuit and the first quantizer circuit.
The second code encodes the quantization error obtained by taking the difference between the output value of the quantizer circuit and the inverse quantization value.
a quantizer circuit; the decoder side includes first and second decoders that decode the code values of the first and second quantizer circuits, respectively; Each of the code values obtained by the quantizer circuit is transmitted to the decoder side, and the decoder side transmits each of the received code values to the first,
A differential PCM code decoder characterized in that an input signal is reproduced by decoding and adding with a second decoder.