JPS6058722A - Differential pcm code decoder - Google Patents

Abstract

PURPOSE:To reduce slope overload distortion without increasing quantized noises and instability of the system by applying differential coding to a sample value at the 1st differential quantizing circuit at the coder side, applying differential coding to the error at the 2nd differential quantizing circuit and adding and decoding two codes at the decoder side. CONSTITUTION:When an input signal Xn is normal and a COD1 can follow up the Xn, since an output I1(n) becomes an intermediate code word, an output (e) of a logical circuit L21 goes to ''0'', the quantizer Q2 codes only simply whether the value of the quantized error QEn is positive or negative and the quantization of 4 bits is attained equivalently. When the signal Xn is not normal, an output 11(n) keeps the transmission of maximum code word. In this case, a signal S2 becomes a value where the value just before the signal (e) goes to 1 is taken as the initial value and the coefficient S4 is multiplied by amultiplier M1, and a COD2 becomes an adaptive delta modulation circuit following up the value of the quantized error QEn of the COD1. The slope distortion generated by the COD1 is corrected by the COD2 until the output I1(n) takes a value other than the maximum code word. Decoders DEC1, 2 are constituted in the decoder side in correspondence to the COD1, 2.

Description

Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to a differential PCM transmission method (DPCM) in which the difference between a sample value of an input signal and its predicted value is quantized and encoded and transmitted.
), a differential PCM code decoder performs adaptive quantization and adaptive prediction, which have a small number of encoded bits and a large prediction effect, especially for analog input signals such as audio signals, which have a wide level change range and non-stationary parts. Regarding.

(b) Prior art and problems In the PCM method, an analog signal is sampled, and the sample value is quantized, encoded, and transmitted, but in the DPCM method, the sample value of the next signal is predicted from the past sample value. Only the difference (prediction error) between the predicted value and the actual sample value is quantized, encoded, and transmitted.

Regarding the circuit configuration of the conventional DPCM system, the encoder side is shown in FIG. 1, and the decoder side is shown in FIG.

In the figure, Q is a quantizer, C/ca7/- is an inverse quantizer, SA, SA'' is a quantization step adaptation circuit, and P
, P′ is the predictor, SPL is the sampling circuit, AI, A
2. A5 is an adder circuit, C is a PCM modulator, and D is a PCM
Demodulator, LPF indicates a low pass filter.

In FIG. 1(a) showing the encoder side, the analog input signal Sin (t) is input at time ti by the sampling circuit SPL.
(where i = L2, 3 . . . ), and the sampled value is assumed to be Xi. The predictor P is XI, X2. X3
. Adder circuit AI (operates as a differential circuit) takes the difference between Xn and Xn and generates a prediction error En.

The prediction error En is quantized by a step width Δn in a quantizer Q, and a double code In is generated as an output. The output binary code In of the quantizer Q is modulated by the next stage PCM modulator C and output to the transmission line.
It is decoded into an analog quantity En and fed to the predictor P. That is, the decoded error En is added to the W circuit A2.
, the sample value Xn is added to the predicted value Xn to obtain a decoded sample value Xn, which is stored in the predictor P to predict the next input sample value Xn-tt.

On the other hand, on the decoder side, input Pin is demodulated by a PCM demodulator, inputted to an inverse quantizer Q, and its output En' and predictor P' are added by a small output adder A5, and the low frequency Input to filter LPF. The step width of the inverse quantizer Q-/ is determined by the output of the quantization step adaptation circuit SA'.

Here, the non-stationarity of the level change of the analog input signal Sin (t) increases, the amplitude change of the prediction error becomes large, and the quantization step Δn of the quantizer Q is too small, resulting in the possibility of slope overload. When the quantization step is large, the quantization step adaptation circuits 5A and S4' perform adaptive quantization in which the quantization step Δn is increased to make the scale coarser, and when the quantization step Δn is small, the quantization scale is made denser. However, in the case of a signal input having a wide level change range, such as an audio signal, there is a problem in that the encoding cannot follow the input level change and large slope overload distortion remains.

Quantization noise (encoding distortion) of a PCM code decoder includes not only slope overload distortion caused by the tracking characteristic for changes in the input signal, but also particle noise caused by encoding when the input signal level is small. There is also the problem that particle noise increases when the adaptation speed is increased by increasing the quantization step Δn for input signals with large changes. Furthermore, since the predictor P having the configuration shown in the figure is included in the feedback system, there is a problem that if the adaptation speed is too high, the system will become unstable due to a slight transmission bit error.

(C) Object of the Invention The object of the present invention is to provide a differential PCM that can particularly reduce slope overload distortion for analog signals with unsteady parts without increasing quantization noise or increasing system instability.
Provides an encoder-decoder.

(d) Structure of the Invention In the present invention, two
A first differential quantizer circuit differentially encodes and transmits a sample value of an input signal, and a quantization error value generated in the differential quantizer circuit is transmitted to a second differential quantizer. The circuit also differentially encodes.

On the decoder side, a circuit is configured to obtain a final decoded value by decoding and adding the separately transmitted code values of the two differential encoders.

(e) Embodiment of the Invention An embodiment of the invention will be described with reference to FIG. FIG. 2 is a block diagram showing only the differential quantizer circuit that is particularly relevant to the present invention (al represents the circuit configuration on the encoder side, (bl represents the circuit configuration on the decoder side). The same letters as in the figure indicate circuits with the same function.New letters L2L L22.L21' as in the second figure.

L22' is a logic circuit, 321. 322. S21',
322' is a selector circuit, zl is a delay circuit, M1 to M5
is a multiplier, and A3 to A7 are added adders.

Note that the encoder shown in FIG.
A circuit example is shown in which 3 bits are allocated to the second differential encoder (CODI) and 1 bit is allocated to the second differential encoder (COD2). Furthermore, C0D1 is a conventional differential PCM encoder (adaptive type) that performs 3-bit quantization with the same configuration as shown in FIG. type).

The sample value Xn of the input signal is first input to the first differential encoder C0D1.
In the conventional differential quantization, the quantization error was reduced to 3
Bittu no 2 progression issue 1. Output (n). At this time, C
Prediction error signal E generated at the input of quantizer Q with OD 1
The difference signal QEn between n and the decoded value En of the inverse quantizer Q is input to the second differential encoder C0D2, delta modulated, and separately output as a 1-bit code (n).

In C0D2, selectors S21 and S22 are controlled by logic circuit l521, and logic circuit L21
1'' when the output 1 t (n) of 1 exhibits the maximum amplitude
and generates a signal e which is O'' at other times. When the signal e is 1'', the selector 321 selects the signal S1,
When the signal e is "0", the value 0 is selected. Selector S22
selects signal S2 when signal e is °゛1'' and e is “o”
In this case, signal S3 is selected. The signal S3 is sent to the first encoder C
Equal to 0 to the quantization step value at 0DI. Quantizer Q2 encodes whether the polarity of the difference between the quantization error component QEn of GOD I and the output value of selector S21 (difference value in adder A4) is positive or negative, and outputs a 1-bit code 12 (r+). . Logic circuit L22 has an output n
) and the output 1 for the previous sample value Xn-/. (n-1
) are the same code word, a coefficient 84 is generated which has a value of 1 or more, and which has a value of 1 or less if they are different. Therefore, the signal S2 is the output of the selector 322 multiplied by a coefficient 84. The above is the configuration and operation of COD 2.

When the input signal Xn is stationary and C0D1 can follow Xn, the output 1z(n) becomes an intermediate code word, so the output e of the logic circuit L21 at C0D2 becomes an addition °', and Q2 simply becomes QEn 4-bit quantization is performed isometrically by encoding only positive or negative values. When the input signal Xn becomes unsteady and GODI cannot follow it, the output 1 t (n) continues to send out the maximum code word. In this case, the output e of the logic circuit L21 becomes 1. That is, the signal S2 has a coefficient of 8 with the initial value immediately before the signal e becomes 1.
4 is multiplied by multiplier M1 and becomes the combined value of second encoder C.
0D2 is an adaptive delta modulation circuit that follows the value of the quantization error QEn of the first encoder.

COD ] can follow the input signal and until the output l1(n) takes a value other than the maximum code word, C0D2 functions to correct the slope distortion generated in C0D1.

Next, on the decoder side, encoder circuits C0D1, C0D
2, decoder circuits DEC1 and DEC2 are constructed in correspondence with the conventional adaptive differential decoder. D
The inverse quantizer Q2 of EC2 decodes! Input −,'(n)
(D positive/negative response +0,5 (!: Generates a value of 0,5. Logic circuit L21 has selectors S'21 and S'2
2 and when the input I'f(n) is less than the maximum value, D
The step size Δn in ECl is multiplied by 0, 5 by multiplier M2, and then multiplied by the output of QU by multiplier M3, and the result is QEn, which is added to the output Xn of DECI by adder A6.
are added to obtain the final decoded value Xn. When decoder manual power -,'(n) reaches the maximum value, step size Δn of DECI immediately before taking the maximum value, similar to the encoder side.
is the initial value, the output of the logic circuit L'22 is multiplied by the multiplier M5, the output of the multiplier M4 is added to the summed value S5 by the adder A7 to obtain the value QEn, and the output Xn of DECl is multiplied by the adder A6.
are added at. At this time, actually input 1; (
n), the value obtained by multiplying S5 by a value of 1, 5 or 0.
The values multiplied by 5 are added in adder A6.

(f> Effects of the Invention As detailed in the embodiment, the quantization error in the non-stationary portion of the input signal is reduced, and the circuit configuration of the present invention, that is, the prediction circuit of the subsequent quantization encoder, provides feedback. Since it is not a system, it has the effect of not becoming unstable even if there is a transmission bit error.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an entire conventional differential PCM code decoder, and FIG. 2 is a block diagram of a differential quantizer circuit related to the present invention. In the figure, C0D1 and C0D2 are differential encoders, DBC
I and DEC2 are differential decoders, Q is a quantizer, Q-/ is an inverse quantizer, SA is a quantization step adaptation circuit, P is a predictor, L21 and L22 are logic circuits, and 521 and S22 are selectors. . 0

Claims (1)

[Claims] In a differential PCM code decoder that predicts the predicted value of the next sample value from the past sample value of the input signal, and quantizes and encodes only the difference between the predicted value and the actual sample value and transmits it, the encoder side It has two differential quantizer circuits, the first differential quantizer circuit differentially encodes and transmits the input signal, and the second differential quantizer circuit converts the quantization error value generated in the differential quantizer circuit. differentially encode and transmit,
A differential PCM code decoder characterized in that, on the decoder side, separately transmitted code values of first and second differential encoders are decoded and added to obtain a final decoded value.