JPH037425A - Programmable logic array - Google Patents

Abstract

PURPOSE:To extend a warranted time of the output signal independently of a synchronizing signal and to eliminate the variance of a delay time of an output signal by providing a dummy product term line and a sum term line selected latest. CONSTITUTION:When an L level signal PHI1 is inputted to an AND term 2, all product term lines P(k) are not selected and when an H level signal PHI1 is inputted to the AND term 2, the dummy product term line P(0) are selected latest independently of an input signal at each cycle. Moreover, when an L level signal PHI1 is inputted, all sum term lines S(m) (m=1...m) are not selected, and when H level signal PHI1 is inputted, the dummy product term line P(0) is selected latest for each cycle. Thus, the warranted period of the output of a programmable logic array is extended without provision of excess precharge control circuits, and the variance of a delay time of an output signal is eliminated.

Description

[Detailed Description of the Invention] Industrial Field of Application The present invention relates to programmable logic arrays built into semiconductor integrated circuits, in particular, to extend the guarantee period of output signals, and to eliminate variations in delay time of output signals. A related to programmable logic arrays that are conventional technology Conventional GEL is a programmable logic array built into a semiconductor integrated circuit that uses synchronization signals to control operations in order to increase operating speed Output signals The guaranteed period is until the end of the next cycle's precharging according to the synchronization signal.When using the output signal of the programmable logic array as an enable signal for a latch circuit, etc. in another block, the guaranteed period of the output signal can be synchronized. This is inconvenient if you want to postpone the output guarantee period regardless of the synchronization signal.It is necessary to provide an extra precharge control circuit to delay the end of the precharge. In addition, in the configuration of a programmable logic array that uses conventional synchronization signals to control operations, the output signal of the OR term depends on the input signal, which causes variations in delay time. Problems to be Solved by the Invention In the configuration of a programmable logic array that uses conventional synchronization signals to control operations, it is difficult to extend the guaranteed period of output signals; It is necessary to provide an extra precharge control circuit to delay the charge. Also, since the output signal of the OR term depends on the input signal, variations in delay time may occur.
The present invention has been made in view of the above-mentioned problems, and is a programmable logic array that is built into a semiconductor integrated circuit and whose operation is controlled using a synchronization signal. It is an object of the present invention to provide a programmable logic array that can extend the warranty period regardless of the synchronization signal and eliminate variations in the delay time of output signals. In order to solve the above problem, in addition to the product term line required to form the logic of the logical product term, a dummy product term line that is selected latest at each cycle regardless of the input signal, and the logical In addition to the sum term line required to form the logic of the sum term, there is a dummy sum term line that is selected latest, and the dummy sum term is selected after the dummy product term line is selected. This is a programmable logic array that uses lines as control signals for output circuits.

Effect of the Invention With the above-described configuration, the present invention can generate an enable signal for an output circuit by providing a dummy product term line and a dummy sum term line that are selected the latest. The output guarantee period can be extended without providing an extra precharge control circuit, and the variation in the delay time of the output signal can be eliminated. In FIG. 1, which is a block configuration diagram showing an example,
1 is the input buffer that drives the n-bit input signal line I (n), 2 is the logical product JX3 is the precharge circuit of the product term line, 4 is the logical sum term, 5 is the precharge circuit of the sum term line 6
is an output buffer including an output latch circuit, 20 is a dummy product term line P(0) that becomes selected latest regardless of the input signal in each cycle, and 30 is a dummy product term line P(0)
The precharge same section 40 is a dummy sum term line 5(0) which is not required to form the logic of the disjunction term 4 and becomes the latest selected state in each cycle, and 50 is a dummy sum term line 5.
(0) precharge circuit a In the input buffer 1, if the synchronizing signal Φ1 is at "L" level, the value of the n-bit input signal line I (n) is taken in. The signal IB has sufficient drive. (2n) and put Kugata's logic term 2 into the logical product term 2.
Sync signal Φ1 is #H# level Generated signal I
Although the value of B(2n) is guaranteed, in the logical product term 2, if the i word Φ1 is at "L" level, all the product term lines P(k) are in the non-selected state, and the synchronizing signal Φ1 is set to ``H''. In the case of level, the dummy product term line P(0) becomes the selected state the latest in each cycle regardless of the input signal, and the other product term lines P(k
)(k-1...k) are selected or unselected depending on the value of (2n) from the input signal. In the product term line precharge circuit 3.30, the synchronizing signal Φl is high
If L 11 level, all product term lines P (k) (k-
0...k) is performed, and the precharge operation ends when the synchronizing signal Φ1 becomes "H" level. 3 is the product term line P (k) (k-1...k). The precharge circuit converts the inverted signal of the product term line P(k) into FB(k
), 6. 30 is the dummy product term line P(0)
The inverted signal of the product term line P(0) is converted into PB by the precharge circuit
In the logical sum term 4, if the synchronizing signal Φl is at “L” level, all the sum term lines S (m) (
m-1...m) are in the non-selected state, and if the synchronizing signal Φ1 is at 'H' level, the dummy sum term line 5(0) becomes the selected state the latest in each cycle, and the other sum term lines S (n)
(m-1...m) is the input signal P B (k) (k-1
...In the sum term line precharge circuits 5 and 50, which are in a selected state or a non-selected state depending on the value of k>, all the sum term lines A precharge operation of S (m) (+n-0...m) is performed, and the precharge operation ends when the synchronizing signal Φl becomes "H" level. 5 is the sum term line S (m) (nr
l...m) outputs an inverted signal of the sum term line S (m) as SB (m). 50 is a precharge circuit for the dummy sum term line 5(0) which generates an enable signal Φ2 for the output latch circuit in the output buffer of the next stage. In this case, the enable signal Φ2 also goes to the "L" level, so the value of the output signal 0 (m) of the previous cycle is held. After the synchronizing signal Φ1 goes to the "H" level, the signal line S B (m
)(m=1...m) is the signal line S(m)(
Depending on the signal line S B (m) (m-1...II]), the enable signal Φ2 is the lowest depending on the signal line 5(0). It is possible to delay the guarantee period for the value of output signal 0(m) in the pre-cycle until all values are determined. Figure 2 is a circuit diagram showing a specific circuit configuration of the precharge circuit for the AND term and the product term line of the programmable logic array of the present invention. 20 is a circuit diagram constituting a dummy product term line, in which an n-channel MO8FET 21 has a gate connected to a synchronizing signal Φ1, a source grounded, and a drain connected to a group 22 of n-channel MO3FETs connected in series. The n-channel MO3FET group 22 (the other product term line P(k) (k-1---k) is connected in a number equal to or greater than the number of series stages of the n-channel MO5FET with the largest number of n-channel MO8FETs 22 By connecting all the gates of the circuit to the power supply voltage, the latest gate is selected in each cycle regardless of the input signal.
n-channel M of n-channel MOS FET group 22
Dummy product term line P on the side not connected to O3FET21
Even if it is connected to the dummy product term line precharge circuit 30 as the output of (0), the dummy product term line precharge circuit 30f;
The gate of T31 is connected to the synchronizing signal Φ1, the source is connected to the power supply voltage, the drain is connected to the dummy product term line P (0) and the input of the inverter 32, and the output of the inverter 32 is output as P B (0). Also synchronization signal Φ
1 is “L” level, the dummy product term line P(0) is “H”
The output signal PB (0) of the inverter 32 is “L”.
” level, it becomes a non-selected state. Synchronous signal Φ1 is HI
+ level, the dummy product term line P(0) is another product term line P
(k) becomes “L” level later than (k-1...k), so the output signal PB(0) of the inverter 32
is the selected state later than other output signals PB(k) (k-1...k). This is a circuit diagram showing the specific circuit configuration of the buffer.
In the circuit diagram configuring the n-channel MO3FET41
Even if the gate is connected to the signal P B (0) generated by the precharge circuit 30 of the product term line P (0), the source is grounded, and the drain is connected to the dummy sum term line 5 (0), the 50 p in the precharge circuit of the dummy sum term line 5(0)
The p-channel O8FE consists of an interchannel O8FET 51, an inverter 52, and a two-person circuit 53.
The gate of T51 and one input of the two-man circuit 53 are connected to the synchronizing signal Φ1 LA. The drain of the p-channel MO3FET 51 and the input of the inverter 52 are connected to the dummy summation line 5 (
0) and connect the output of inverter 52 to 5
By connecting to the remaining input of 3, the two-man circuit 53 generates the enable signal Φ2 of the output latch circuit in the output buffer. (m-0...m) becomes a non-selected state, the enable signal Φ2 also becomes u L n level, and the output signal of the previous cycle ○(m)(II+-1... Even if the value of m) is held, when the synchronizing signal Φ1 goes to "H" level, the sum term line S(+n) (m-1...m) becomes the selected state or non-selected state in the logical sum term, and then the dummy By selecting the sum term line 5(0), the enable signal Φ2 is activated in the dummy sum term line precharge circuit 50.
The output signal 0 (m) (m=1...
・It is possible to extend the guarantee period for the value of m), and (2) it is possible to output signals without variations in the delay time of the output signal. (4)
The figure shows a time chart during operation of the programmable logic array of the present invention.
(n) is the input signal Φ1 is the synchronization signal that determines each cycle IB (2n) is the output signal of the input buffer P (k) is the product term line P (0) is the dummy product term line PB (k) is the disjunction term PB(0) is the dummy product term line in the disjunction term S(m) is the sum term fil 5(0) is the dummy sum term line SB(m) is the sum term line that becomes the input of the output buffer Φ2 is an enable signal for the output latch circuit in the output buffer sofa. Input signal I (n) changes when the synchronizing signal ΦI is at L" level, and becomes the input signal I for the next cycle.
Even if B(2n) is applied to the logical product term, all the product term lines P (k) (ki...k) while the synchronization signal Φ1 is at "L" level.
is in a non-selected state and the “H” level is detected. Synchronous signal Φ1
When becomes "H" level, the dummy product term line P (0) becomes the slowest "L rubel" in each cycle regardless of the input signal, and the other product term lines P (k) (k-1--- k)
is selected according to the value of input signal IB (2n) and becomes “L”
Keep the “H” level without selecting the level, PB(
k) and PB(0) are obtained as inverted signals of P(k) and P(0), respectively, by an inverter. The synchronization signal Φ1 is “
If it is L” level, all the sum term lines S (m) (m-1・
... l11) is in the non-selected state and the "H# level is detected. If the synchronization signal Φ1 is the "H" level, the dummy sum term line 5 (
0) is selected the latest in each cycle and becomes the "L" level, and the other sum term lines S(m) (m-1...m) are selected according to the value of the input signal PB(k). SB(m) is obtained as an inverted signal of S(m) by the inverter and is taken into the output buffer at the timing of Φ2, but the synchronizing signal Φ1 remains "H". ” level, Φ2 becomes S every cycle.
When the synchronizing signal Φ1 becomes “H” level later than B(m) and takes the already determined value of SB(m) into the output buffer, 5B(I
Before the value of ll) reaches the "L" level - quickly °'L"
According to the present invention, the guarantee period of the output of the programmable logic array built into the semiconductor integrated circuit is extended by adding an extra precharge control circuit. It is possible to delay the delay time without having to provide a

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the programmable logic array according to the present invention. Figure 3 shows the logical sum style of the programmable logic array of the present invention.
Figure 4 is a time chart diagram illustrating the operation of the programmable logic array of the present invention. 1... Input buffer, 2 ...Conjunction term 3.
...Precharge same section of product term line 4...Order term 5...Precharge same section of sum term line 6...Output buffer, 20...Dummy product term line 30...
Precharge cycle of dummy product term line 40... Dummy sum term line 50... Precharge cycle of dummy sum term line Figure 1 Figure 2 Figure 3 and 4

Claims (1)

[Claims] An input buffer and a logic product term with the product term lines needed to form the logic plus a dummy product term line that is selected latest each cycle regardless of the input signal, and a product term line pre-processor. Includes a charge circuit, a disjunction term having a dummy sum term line selected latest in addition to the sum term line required to form the logic, a precharge circuit for the sum term line, and an output latch circuit. and an output buffer, wherein the dummy sum term line selected after the dummy product term line is selected is used as a control signal for the output latch circuit.