JPH0374004B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] The present invention relates to a temperature sensor for detecting a predetermined temperature, and particularly to a temperature sensor element made of a semiconductor.

In recent years, the development of various sensors has become active, and temperature sensors with various structures have also been developed.

An object of the present invention is to provide a temperature sensor element with a novel structure made of semiconductor.

[Structure of the invention]

According to the present invention, a semiconductor layer of a first conductivity type, first and second electrodes formed on the semiconductor layer at positions apart from each other, and a first and second electrode on the semiconductor layer.
an electrically floating semiconductor region of a second conductivity type opposite to the first conductivity type, formed at a position between the electrodes and separated from the first and second electrodes; When a predetermined voltage is applied between the first and second electrodes, if the ambient temperature is lower than the predetermined temperature, a depletion layer formed at the junction between the semiconductor layer and the semiconductor region is removed from the first and second electrodes. A conductive path between the first and second electrodes is blocked, and when the ambient temperature is equal to or higher than the predetermined temperature, the depletion layer unblocks the electrically conductive path and current flows between the first and second electrodes. A semiconductor temperature sensor element characterized by this is obtained.

Next, embodiments of the present invention will be described with reference to the drawings.

First, the principle of the present invention will be explained with reference to FIG.

The element shown in FIG. 2A is a semiconductor resistor in which first and second electrodes 11 and 12 are formed at both ends of an N-type Si substrate 10, for example. This semiconductor resistance element is
It has a structure in which an electric field is applied between the first and second electrodes 11 and 12 to flow a current, and the amount of current flowing is controlled by the specific resistance of the Si substrate 10.

As shown in FIG. 2B, first and second
Two Si regions 13 of a conductivity type opposite to that of the Si substrate 10 (i.e., P type) are located between the electrodes 11 and 12.
If they are formed so that a gap is formed between them, the current flowing between the first and second electrodes 11 and 12 is reduced. P-type Si region 13 is electrically floating. When the gap is narrowed, depletion layers generated at the PN junction formed by the two P-type regions 13 and the N-type substrate 10 overlap each other, and both electrodes 11
A state is formed in which no current flows until the voltage applied between the terminals and 12 reaches a predetermined voltage value. The predetermined voltage value is between the N type substrate 10 and the P type region 13
It is determined by the impurity density (specific resistance) of and the interval of the gap.

In the device of FIG. 2B, the present invention sets the impurity density of the N-type substrate 10 and the P-type region 13 and the interval of the above-mentioned gap to a certain state, and creates a gap between the first and second electrodes 11 and 12. As a result of investigating the relationship between the applied voltage and the ambient temperature of this element, they discovered and utilized the property that the voltage value at which no current flows decreases as the ambient temperature rises.

That is, in the semiconductor temperature sensor element according to the present invention, when a predetermined voltage is applied between the first and second electrodes 11 and 12, if the ambient temperature is lower than the predetermined temperature, the N-type Si substrate 10 and the two P The depletion layer formed at the PN junction with the type region 13 is the first and second depletion layer.
The conductive path between the electrodes 11 and 12 is interrupted,
When the ambient temperature is equal to or higher than the predetermined temperature, the conductive path is unblocked by the depletion layer and current flows between the first and second electrodes 11 and 12.

The semiconductor temperature sensor element according to the invention is structurally similar to a vertical field effect transistor (V-FET), but the semiconductor temperature sensor element according to the invention has a region 13 of the opposite conductivity type to the substrate 10 that is electrically It is a two-electrode resistor (passive element) that is floating in the air and has no amplification ability. In other words, it's not a transistor.

On the other hand, the V-FET is a three-electrode active element, and of course has an amplification ability, and the third electrode (gate electrode) is not floating, and a voltage is applied for control.

In addition, in the semiconductor temperature sensor element according to the present invention, if the first and second electrodes 11 and 12 are formed on both sides of the Si substrate 10, as shown in FIG. Becomes a resistor.
Also, as shown in FIG. 4, if the first and second electrodes 11 and 12 are formed on one side of the N-type Si layer 10,
The N-type Si layer 10 serves as a resistor through which current flows laterally (in the radial direction of the Si layer 10). In Figure 4, 14
is a P-type Si substrate.

Next, examples of the present invention will be described.

1 and 5 both show semiconductor temperature sensor elements according to embodiments of the present invention.
Figure 5 shows the P ⁺ layer 3 embedded, and the P ⁺ layer 3
and the P ⁺ pad layer 3' are connected externally. In Fig. 1, the P ⁺ layer 3 is formed at the bottom of the cut groove by diffusion, and as in the case of Fig. 5, the P ⁺ layer 3 is formed at the bottom of the cut groove.
and the P ⁺ pad layer 3' are connected externally. In addition, in FIG. 1 and FIG. 5, 1 is an N ⁺ Si substrate,
2 is the N ⁻ layer and 4 is the N ⁺ layer.

1 and 5, the N ⁺ Si substrate 1 corresponds to the first electrode 11 in FIG. 2B, the N ⁺ layer 4 corresponds to the second electrode 12 in FIG. 2B, and the P ⁺ Layer 3 and
P ⁺ pad layer 3' corresponds to P type region 13 in FIG. 2B.

1 and 5 show an example of a structure in which the conductive path W is formed in the thickness direction of the semiconductor substrate, that is, a vertical type, but according to FIG. 4, the conductive path W is formed in the radial direction of the substrate. A horizontal structure is also possible. The point is that the relationship between the width W of the conductive path and the impurity density of the N ^- layer 2 should be established under certain conditions.
Further, the number or area of the conductive paths does not need to be as large or large as in the case of a transistor, and may be designed as desired.

FIG. 6 shows an example of the present invention in which the impurity density N ^- of the N ^- layer 2 is set to 2× in the device having the structure shown in FIG.
Width W of conductive path when constant as 10 ¹³ cm ^-3
The device characteristics at room temperature (25°C) are shown when the temperature is changed appropriately. The voltage applied between the first electrode 1 and the second electrode 4 is plotted on the horizontal axis, and the current flowing through the conductive path between the first and second electrodes 1 and 4 is plotted on the vertical axis. It is. When the conductive path width W is 1.7 μm, no current flows until approximately 400V (electrical resistance is infinite), and current suddenly begins to flow above 400V. or,
When W = 3.0 μm, no current flows until the voltage reaches 100V (infinite electrical resistance), and when the voltage exceeds 100V, the current begins to flow suddenly. In other words, the blocking voltage of the device at room temperature is 400V for the former and 100V for the latter. As described above, by keeping the impurity density of the N ^- layer 2 constant and changing the conductive path width W appropriately, the value of the blocking voltage at room temperature can be arbitrarily selected.

Now, next in Figure 6, W = 1.7 μm (blocking voltage
Figure 7 shows the temperature change in blocking voltage of a device with a voltage of 400V. The data shows the blocking voltage measured while varying the device temperature in a device with W=1.7 μm and N ^- impurity density of 2×10 ¹³ cm ⁻³ . In this way, the blocking voltage changes to various values depending on the temperature. Focusing on the above behavior, by appropriately selecting the impurity density N ^- and the width W of the conductive path, the point at which the blocking state (infinite resistance) changes to the conducting state (blocking voltage) can be set arbitrarily depending on the temperature. The semiconductor temperature sensor element of the present invention can be obtained because the temperature sensor can be selected as follows.

It goes without saying that the element of the present invention is used by being attached to the tip of a metal frame, sealed with resin, with lead wires drawn out, and directly attached to the temperature measuring part.

The method for manufacturing the sensor element will be specifically described below.

In Figures 1 and 2, 1 indicates that the specific resistance ρ is
It is an N ⁺ type Si substrate with a resistance of 0.02Ωcm or less, and 2 is an N ⁺ type Si substrate.
High-resistance N ^- is grown on the substrate 1 in a vapor phase at a temperature of 1200°C using SiCl ₄ as a raw material and H ₂ as a carrier gas.
It is a layer. The specific resistance ρ is 200 to 250 Ωcm, and the thickness is about 30 μm. SiO ₂ is deposited on the entire surface of this N ^- or N ⁺ two-layer structure Si substrate 1 by normal thermal oxidation.
After forming the film, aperture windows are usually formed locally by a photorinography method using a type photoresistor. Thereafter, the SiO ₂ film is locally opened so that the P ⁺ layers 3 and 3' are selectively diffused.

In the case of the P ⁺ layer embedded type shown in Fig. 5, pre-deposition is performed at 950°C using BBr ₃ or Bcl ₃ as a raw material and N ₂ and O ₂ as carrier gas, followed by a pre-deposition at 110°C using the usual open tube liquid diffusion source diffusion method. Drive-in is performed to diffuse the P ⁺ layers 3 and 3'.
The surface impurity concentration Ns of P ⁺ layers 3 and 3' is 1×10 ¹⁹ cm ^-3
The above shall apply. Next, vapor phase growth is performed using Sicl ₄ as a raw material and H ₂ as a carrier gas to form P ⁺ layers 3 and 3' with N ^-
Embed in the layer. During this second vapor phase growth, the temperature is approximately 100° C., lower than that during the first growth. This is to prevent boron atoms from jumping out from the P ⁺ layers 3, 3' and to accurately form the conductive path width W between the P ⁺ layers 3, 3' after embedding. The specific resistance ρ of the second growth layer is 5 to 50 Ωcm, and around 10 μm is an easy value from the viewpoint of forming the above-mentioned conductive path width W.
After embedding the P ⁺ layers 3 and 3' between the N ^- layers, an N ⁺ layer 4 is formed on the entire surface by diffusion using a conventional open-tube liquid diffusion source. The N ⁺ layer 4 is formed using POCl ₃ as a raw material and N ₂ and O ₂ as carrier gases. Surface impurity concentration
Ns is preferably 1×10 ²⁰ cm ^-3 or more.

The main electrodes are N ⁺ layers 1 and 4, with Al on the surface
The element is completed by forming electrode metals such as by vapor deposition or other means.

On the other hand, in the case of the notch type shown in Figure 1, the above-mentioned
After opening the selective diffusion windows of P ⁺ layers 3 and 3', use a conventional silicon etching solution (for example, HF:HNO ₃ :=
1:2), perform selective etching of about 4 to 7μ,
Subsequently, boron is diffused into the bottom of the kerf by ion implantation to form P ⁺ layers 3 and 3'. The N ⁺ layer 4 is formed by the usual photolithography method and the same diffusion method as described above, and the electrode metal is formed in the same way.

The device obtained as described above can be used in a normal semiconductor case, such as a TO-3 type metal case.
It is assembled into a TO-220 type molded case to create a completed product.

Next, the method of using the semiconductor temperature sensor element according to the present invention will be explained with reference to FIG. That is, in FIG. 8, a semiconductor temperature sensor element 10 according to the present invention is shown.
0 in place of a thermal reed switch, etc., and connect the cooling fan 200 and power supply (for example,
It is used as a sensor for detecting the temperature inside the thermostatic chamber (chamber) 300 by inserting and connecting it in series to the connection line between the thermostat (AC100V) and the thermostat (room) 300. When the temperature inside the constant temperature bath 300 rises and reaches a predetermined temperature, a current flows through the semiconductor temperature sensor element 100 (that is, the semiconductor temperature sensor element 100 turns on), and the cooling fan 20
0 rotates to lower the temperature inside the constant temperature bath 300. When the temperature inside the constant temperature bath 300 falls, the semiconductor temperature sensor element 100 is also turned off again, and the cooling fan 200 stops rotating.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to obtain a temperature sensor element with a novel structure made of a semiconductor.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a semiconductor temperature sensor element according to an embodiment of the invention, FIGS. 2 to 4 are sectional views of the element for explaining the principle of the invention, and FIG. 5 is another embodiment of the invention. A cross-sectional view of a semiconductor temperature sensor element according to an example, FIG. 6 is a diagram showing the element characteristics at room temperature of the embodiment of FIG. 1, and FIG. 7 is a diagram showing the temperature dependence characteristics of the blocking voltage of the embodiment of FIG. 1. 8 are diagrams showing an example of use of the semiconductor temperature sensor element according to the present invention. 1 and 11...first electrode, 4 and 12...second electrode, 2 and 10...N-type Si layer, 3, 3' and 13...P-type Si region.

Claims (1)

[Claims] 1 a first conductivity type semiconductor layer, first and second electrodes formed in the semiconductor layer at positions separated from each other;
electrically of a second conductivity type opposite to the first conductivity type, formed in the semiconductor layer at a position between the first and second electrodes and separated from the first and second electrodes; a floating semiconductor region;
When a predetermined voltage is applied between the first and second electrodes, if the ambient temperature is lower than the predetermined temperature, the depletion layer formed at the junction between the semiconductor layer and the semiconductor region is A conductive path between the electrodes is blocked, and when the ambient temperature is equal to or higher than the predetermined temperature, the conductive path is unblocked by the depletion layer and a current flows between the first and second electrodes. Characteristic semiconductor temperature sensor element.