JPH0373499A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To suppress the fault rate of redundancy word line or a redundancy data line after saving a defect by executing switching to the redundancy word line or the redundancy data line only by a memory array or a memory mat including a defective word line or a defective data line. CONSTITUTION:The memory array SM or the memory mat MAT including the defective word line or defective data line is discriminated and the switching to the redundancy word line Wr0 or a redundancy data line is selectively execut ed only by the discriminated memory array SM or memory mat MAT. Conse quently, the fault rate of the redundancy word line Wr0 or redandancy data line after saving the defect can be suppressed and the number of required redun dancy word lines or redundancy data lines to be connected can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of application for m business owners) This invention relates to a semiconductor memory device, for example,
The present invention relates to a technique that is particularly effective for use in repairing defects in dynamic RAMs having a plurality of memory arrays or memory mantles.

[Conventional technology]

There are dynamic RAMs that have multiple memory arrays or memory mantles. In addition, as a means of increasing the product yield of such dynamic RAMs, etc., there is a defect relief method in which a predetermined number of redundant word lines and redundant data lines are provided in the memory array and assigned to the word line or data line in which a defect has been detected. There is.

A defect relief method for dynamic RAM and the like is described in, for example, Japanese Patent Application No. 61-223579.

[V1 Problem to be Solved by the Invention] FIG. 3 shows an example of a block diagram of a dynamic RAM having a plurality of memory mats. In the figure, the dynamic RAM includes 4(il(7)+lmomo9fufu MAT0-MAT3), and each memory mat has two pairs of sub-memory arrays 5M0O to 5MO3 to 5M30 to 5M33 in a shared sense configuration. Each sub-memory array has a plurality of word lines including a predetermined number of redundant word lines, and these word lines are
It is coupled to corresponding row address decoders RDOO-RDO3 to RD30-RD33.

In this Guinami 7 type RAM, from each memory cloak,
Upper 2 bits of internal address fi number axl-1 and mx
A total of four sub-memory arrays, each designated by Hll, are simultaneously selected, and in these sub-memory arrays, internal address signals axQ to axj-
One word line designated by 2 or a redundant word line corresponding to the word line is selectively selected.

The dynamic RAM selectively selects a designated word line or redundant word line by selectively transmitting a word line drive signal φX whose absolute value is a predetermined boost level greater than the circuit's li source voltage. A so-called word line driving method is adopted. Therefore, the dynamic RAM includes a word line drive signal generation circuit XG that forms the word line drive signal φX, and a word line drive signal φX that forms the word line drive signal φX.
For example, the lower two bits of internal address signals axQ and a
A word line selection drive circuit XJ selectively forms word line selection drive signals -xO to -x3 based on xL, and a redundant word line selection drive circuit XRJ forms a redundant word line selection drive signal φX. Be equipped.

In the Dyna main 7 type RAM that adopts the conventional defect relief method as described above, the redundant address memory RM holds the defective address assigned to each redundant word line.
and a redundant address comparison circuit R that compares and verifies the address supplied during memory access with the defective address.
C is provided commonly to all memory cloaks. Then, the word line selection drive circuit XJ and the redundant word line selection drive circuit XRJ are selectively activated in accordance with the redundancy enable signal xra output from the redundancy address comparison circuit RC. Row address decoder RDOO~R
DO3 to RD30 to RD33 are selectively put into operation state in groups of four in accordance with submemory array selection signals ssQ to 333 outputted from submemory array waste circuit SSL. In this operating state, each row address decoder receives the word line selection drive signal φXO~
By combining φx3 and the predecode signal supplied from the Brillo address decoder PRD, the designated word line is alternatively selected, and the redundant word line selection g! By combining the lj signal φXr and the redundant word line selection signal rwQ supplied from the redundant address comparison circuit RC, the corresponding redundant word line is alternatively selected. As a result, the word line in which the defect has been detected is automatically switched to the corresponding redundant word line, and the predetermined defect #i1? lf is realized.

However, the inventors of the present invention have discovered that the dynamic RAM described above has the following problems. That is, in the dynamic RAM described above, the redundant address memory RM, the redundant address comparison circuit RC, the word line drive signal generation circuit XG, the word line selection drive circuit XJ, and the redundant word line selection drive circuit XRJ.
is provided in common to all memory mats. Therefore, for example, as shown in FIG. 3, if a jl error is detected in the word line Wk of sub-memory array 5Ml0 and this is relieved by redundant word 1jWrO, then in the corresponding sub-memory arrays 5M0Q, 5M20 and 5M30 of 3fii, Also, the normal word line Wk is switched to the corresponding redundant word line WrO, and as a result,
On the other hand, the probability that a fault will occur in the four redundant word lines WrO that have been switched increases, and the number of redundant word lines must be increased accordingly. Sub memory array 5Ml
0 or the memory mantle MATl including this is considered, but the word line drive signal generation circuit XG, the word line selection drive circuit Xj, and the redundant word line selection drive circuit X
Since the RJ is provided in common to all memory mantles, it is not possible to identify in which submemory array, for example, a short-circuit failure of adjacent word lines, which has a relatively high occurrence rate, is occurring.

An object of the present invention is to provide an effective defect relief method for a dynamic RAM having a plurality of memory arrays. Another object of the present invention is to suppress the failure rate after defect repair in a dynamic RAM having a plurality of memory arrays, and to correspondingly reduce the required number of redundant word lines and redundant data lines. .

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in a dynamic RAM or the like that includes a plurality of memory arrays each including a predetermined number of redundant word lines or redundant data lines, switching to a redundant word line or redundant data line is performed by a memory array including a defective word line or a defective data line, or a memory array including a defective word line or defective data line. This is carried out only in the memory mat that includes this memory array. Then, selection drive circuits corresponding to at least the number of simultaneously selected word lines or data lines are provided corresponding to each memory array or memory mantle.

(Function) According to the above-described means, a memory array or memory mat including a defective word line or defective data line is identified,
Switching to redundant word lines or redundant data lines can be selectively performed only in identified memory arrays or memory mats.

Thereby, it is possible to suppress the failure occurrence rate of redundant word lines or redundant data lines after defect relief, and to correspondingly reduce the required number of redundant word lines or redundant data lines to be installed.

(Example) FIG. 1 shows a dynamic type RA to which this invention is applied.
A block diagram of one implementation of M is shown. The surrounding elements for each block in the figure are not particularly limited by known semiconductor integrated circuit manufacturing techniques, but are made of H! i is formed on a semiconductor substrate.

Although the following explanation will focus on redundant word lines, basically the same method can be applied to redundant data lines as well.

In FIG. 1, the dynamic RAM of this embodiment has four memory mats MATO to
MAT3, each memory mat has two pairs of sub-memory arrays SMO0 to 5MO3 in a shared sense configuration.
to 5M30 to 5M33. These memory mats are specially designed for il! Although not limited to, each sub-memory array is arranged symmetrically across a common column address decoder CD, and each pair of sub-memory arrays is connected to a corresponding sense amplifier S^O.
O or SMO1 to 5M30 or 5M31 are arranged symmetrically.

Sub memory array 5M0O~5MO3~5M30~
5M33 includes, but is not particularly limited to, a plurality of word lines and redundant word lines arranged in parallel in the vertical direction of the diagram, and a plurality of data lines and redundant data lines arranged in parallel in the horizontal direction, respectively. A plurality of dynamic memory cells are arranged in a grid at the intersections of these word lines and data lines. In this embodiment, the word line and data line addresses of each sub-memory array are associated with each other, and the same row address and column address are assigned.

The word lines and redundant word lines serving each sub-memory array are connected to the corresponding row address decoders RD00 to RD.
It is coupled to O3 to RD30 to RD33, and each is alternatively set to a selected state. Although not particularly limited, these row address decoders are commonly supplied with a predecoded signal from the BRIDGE address decoder PRD, and are also supplied with corresponding sub-memory array selection signals ssO to ss3 from the sub-memory array selection circuit SSL. Supplied in predetermined combinations. In addition, word line selection drive signals φxQ to φ are applied to the four submemory arrays 5M0O to 5M03 to 3M30 to 3M33 corresponding to each memory mat from the corresponding word line selection drive circuits XJO to XJ3.
x3 is also the corresponding redundant word line selection drive circuit XRJ
The redundant word line selection drive signal φxr is output from O-XRJ3.
Further, a redundant word line selection signal rwQ and the like are commonly supplied from the corresponding redundant address comparison circuits RCO-RC3.

Here, the sub memory array selection signals ssQ to ss3
is selectively formed according to the internal address signals axL1 and axl of the upper 2 bits, although not particularly limited, and the predecode signal further converts the lower 2 pins to the internal address signals ax2 to axL2 of M<1-3 pins. It is selectively formed by decoding each bit in a predetermined combination. In addition, the word line selection drive signal φXO~-
13 is formed alternatively according to the internal address signals axQ and axl of the lower two pins on the condition that the address supplied during memory access and the defective address assigned to each redundant word line do not match. . Furthermore, the redundant word line selection drive signal φxr is selectively formed when the address supplied during memory access matches the defective address assigned to any redundant word line, and at this time, the redundant word line selection drive signal φxr Selected fs numbers rwQ, etc. are alternatively formed. The high level of the word uA selection drive signals φxQ to φx3 and the redundant word line selection drive signal φXr is a predetermined boost level whose absolute value exceeds the power supply voltage of the circuit.

Row address decoder RDOO~RDO3 or RD3
0 to RD33 are selectively put into an operating state in groups of four by the corresponding sub-memory array selection signals ssQ to ss3 being alternatively set to high level. In this operating state, each row address decoder combines the word line selection drive signals φxO to -x3 and the predecode signal, or by combining the redundant word line selection drive signal φxr and the redundant word line selection signal rvQ, etc. A corresponding word line or redundant word line of a corresponding sub-memory array is alternatively brought into a selected state. As a result, the corresponding four sub-memory arrays 5M00-3M30 to 5MO3-5 of each memory mat
At M33, four word lines or redundant word lines are simultaneously brought into a selected state. As a result, this dynamic RAM
The number of word lines remaining at the same time is four.

Although not particularly limited, the sub-memory array selection circuit SSL selects the upper two
Decodes the focused internal address signals axj-1 and axi to generate the corresponding sub-memory array selection signal ssQ~
ss3 is alternatively formed. In this embodiment, internal address signals axO to axl are not particularly limited, but
These are complementary signals consisting of non-inverted and inverted signals, respectively.

In addition, the non-inverted and inverted signals of each internal address signal are set to a low level when the dynamic RAM is in a non-selected state, and are set to a high level in a compensatory manner at a predetermined timing when the dynamic RAM is in a selected state. It is said that Therefore, the submemory array selection signal ssO~
333 is alternatively formed at a predetermined timing when the dynamic RAM is brought into a selected state, and can serve as an activation signal for the corresponding row address decoder.

Although not particularly limited, the low address decoder PRD is supplied with 1-3 from the row address buffer RAB.
The focus internal address signals ax2 to axi-2 are decoded several bits at a time in a predetermined combination to selectively form the predecoded signal. Similar to the sub-memory array selection signal ssQwss3, these predecode signals are all invalidated when the dynamic RAM is in the non-selected state, and are alternatively enabled at predetermined timings when the dynamic RAM is in the selected state. be done.

Word line selection drive circuits XJO-X and J3 include, but are not limited to, corresponding word line drive signal generation circuits XGO.
The word line drive (No. 8 - wing) is supplied from -XG3, and the inverted signal of the redundancy enable signal xre by the inverter circuit Nl is supplied from the corresponding redundant address comparison circuits RCO to RC3. 2-bit internal address signals axQ and axl are commonly supplied. On the other hand, the redundant word I*ii! selection drive circuits XRJO to XRJ3 receive the word line drive signal from the corresponding word line drive signal generation circuits XGO to XG3. φ
X is supplied, and the corresponding redundant address comparison circuit RCO~
The redundancy enable Cδ number Xra is supplied from RC3.

When the output signal of the corresponding inverter circuit Nl, that is, the inverted No. 13 of the redundancy enable signal XI'6, is set to high level, the word line selection drive circuits XJO-XJ3
In other words, the corresponding redundant address comparison circuit RCO~
In RC3, when the address supplied during memory access and the defective address assigned to each redundant word line do not match, the redundant word line is selectively activated. In this operating state, the word E' line selection drive circuit XJ
O to XJ3 decode the internal address signals m)cQ and axl and combine with the word line drive signal φX to selectively form the word line selection drive signals Ca signals φx0 to φx3. In other words, the word line selection FIA operating circuit XJ
O-XJ3 is the boost level word line drive signal φX
are selectively relayed as word line selection drive signals φxO to φx3.

Redundant word line selection drive circuits XRJO-XRJ3, when the corresponding redundancy enable signal xrs is set to high level, ε, in other words, one of the addresses supplied at the time of memory access in the corresponding redundant address comparison circuits RCO to RC3. When a defective address assigned to a redundant word line matches, it is selectively activated.

In this operating state, redundant word line selection drive circuit XR
JO to XRJ3 are boost level word line drive fS
The signal φX is relayed as the redundant word line selection drive signal φX''.

The word line drive signal generation circuits XGO to XG3 are commonly supplied with the tie writing signal φW from the tie writing signal generating circuit TO. Here, the tying signal φW is normally set to a low level, although it is not particularly
When M is selected, the internal address signal ax
It is set to high level at the timing when the logic levels of O to axI and the predecode signal are established.

The word line drive signal generation circuit XGO-XG3 has a predetermined boost capacity, although not particularly limited, and forms the word line wA movement signal φI at a boost level in accordance with the tying signal φW.

Although not particularly limited, the redundant address comparison circuit RCO-RC3 includes a plurality of address comparison circuits provided corresponding to each redundant word line of a 4-fil sub-memory array forming the corresponding memory mantle. A row address buffer R is connected to one input terminal of these address comparison circuits.
Internal address signals axO to axt-z of 1-1 bits excluding the upper 2 bits are commonly supplied from AB, and one of the input terminals receives the corresponding address signals from the corresponding redundant address memories RMO to RM3. !-1 bit defective address rxO-rxi assigned to redundant word line
-2 is supplied.

Each address comparison circuit of the redundant address comparison circuits RCO to RC3 compares the address supplied due to memory access, that is, the internal address signal axQ to axj-2, and the corresponding defective address rxQ to rxi-2.
Compare and match each. As a result, when all bits of both addresses match in either address comparison circuit, the corresponding redundancy word line selection signal rwQ etc. are set to high level, and the corresponding redundancy enable signal xre is set to high level. When the two addresses do not match in all the address comparison circuits of each redundant word line selection drive circuit, the corresponding redundancy enable signal xra remains at a low level.

The redundant address memory RMO-RM3 includes, but is not particularly limited to, a plurality of read-only memories provided corresponding to each redundant word line of the corresponding memory mantle and using a hissing means as a storage means. In a predetermined test process, the row address of the defective word line assigned to the corresponding redundant word line, that is, the defective address, is written into these read-only memories. The storage contents of these read-only memories are the above-mentioned defective addresses rxO~r.
It is always read out as Xi~2 and supplied to the corresponding address comparison circuits of the corresponding redundant address comparison circuits RCO~RC3.

By the way, in the dynamic ivy-type RAM of this embodiment, four sub-memory arrays 5M0O to 5MO3 to 5M30 to 5M30 to 5M0O to 5MO3 constituting the memory map γI-MATO-MAT3 are used.
As mentioned above, the row addresses assigned to each word line of 5M33 are associated with each other, and internal address signals axQ and ax of i-1 bits excluding the upper 2 bits and
i-2, a total of four word lines, one from each memory mant, are selectively selected. Each sub-memory array includes a predetermined number of redundant word lines, and these redundant word lines are assigned only when a defective word line is detected in a sub-memory array within the corresponding memory muff L. At this time, the row address of this defective word line is written into the corresponding read-only memory of the corresponding redundant address memories RMO to RM3 as a so-called defective address. When the address supplied at the time of memory access matches this defective address, the corresponding redundant word line is placed in a selected state.

That is, for example, as shown in FIG. 1, word 1JIW of sub-memory array 5Ml0 of memory mantle MATI
If a defect is detected in word line Wk, this word line Wk is automatically switched to, for example, a redundant word line W r Q.

However, other memory mats MATO and MA
At T2 and MAT3, the corresponding word line Wk is kept in the selected state without being switched to the redundant word line W r Q. As a result, the probability that a fault will occur in the switched redundant word line after defect relief is reduced to one-fourth of that in the case of Figure 3, and the number of redundant word lines required to be installed is correspondingly reduced. The product yield of dynamic RAM can be increased.

The row address buffer 7FA RAB is connected to the address input terminal AO.
X address signal A supplied in a time-division manner via ~^l
XO to AXi are captured and held according to the timing occurrence. Furthermore, the internal address signal axQ-axi is formed based on these X address signals. this house,
Internal address signals axi-1 and axi of the upper two pins
are supplied to the sub-memory array loss circuit SQL, and the lower two bits of internal address signals axQ and axl are commonly supplied to the word aIA selection drive circuits XJO to XJ3. Furthermore, the internal address signal axOxaxL2 with M<1-1 bits for the upper two pins is connected to the redundant address comparison circuit R.
Commonly supplied to CO to RC3, and further excluding the lower two pins (internal address signals ax2 to axi- of pins 1 to 3)
2 is (co-supplied) to the Brillou address decoder PRD.

Next, the data lines constituting each sub-memory array are coupled to the corresponding unit amplification circuits via the corresponding shared sense MO3FETs of the corresponding sense amplifiers 5AOO or 5AOI to 5A30 or 5A31, although not specifically mentioned. Corresponding column switch MO3FET
are selectively connected to corresponding common data lines CD0O or CDOl to CD30 or CD31 via. A corresponding data line selection signal is supplied from a column address decoder CD to the gates of these column switches MO5FET.

Each unit 111-width circuit of sense amplifiers SAOO and SAO1 to 5A30 and 5A31 is selectively brought into operation according to a timing signal φpa, not shown. In this operating state, each unit amplification circuit of the sense amplifier receives minute read signals output via the corresponding data line from the plurality of memory cells coupled to the selected word line of the left or right sub-memory array. It is amplified and made into a high level or low level readout signal. These binary read signals are further transmitted to the corresponding common data line CD.
It is transmitted to the corresponding main amplifiers MAO to M^3 via 0O or CD0I or CD30 or C031.

Column address decoder CD is supplied with 51-pin internal address signals ayO to ayl from column address buffer CAB, although not particularly limited thereto, and is supplied with timing (rs number φy) from timing generation circuit TG.

The column address decoder CD receives the timing signal φ.
By setting y to a high level, the device is selectively put into an operating state. In this operating state, column address decoder CD decodes internal address signals ayO-ayl and selectively sets the corresponding data line selection signal to a high level. These data line selection signals are not limited to 1i1, but are sent to all sense amplifiers 5AOO and 5AOI to 5A30 and 5A via corresponding selection signal lines.
31 corresponding column switch MO8FETs in common.

Although not particularly limited, the column address buffer CAB converts the Y address signal AYO-AYl supplied in a time-division manner via the address input terminal AO-At to the tying signal supplied from the tying generation circuit TO. -take in and hold according to ac. Also, form a corner address signal ayOxayl based on these Y address signals and supply it to the column address decoder CD.

The main amplifier MAO-MA3 includes a read amplifier and a write amplifier, respectively. Of these, each read amplifier is selectively brought into operation according to a tying signal -ma (not shown) supplied from a timing generation circuit TG when the dynamic RAM is placed in a read mode. In this operating state, the lead amplifier of each main amplifier is connected to the corresponding memory cloak M ATO-M.
Corresponding common data 1icDOO or CD0I to CD30 or C from the selected memory cell of A T3
The read signal outputted via D31 is further amplified and transmitted to the corresponding data output buffer of the data input/output circuit I10.

- On the other hand, the write amplifier of the main amplifier MA O-MA 3 is selectively brought into operation according to a timing signal φw6 (not shown) supplied from the timing generation circuit TG when the dynamic RAM is in the write mode. In this operating state, the write amplifier of each main amplifier uses the write data transmitted from the corresponding data manual buffer of the data input/output circuit 110 as complementary write fδ, and connects the corresponding common data line CD0O or CD0I to CD30 or CD31. The data is written to the selected memory cell of the corresponding memory man 1-MATO to MAT3 through the memory cell.

Data input/output circuit I10 is 1, data input/output terminal DO~
Four data output buffers and four data manual buffers are provided corresponding to D3. Of these, the data output cover 7 is selectively activated in accordance with a timing signal φOe (not shown) supplied from the tying generation circuit TG when the dynamic RAM is in the read mode, although this is not particularly limited. Ru. In this operating state, each data output buffer sends out the read signal output from the corresponding main amplifier MAO-MA3 via the corresponding data input/output terminal DO-D3.

On the other hand, the data manual buffer of the data input/output circuit I10 is not particularly subjected to wlvR, but when the Guinamink type RAM is set to the blue write mode, it is selectively brought into an operating state according to the timing signal φ1a (not shown) supplied from the timing generation circuit TG. It is said that In this operating state, each data input cover sofa transmits write data supplied via the corresponding data input/output terminals DO to D3 to the corresponding main amplifiers MAO to M^3.

Although not particularly limited, the timing generation circuit TG receives a row address strobe signal hi RAS and a column address strobe signal CA supplied as control signals from the outside.
Based on S and write enable signal WE, the various tying signals mentioned above are generated and supplied to each circuit.

As described above, the dynamic RAM of this embodiment is
It is equipped with 4 (il memory muffs) MAT0 to MAT3 each including two pairs of sub-memory arrays 5M00-3MO3 to 5M30-5M33 each having a shared sense configuration, and a word u provided corresponding to these memory mants.
A drive signal generation circuits XGO to XG3. War F&11I
Selection drive circuit xJO to XJ3 and redundant word line selection drive v
J circuits X R, J Q to XRJ3, redundant address comparison circuits RCO to RC3, and redundant address memories RMO to R
M, 3. Each sub-memory array includes a plurality of word lines and redundant word lines to which addresses are respectively associated, and a total of four word lines, one each assigned the same row address from each memory mat, are selectively And at the same time, it is set to the selected state. In this embodiment, switching for each redundant word line is performed only in the memory mat containing the defective word line, and word lines to which corresponding row addresses of other memory mats are assigned are selected without being switched to the redundant word line. State ε is reached. As a result, it is possible to easily identify, for example, a short && fault in an adjacent word line, which has a relatively high probability of occurrence, and it is also possible to suppress the probability of a fault occurring in a redundant word line after defect relief. As a result, the location of the redundant word line g! The number of installations is ll! This can reduce ITJ or increase the product yield of dynamic RAM.

As shown in the above-described embodiment, the following effects can be obtained by applying the present invention to a semiconductor memory device such as a dynamo-type RAM having a plurality of memory arrays. That is, (1) a dynamic RA comprising a plurality of memory arrays each including a predetermined number of redundant word lines or redundant data lines;
In M, etc., switching to redundant word lines or redundant data lines is performed only in the memory array that includes the defective word line or defective data line, or in the memory array that includes this memory array, and the switching for each memory array or memory mat is performed. By providing selection drive circuits corresponding to at least the number of simultaneously selected word lines or data lines,
This provides the advantage that a memory array or memory mat containing a defective word line or data line can be easily identified.

(2) Clause 2 (Xi) performs multiple switching of redundant word lines or redundant data lines only in the memory array or memory mantle in which the existence of a defective word line has been identified, and This has the effect of suppressing the failure rate of lines or redundant data lines.

(3) According to the above (11) and (21), the required number of redundant word lines or redundant data lines to be installed can be reduced accordingly, or the yield of products such as dynamic RAMs can be increased.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, the redundant address comparison circuit and the redundant address memory are provided corresponding to the memory mant in the embodiment shown in FIG. 1, but as illustrated in FIG. In this case, for example, the redundant address memory RM
2-bit redundant loss signals rxo and rxl for specifying a memory mat containing a defective word line;
This is decoded by the redundant cloak selection circuit R3L,
Redundancy selection signals rso to rs3 are alternatively set to high level. This allows memory pins containing defective word lines]
The word line selection drive circuits XJO to XJ3 and the redundant word line selection drive circuits XRJO to XRJ3 corresponding to . Dynamic type R
The AM may include a predetermined number of redundant data lines in each memory array, and for these redundant data lines,
A basically similar redundant switching method can also be adopted.

The dynamic RAM may not employ the column at-sensing method, or may include a plurality of column address decoders provided corresponding to each memory mantle. Furthermore, various embodiments may be adopted, such as the plotter configuration of the dynamic RAM shown in FIGS. 1 and 2, and combinations of control signals and address signals.

The above explanation will mainly focus on the invention made by the present inventor, which is the field of application which is the background of the invention.
M1. : Although we have explained the case where it is applicable, it is not limited to that, for example, multi-port R whose basic configuration is static type RAM or dynamic type RAM.
The present invention is applicable to various semiconductor memory devices such as AM and the like.The present invention is applicable to a semiconductor memory device including a plurality of memory arrays each including at least a redundant word line or a redundant data line, and a digital integrated circuit device including such a semiconductor memory device. Can be widely used.

(Effects of the Invention) The effects obtained by typical inventions disclosed in this application are briefly described below. That is, the dyna[7] includes a plurality of memory arrays each including a predetermined number of redundant word lines or redundant data lines.
In a redundant RAM, etc., switching to a redundant word line or redundant data line is performed only in the memory array containing the defective word line or defective data line or the memory cloak containing this memory array, and the switching for each memory array or memory mat is performed. By providing selection drive circuits corresponding to at least the number of simultaneously selected word lines or data lines, a memory array or memory mat containing a defective word line or defective data line can be easily identified, and a redundant word line or redundant word line or redundant word line or memory mat can be easily identified. Switching to the data lines can only be performed in this memory array or memory mantle. As a result, it is possible to suppress the failure rate of redundant word lines or redundant data lines after defect repair, so the number of required redundant word lines or redundant data lines to be installed can be reduced by #1, or the number of redundant word lines or data lines required to be installed can be reduced by #1, or Product yield can be increased.

[Brief explanation of drawings]

! @Figure 1 is a dynamic RA to which this invention is applied.
Kazumi J of M! j! A block diagram showing an example, FIG. 2 is a block diagram showing another embodiment of a Dynat7 type RAM to which the present invention is applied, and FIG. VS3 is a block diagram showing an example of a conventional dynamic type RAM. . MATO~MAT3...Memory cloak, 5M00-3
M33...Sub memory array, 5AOO~SA31・
...Sense amplifier, RDOO-RD33...Row address decoder, CD...Column address decoder, R
AB...Row address buffer, CAB...Column address buffer, SSL...Sub memory array selection circuit, PRD...Brillou address y-coder, J
'? M. RMO-1? M3...Redundant address memory, RC. RCO-RC3...Redundant address comparison circuit, XG, X
GO~XG3...word line drive signal generation circuit, XJ,
XJO-XJ3...word line selection drive circuit, XRJ,
XRJO~XRJ3---Redundant word line selection drive circuit,
MAO~MA3...Main amplifier, Ilo...Data input/output circuit, TO...Timing generation circuit, R3L
...Redundant mat selection circuit. Wk...word line, WvO...redundant word line,
N1-N2...Inverter circuit, Gl...AND gate circuit.

Claims (1)

[Scope of Claims] 1. A plurality of memory arrays each including a redundant word line and/or a redundant data line and whose addresses are associated with each other, wherein switching to the redundant word line or redundant data line is caused by a defect. A semiconductor memory device characterized in that it is implemented only in a memory array that includes a word line or a defective data line, or a memory mat that includes this memory array. 2. The semiconductor memory device adopts a word line drive method in which a designated word line or redundant word line is selectively brought into a selected state by selectively transmitting a word line drive signal having a predetermined boost level. a word line drive signal generation circuit that forms the word line drive signal; a word line selection drive circuit and redundant word line selection drive that relays the word line drive signal to a designated word line or redundant word line; A circuit, a redundant address memory that holds a defective address assigned to a redundant word line, and a redundant address memory that holds the defective address assigned to the redundant word line, compares and matches the address supplied at the time of memory access with the defective address, and activates the word line selection drive circuit or the redundant word line selection drive circuit. 2. The semiconductor memory device according to claim 1, wherein the redundant address comparison circuits that are selectively brought into operation are provided corresponding to memory arrays or memory mats, respectively. 3. The redundant address memory and the redundant address comparison circuit are provided in common to all memory arrays or memory mats, and in this case, the redundant address memory is further configured to determine whether the held defective address is in any memory. 3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device retains a predetermined number of bits of redundant selection signals indicating whether the device corresponds to an array or a memory mat.