JPH0373192B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an imaging device capable of accurate and quick AE lock.

(Prior Art) Conventionally, it is known that an imaging device such as a video camera is provided with an optical viewfinder in order to obtain a clean viewfinder image.

However, in order to enable lens exchange in such an imaging device, the finder optical system must be placed behind the aperture.

This is because it is difficult to accurately control the aperture unless the aperture is located in the middle of the imaging optical system.Moreover, if the finder optical system is installed in front of the aperture, when the interchangeable lens is attached to the video camera, it will be difficult to control the aperture accurately. This is because the imaging optical axis and the viewfinder optical axis must be accurately aligned with each optical axis on the video camera side, which is extremely difficult.

Therefore, these problems can be solved by providing a finder behind the diaphragm.

However, with this configuration, the viewfinder sees the light from the actual aperture, making it extremely dark and inconvenient for composition, distance measurement, etc. Therefore, the above-mentioned problem can be solved by opening the aperture before taking an image and narrowing the aperture when starting to take an image.

However, if you do this, the image pickup tube and
Since the dynamic range of an imaging device such as a CCD does not extend to the maximum aperture light, a problem arises in that photometry using an imaging device such as a normal auto iris becomes impossible.

(Objective) An object of the present invention is to provide an imaging device capable of solving the above-mentioned problems of the prior art.

Another object of the present invention is to perform AE lock operation with high precision.
It is also an object of the present invention to provide an imaging device that can be used quickly.

(Examples) Hereinafter, the present invention will be explained in detail based on Examples.

FIG. 1 is an exploded perspective view showing the arrangement of the diaphragm of the present invention.

In the figure, 10 is an aperture ring, 11 is an aperture blade, and 12 is a protruding member fixed to the ring 10 and has a long hole 12a. 13 is an aperture control arm having a pin 13a. Reference numeral 14 denotes an aperture drive motor, and its drive shaft 14a is fixed to the control arm 13. 15 is a half mirror, 16 is a shutter blade, 17 is a shutter drive motor and its drive shaft 17
a is fixed to the shutter blade 16. 18 is a CCD as an imaging means. This may be a MOS image sensor, an image pickup tube, or the like. Also, 1
Reference numeral 9 is an SPC as a photometric means, and it is sufficient if it has a wider dynamic range than the imaging means, and other methods such as CdS can be considered.

The driving force of the aperture drive motor 14 is the control arm 1
3. The protruding member 1 is inserted through the pin 13a and the elongated hole 12a.
2 and rotates the aperture ring 10. The rotation of the aperture ring 10 drives the aperture blades 11 and controls the aperture area. A portion of the subject light passing through the aperture is projected onto a photometric element 19 by a half mirror 15, and at the same time is imaged onto the CCD 18 surface. Further, the shutter blade 16 is driven by the motor 17 to rotate at, for example, 60 rpm, and prohibits the irradiation of subject light to the CCD 18 while the CCD 18 is in the transfer operation.
Prevents smearing.

Note that 23 is a half mirror, which is configured so that a part of the subject light guided to the photometric element via the half mirror 15 can be visually recognized through the eyepiece lens 24. Furthermore, a physical shutter may be used instead of the aperture blades 11 or the like.

FIG. 2 is a diagram showing an example of the configuration of an imaging device according to the present invention.

Note that the same numbers in FIG. 2 as in FIG. 1 indicate the same elements. Reference numeral 1 denotes an imaging optical system, and numeral 2 denotes an aperture means, which includes an aperture ring 10, aperture blades 11, etc. shown in the first figure. 5 is a signal processing circuit for applying various corrections to the luminance component and color component in the output signal of the CCD 18, and 6 is an integrating circuit consisting of, for example, a low-pass filter, which integrates the luminance signal appropriately formed in the signal processing circuit. be. 7 is an error amplification circuit that compares the output of the integration circuit 6 with the potential Vref of a predetermined reference voltage source 8, and sends the error signal to a switch circuit 9 via a sample and hold circuit 25 serving as a second storage means. Enter.

The switch circuit 9 has a common contact d and three switching contacts a to c, and includes a timing signal forming circuit 1 described later.
1 control output x _{1 of the switching contact depending on the level of 2}
and the common contact. Reference numeral 100 denotes an aperture drive coil connected to this common contact, which drives the aperture 2 to narrow down as the voltage level applied to the common contact d increases.

Note that when no current flows through the coil 100, the diaphragm is fully open. Reference numeral 112 is a shutter time setting circuit which specifies the opening angle amount of the rotary shutter 16, that is, the shutter time Tv.
113 is an arithmetic circuit that calculates the shutter speed
Aperture information Av ₁ is output by calculating Tv and the output of the photometric element 19, that is, the brightness information Bv.
Reference numeral 114 designates a sample hold circuit serving as a first storage means for sampling and storing the calculated output Av ₁ at the timing of the control output X ₁ of the timing signal forming circuit 111, which will be described later. 26 is an automatic gain control amplifier (hereinafter abbreviated as AGC),
While the output signal _X4 of the timing signal forming circuit 111 is at a high level, the gain is controlled so that the level of the luminance signal etc. obtained through the signal processing circuit is constant, and when the signal _X4 falls to a low level. ,
It operates to maintain the gain state at the time of this fall. 20 is a gate circuit; 21 is a recording device; the opening period and timing of the gate circuit 20 are controlled by the control output _X3 of the timing signal forming circuit 111; The timing signal forming circuit 111 functions as an aperture control means, and outputs the output of the release circuit 22 for forming a release signal.
The output of the synchronization circuit 117 and the output of the AE lock circuit 27 for forming a synchronization signal are respectively input, and the third
It outputs control outputs X ₁ to _{X 4} as shown in the figure.

Furthermore, 28 is a window comparator for detecting whether or not the output level of the error amplification circuit 7 is within a predetermined minute range, and if so, a flip-flop circuit (hereinafter abbreviated as FF) is used. 2
9 and make the output of FF29 high level. While this FF29 is at a high level, the display circuit 3
0 indicates this by sound or light.

Further, the FF29 is reset in synchronization with the fall of the output _X3 of the timing signal forming circuit 11, and the FF29 is reset.
The output of 9 becomes low level and the display disappears.

Note that the window comparator 28 may have a slight time constant or hysteresis to prevent hunting or the like.

Next, the operation of the circuit shown in the second diagram will be explained based on the timing chart shown in the third diagram.

After turning on a power switch (not shown), an AE lock button (not shown) is pressed at time _t0 , and a high level signal is output from the AE lock circuit 27 while the button is pressed.

Also, since the output _X1 from the timing signal forming circuit 111 falls immediately after the rise of this AE lock signal, the aperture value _Av1 calculated from the output Bv of the SPC 19 and the preset shutter time Tv.
is held.

Note that up to this stage, the level of control output X ₂ is v ₁
So the aperture is fully open. Therefore, since the viewfinder is bright, it is easy to adjust the focus and set the composition.

Also, the time t ₁ immediately after the aperture value Av ₁ is held
At this point, the control output X ₂ output from the timing signal forming circuit 111 reaches the level v ₂ as shown in FIG _. narrowed down to. Then, when a time slightly longer than the longest time necessary for controlling the aperture has elapsed (time t ₂ ), the control output is output from the timing signal forming circuit 111.
Since X ₂ is at level v ₃ as shown in the third diagram, contacts d and c of switch 9 are connected, and diaphragm 2 is servo-controlled in accordance with the output of error amplification circuit 7.

Therefore, at this stage, the aperture can control the amount of light with high precision. Moreover, it starts up extremely quickly and never misses a start.

That is, at time _t2 , when the servo control of the aperture is started by the output of the error amplification circuit 7, the aperture value is
Since the target value has already been almost reached by the output of the SPC, control of the diaphragm by accurate aperture photometry is achieved in a short period of time (times t ₂ to _{t 4} ). The aperture is servo-controlled by the output Av ₂ of the error amplifier 7, and when it almost reaches the target value Av ₂ (time t ₃ ), a high level is output from the window comparator 28,
The display circuit 30 notifies the operator that AE lock has been completed.

Note that the control output X ₁ becomes high level again at, for example, time t ₅ after the control output X ₃ reaches the level v ₃ .

Also, after the aperture reaches the target value Av ₂ , AGC26
When the predetermined time required for stabilization has elapsed, the control output _X4 is synchronized with the vertical synchronization signal _VD (time _t7 ).
becomes low level. As a result, the gain of the AGC 26 and the output of the sample and hold circuit 25 are held at the level at time _t7 . Furthermore, the aforementioned FF29
may be configured to be set at this time _t7 . Immediately after this, at time _t8 , the control output _X2 returns to the level _v1 again, whereby the common contact d and the switching contact a of the switch circuit 9 are connected.

Therefore, the aperture becomes open again, making it suitable for setting the composition of a new subject or screen.

After that, when the release button (not shown) is pressed at an appropriate timing (time t ₉ ), the control output X ₂ becomes level V ₃ , which causes the current to change according to the aperture control value Av ₂ that had been held until then. flows through the aperture drive coil 100, and the aperture is directly narrowed down to an aperture value corresponding to the aperture control value _Av2 .

After that, when a slightly longer time than the longest time required for aperture control has passed, 1 field or 1
The control output X ₃ becomes high level only during the frame period (time t ₁₁ to t ₁₂ ), and the gain of the AGC 26 is fixed.
The output via the recording device 21 is recorded.

Further, upon completion of this recording, the flip-flop 29 is reset at the fall of the control output _X3 (time _t12 ), and the AE lock display by the display circuit 30 is completed.

After that (time t ₁₃ ), the control output X ₂ becomes the v ₁ level again, the aperture is opened, and the AGC starts to perform normal automatic gain control.

In this embodiment, when performing AE lock, AE lock is not performed based on the measured value in the open aperture state, but is performed based on the photometric value obtained by aperture metering using the imaging means. , extremely accurate AE lock is possible.

Furthermore, according to the embodiment of the present invention, in the case where the finder optical system is provided behind the aperture, when the aperture is open, photometry is performed using SPC, CdS, etc., which have a relatively wide dynamic range, and the aperture is narrowed down. In this state, photometry is performed using the output of an imaging device such as a CCD, image pickup tube, or MOS image sensor, so the aperture can be opened as necessary to brighten the viewfinder.

Also, when performing AE lock, the aperture metering value is memorized in order to quickly shift to the aperture metering state, and the aperture is first narrowed down based on this memorized value, making the start-up of aperture control extremely fast. .

Of course, if the aperture response is inherently fast,
Control using such an open photometry value may be omitted.

Furthermore, this embodiment has a display means for indicating that the aperture is stabilized in the stopped-down state, that is, that the AE lock is completed, so that recording will not be performed while the servo aperture is unstable.

In this embodiment, the window comparator 28 is configured to detect whether or not the output level of the error amplifier 7 falls within a predetermined range in order to start displaying the completion of AE lock. For example, detection may be performed using a timer that outputs a high-level pulse after a predetermined time after pressing an AE lock button (not shown). In that case, the output of this timer can be directly input to the FF 29.

In addition, in this embodiment, after performing AE lock in the aperture state, AGC2 is activated to return to the open aperture state.
6 gain lock and sample hold circuit 25
Since the hold is performed, a bright finder can be obtained after AE lock until recording is performed.

Next, FIG. 4 is a diagram showing an embodiment in which the integrating circuit 6 of the image pickup apparatus of the second illustrated embodiment is further improved.

In the figure, reference numeral 50 denotes a shift register which sequentially outputs high-level pulses from output terminals a, b, and _c using a clock _3HD with a frequency three times that of the horizontal synchronizing signal HD. For example, a level period has a length of 1/3 of one horizontal period.

51 to 53 are two-input AND gates, 49 is a three-input OR gate, and 59 is an analog switch. A read-only memory (ROM) 54 stores data to be input to the AND gates 51 to 53 in the form described later. Reference numeral 56 denotes a block address memory for specifying the address of one predetermined memory block in the ROM 54, and in this embodiment, the above address stored in this memory is the address necessary for central spot photometry at the time of AE lock. It corresponds to Further, 57 is a decoder for designating different block addresses depending on the output level of the photometry mode changeover switch 48. 5
Reference numeral 5 denotes a switch circuit for selectively using the output of one of the memory 56 and decoder 57 to designate a block address of the ROM 54.

47 is a flip-flop circuit for switching the switch circuit 55 between AE lock and other times; it is set at the rising edge of the output of the AE lock circuit 27, and the control output X ₃ of the timing signal forming circuit 111 is set. It is reset at the falling edge of . The switch 55 is this flip-flop circuit 4.
Switches according to the Q output of 7. That is, when the Q output is at a high level (set state), that is, when the AE lock state is established, the output of the memory 56 is guided to the ROM 54 to perform center spot photometry, and when the Q output is at a low level (reset state), that is, when the Q output is at a low level (reset state), When not in the AE lock state, the output of the decoder 57 is guided to the ROM 54 to perform various types of photometry specified by the photometry mode changeover switch 48. 60 is an integrating circuit which is reset at the fall of the vertical synchronizing signal _VD shown in the third figure. Further, 204 is a gain control circuit. Further, 61 is a sample and hold circuit as a second storage means according to the present invention, which performs sampling according to the rising edge of the high-level pulse of the AND gate 62, and the gain control circuit 204 until the rising edge of the next high-level pulse is obtained. Holds the output of Note that 201 is a counter connected to the output of the OR gate 49, which counts the total on-time of the analog switch (ASW) 59, and is reset at the fall of _VD . The output of the counter 201 is input to a D/A conversion circuit 202, and its output is connected to a gain control terminal 204a of a gain control circuit 204 through a reciprocal circuit 203. The input of gain control circuit 204 is connected to integration circuit 60, and its output is input to sample and hold. By doing this, even if the photometry range in the screen changes through the analog switch, the output voltage of the gain control circuit 204 is controlled to be the same for objects of the same brightness. The vertical synchronizing signal V _D and the control output X ₄ are input to the AND gate 62 .

Therefore, while the control output _X4 is at a high level, the output of the integral value of the previous field signal via the gain control circuit 204 is sampled and held every time _VD rises.
This value continues to be held while _X4 is low level. 7 is the above-mentioned error amplification device, and this amplification device 7
The output of the switch 9 is directly connected to the switching terminal C of the switch 9. With this structure, until the AE lock signal is output from the AE lock circuit, so-called evaluation photometry is performed using part or all of the output of the CCD 18 in the photometry mode according to the selected position of the photometry mode changeover switch 48. That is, center-weighted metering, average metering, spot metering, etc. are possible, but once the AE lock signal is output, the mode is automatically switched to the center spot metering mode stored in the memory 56 until recording is completed. .

Figure 5 shows the configuration of the ROM 54, and Figure 6 is a diagram explaining such a photometry mode, where the CCD is 3x.
A case of three pixels is shown. ROM
For example, there are three blocks in the block 54, each having a block address of 1 to 3, and each block has a block address of 1 to 3.
It has data addresses of ~3. Each data address stores 3 bits of binarized data as shown in the figure, a predetermined block is designated by an address signal via a switch 55, and a predetermined data address is designated by a counter 58. Then, the 3-bit data within that data address is input to AND gates 51-53, respectively. Therefore, if block address 1 of the ROM 54 shown in FIG. Only the outputs of the pixels marked with diagonal lines are led to an integrating circuit 60 via an analog switch 59 and integrated.

Similarly, if block address 2 is specified, only the CCD output in the shaded area in Figure 6b is integrated, and if block address 3 is specified, the output in the shaded area in Figure 6c, that is, the entire CCD is integrated. It is integrated. Of course,
If the number of data addresses in each block is set to about 252, for example, it becomes possible to weight the outputs of all horizontal lines of the CCD 18. Furthermore, by increasing the number of blocks, the number of photometry modes can be increased accordingly. Of course, as the number of data addresses in each block increases, the types of photometry modes can be increased.

As described above, the output of the processing circuit 5 is masked and then integrated in the integrating circuit 60. Normally, the output of the processing circuit 5 is sampled and held at the rising edge of _{the V D signal} shown in FIG. It will be reset. Also, control output _X4 becomes low level and AE
While the lock is maintained, the sample and hold circuit is in a hold state.

According to this embodiment, the photometry mode can be switched with a simple configuration. Furthermore, since the photometry mode is switched to center spot photometry when the AE lock is activated, there is no need to lock the photometry value when approaching a specific subject, as is the case with conventional silver halide photographic cameras.

In other words, when performing AE lock, for example, bring a backlit person to the center of the viewfinder and press the AE lock button.The aperture will be automatically narrowed down, and the center spot photometric value and
Since the AGC gain is memorized, there is no need to approach the person and perform AE lock. Furthermore, since the switching to central spot photometry accompanying AE lock is automatically performed in conjunction with AE lock operation, the operation is extremely easy.

In this embodiment, when the AE lock is activated, the mode is switched to the center spot metering mode (for example, a mode in which only the center output is used for photometry as shown in Fig. 6a). It may be photometry.

(Effects) As explained above, according to the present invention, exposure control information is stored by the photometry means having a wider dynamic range than the imaging means before performing exposure control using the aperture, etc., and when the aperture starts driving. The aperture is then directly changed to a value corresponding to the exposure control information, and then the aperture is corrected by the output of the imaging means, so the aperture can be controlled very accurately and has a fast start-up. Further, since a second storage means is provided for storing the output of the imaging means in the finally corrected aperture state, it is extremely convenient for performing AE lock. That is, the AE lock information can be obtained quickly, and this AE lock information has high accuracy. In addition, by providing the second storage means, the aperture can be opened once, which makes it easier to decide on the composition and adjust the focus when actually taking an image, and many other effects. has.

[Brief explanation of drawings]

FIG. 1 is an exploded perspective view of an example of essential parts of the imaging device of the present invention, FIG. 2 is a diagram showing an example of the circuit configuration of the imaging device of the invention, and FIG. 3 is an operation timing diagram of the circuit shown in the second diagram. 4 is a diagram showing another example of the configuration of the main part of the circuit shown in the second diagram, FIG. 5 is a diagram showing an example of a ROM reference table, and FIGS. FIG. 3 is a diagram illustrating different photometry modes. 10...Aperture ring, 11...Aperture blade, 15
...Half mirror, 18...Image sensor, 19...
Photometric element, 114...first storage means, 25, 6
1...Second storage means.

Claims (1)

[Scope of Claims] 1. A first switch means for performing photographing, a second switch means for performing exposure control, an imaging means for converting imaging light from a subject into an electrical signal, and a subject. a light metering means other than the image pickup means for detecting the brightness of the image pickup means; a light amount limiting member that limits the amount of light irradiated to the image pickup means; and a light amount limiting member that selectively uses the output of the photometer or the output of the image pickup device. a switching means for driving and controlling the member; and in response to the second switch means, the switching means drives and controls the light amount limiting member according to the output of the photometry means, thereby roughly adjusting the exposure amount. control means for sequentially switching and controlling the switching means to perform fine adjustment of the exposure amount by driving and controlling the light amount limiting member according to the output of the imaging means; and a memory for storing an exposure control signal resulting from the fine adjustment. An imaging apparatus comprising: means for setting an exposure amount based on an exposure control signal in the storage means in response to an operation of the first switch means.