JPH0373034A - Shift scan system - Google Patents

Abstract

PURPOSE:To detect the abnormality of a clock signal for operation on a side supplying a clock for shift scan by inverting a response completion flag bit, which is set by a unit to supply the clock for shift scan, corresponding to the clock for operation in a unit to which the clock for shift scan is supplied. CONSTITUTION:In the case of transmission from a unit 100 to a unit 120, a response completion flag bit 109 is added to prescribed transmission information. An inversion control means 123 of the unit 120, for which the reception completion of all bits in data is recognized, inverts the logic value of the response completion flag bit, which is received on a shift register 121, corresponding to the clock signal for operation. In the unit 100, data are samely fetched from the unit 120 and the abnormality of the clock signal for operation is recognized since a monitoring and controlling means 103 recognizes the presence and absence of the inversion in the response completion flag bit. Thus, the abnormality of the clock signal for operation can be detected on the side of the unit which supplies the clock for shift scan.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a shift scan method used for on-line diagnosis between units constituting a system or for online diagnosis of these units, and the present invention is a method for detecting abnormalities in operating clock signals of units to which shift scan clocks are supplied. For the purpose of detection on the unit side that supplies the shift scan clock, units with shift registers in which internal data is set according to the operating clock are placed facing each other, and the shift registers of each unit are connected in series. However, in a shift scan method in which data is transferred in accordance with a shift scan clock supplied from one unit to each shift register, a response completion flag bit is provided in the data transferred from one unit, and a response completion flag bit is provided in the data transferred from one unit. , comprising an inversion control means for inverting the logical value of the response completion flag bit transferred together with the data in accordance with the operating clock signal, and one unit is provided with an initial setting of the logical value of the response completion flag bit; The configuration includes a monitoring control means that compares the logical value of the response completion flag bit transferred from the other unit with its initial setting value and monitors the operating state of the other unit.

[Industrial application field]

The present invention relates to a shift scan method for online diagnosis between units constituting a system or for online diagnosis of these units.

[Conventional technology]

FIG. 3 is a block diagram showing a conventional configuration of a conventional shift scan method.

In the figure, a diagnostic unit 300 and a diagnosed unit 320 are connected to an uplink data line 325 and a downlink data line 3.
07 to exchange serial data.

Further, a shift scan clock 303 and a data strobe signal 308 are sent from the diagnostic unit 300 to the unit to be diagnosed 320, forming a pair of shift scan interfaces between the diagnostic unit 300 and the unit to be diagnosed 320.

The sense data processing section 302 of the 941M unit 300 supplies an operating clock signal 306 to the shift register 301 and sets downlink transmission data 305. The decoder 326 of the unit to be diagnosed 320 decodes the command part (upper 8
bit) and notifies it to the sense data collection unit 321. The sense data collection unit 321 supplies the operating clock signal 324 to the shift register 323, and outputs the diagnostic data in the unit corresponding to the command as uplink transmission data 322 to the data section of the shift register 323 (
lower 24 bits).

The shift register 301 of the diagnostic unit 300 and the shift register 323 of the unit to be diagnosed 320 are connected via a down data line 307 and an up data line 325, and are operated according to the shift scan clock 303 supplied from the sense data processing section 302. Downlink data line 30
Serial data is transferred via the 7 or upstream data line 325.

Note that the sense data collection unit 321 is connected to the diagnostic unit l-3.
The completion of reception of all bits of these data is recognized by the data strobe signal 308 sent from 00.

[Problem to be solved by the invention]

By the way, in the shift scan method with such a conventional configuration, the operating clock signal 324 is connected to the unit to be diagnosed 3.
The sense data collection unit 321 within the sensor 20 generates the sense data locally. Therefore, even if some abnormality occurs in the operating clock signal 324 and the operation of setting new data to the shift register 323 becomes impossible, the diagnostic unit 300 side will connect the uplink data line 325 from the unit to be diagnosed 320. It is possible to receive data sent via the network. However, in this state, the unit to be diagnosed 320
In this case, the data to be notified to the diagnostic unit 300 cannot be updated, but the diagnostic unit 300 side could not detect whether there is an abnormality in the unit to be diagnosed 320 from the transferred data.

SUMMARY OF THE INVENTION An object of the present invention is to provide a shift scan method in which an abnormality in an operating clock signal of a unit to which the shift scan clock is supplied can be detected on the side of the unit that supplies the shift scan clock.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention.

In the shift scan method, unit internal data is set in a shift register 101. ．．
The shift registers 101 and 121 of each unit are connected in series, and data transfer is performed in accordance with a shift scan clock supplied from one unit to each shift register. .

In the present invention, a response completion flag bit is provided in data transferred from one unit 100.

The inversion control means 123 of the other unit 120 inverts the logical value of the response completion flag bit transferred together with the data in accordance with the operating clock signal.

The supervisory control means 103 of one unit 100 initializes the logical value of the response completion flag bit, compares the logical value of the response completion flag bit transferred from the other unit 120 with its initial setting value, and compares the logical value of the response completion flag bit transferred from the other unit 120 with its initial setting value. The operating status of unit 120 is monitored.

[For production]

When transmitting from one unit 100 to the other unit 120, a response completion flag bit 109 is sent to predetermined transmission information.
is added. Recognizing the completion of reception of all bits of data, the inversion control means 123 of the other unit 120 inverts the logical value of the response completion flag bit received on the shift register 121 in accordance with the operating clock signal.

Further, one unit 100 similarly takes in data from the other unit 120, and the monitoring control means 10
3 recognizes whether or not the response completion flag bit included in the data is inverted.
Recognizes an abnormality in the operating clock signal.

[Example] Hereinafter, an example of the present invention will be described in detail based on the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention.

In the figure, 0.1 in shift register 201.223
, . . . , 32 indicate the bit numbers of the serial signals on the uplink data line 225 and the downlink data line &%2.07.

In addition, the diagnostic unit 200 and the diagnosed unit 220
correspond to unit 100 and unit 120 in FIG. 1, respectively.

The sense data processing section 202 in the diagnostic unit 200 is
An operating clock signal 206 is given to the shift register 201, and downlink transmission data 205 and the unit to be diagnosed 22 are sent as predetermined information corresponding to the function of the diagnostic unit 200.
Sets the initial value of the response completion flag bit 209 to be sent to 0. The sense data processing unit 202 supplies the shift scan clock 203 to the shift registers 201 and 223 in the diagnosis unit 200 and the unit to be diagnosed 220, and synchronizes both while processing the data set in the shift register 201 one bit at a time. Downlink data line 20
Send to 7.

In the unit to be diagnosed 220, the shift register 223 receives the data transferred via the downlink data line 207 using the shift scan clock 203.

The sense data collection unit 221 recognizes the completion of reception of all bits of these data based on the data strobe signal 208 sent from the diagnostic unit 200. On the other hand, the response completion flag bit 228 is applied to the inversion circuit 227 of the unit to be diagnosed 220.

In the inverting circuit 227, the inverting operation is enabled in response to the data strobe signal 208 sent from the diagnostic unit 200, and an inverted response completion flag bit 229 is output.

Further, the decoder 226 of the unit to be diagnosed 220 decodes the command part (upper 8 bits) of the serial data received by the shift register 223 and sends it to the sense data collection unit 220.
Notify 21. The sense data collection unit 221 performs predetermined processing corresponding to the command, and sets the data to be transmitted to the diagnostic unit 200 into the data section (lower 24 bits) of the shift register 223 using the operating clock signal 224. . Further, the response completion flag bit 229 inverted by the inverting circuit 227 is also set in the shift register 223 at the same time.

Furthermore, the sense data processing section 2 in the diagnostic unit 200
02, the data on the shift register 223 (
Set with the inverted response complete flag bit. ) is sent back one bit at a time to the upstream data line 225 and received by the shift register 201.

After completing the return of all bits, the sense data processing unit 20
At step 2, the returned response completion flag bit 210 is transferred from the shift register 201 and compared with the transmitted initial value to recognize whether or not the operating clock signal of the unit to be diagnosed 220 is normal.

〔Effect of the invention〕

As described above, according to the present invention, the unit to which the shift scan clock is supplied inverts the response completion flag bit set by the unit that supplies the shift scan clock in accordance with the operation clock. . Therefore, in the unit that supplies the shift scan clock, the operating state can be recognized by collecting response data corresponding to the instruction to the opposing unit and by noticing whether or not the response completion flag has been inverted. I can do it.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the principle of the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a block diagram showing the conventional structure of the shift scan method. In the figure, 100.120 is a unit, 101.121.201.223.301.323 is a shift register, 1 and 03 are supervisory control means, 123 is a reversal control means, 200.300 is a diagnostic unit, and 202.302 is sense data. Processing unit, 203.303
is the shift scan clock, 205.305 is the downlink transmission data, 206.224.306.324 is the operating clock signal, 207.307 is the downlink data line, 208.308 is the data strobe signal, 209 is the response completion flag bit , 210 is the response completion flag bit sent back, 221
．． 321 is a sense data collection unit, 225.325 is an uplink data line, 226.326 is a decoder, 227 is an inversion circuit, 228 is a received response completion flag bit, 229 is an inverted response completion flag bit, 322 is an uplink This is the sending data. ;4. Rattan F March's Hara Gori Derozuku Map Figure 1 Hee ---J9 is an adventurer and there is Bρ's Ikkoshishutan! J2 Show 710・Review ``1-Iη, Ko-hien-=, L-d Hi

Claims (1)

[Claims] (1) Units (100, 120) having shift registers (101, 121) in which unit internal data is set according to the operating clock are arranged facing each other, and the shift registers (101, 121) of each unit are connected in series. In the shift scan method in which data is transferred in accordance with a shift scan clock supplied from one unit to each shift register, a response completion flag bit is provided in the data transferred from one unit (100), and the other unit (100) is connected. The unit (120) is provided with an inversion control means (123) for inverting the logical value of the response completion flag bit transferred together with the data in accordance with its operating clock signal; Initializes the logical value of the response completion flag bit and sends the response to the other unit (120)
A shift scan method characterized by comprising a supervisory control means (103) that compares the logical value of the response completion flag bit transferred from the unit with its initial setting value and monitors the operating state of the other unit (120). .