JPH0371788A - Television signal coding system - Google Patents

Abstract

PURPOSE:To reduce the information quantity without deteriorating the picture quality by applying PCM coding only to a video signal and converting a synchronizing signal into a code to as to avoid PCM coding. CONSTITUTION:A synchronizing signal detection means 200 detects a synchronizing signal included in each horizontal scanning signal. Then a code conversion means 300 identifies the type of the synchronizing signal detected by the synchronizing signal detection means 200 and converts the type into a predetermined code corresponding to the type. Thus, only a video signal is subjected to PCM coding and the synchronizing signal is converted into a code and the PCM coding is not applied to save the information quantity in comparison with the PCM coding of a conventional system equally for a synchronizing signal and the required transmission line is utilized efficiently.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a television signal encoding circuit, and in particular to a television signal encoding method for an encoding circuit that converts a high-definition television signal into a PCM code.
The purpose of this is to reduce the amount of information without degrading image quality when encoding commercials. In a PCM encoding circuit that converts a television signal composed of a plurality of horizontal scanning signals each composed of a video signal into a PCM code, a synchronization signal detection means for detecting a synchronization signal included in each horizontal scanning signal; Code conversion means is provided for identifying the type of synchronization signal detected by the synchronization signal detection means and converting it into a predetermined code corresponding to the type, and the code conversion means outputs a PCM code corresponding to the video signal. The PCM code of each horizontal scanning signal is output as a PCM code of each horizontal scanning signal.

[Industrial application field]

The present invention relates to a television signal encoding circuit, and in particular to a television signal encoding system for an encoding circuit that converts a high-definition television signal into a PCM code. It consists of color difference signals PR and P, and has a signal band of 20 MHz, 7 MHz, and 7 MHz, which is several times that of the conventional NTSC television signal, so a wideband transmission path is required. Become.

On the other hand, each type of unit transmission line has its own transmission band,
In order to realize a transmission line with a required band, a plurality of unit transmission lines must be installed in the required number.

Therefore, the number of required unit transmission paths is often reduced by a slight reduction in the amount of information.

[Conventional technology]

FIG. 7 is a diagram showing an example of a conventional PCM encoding circuit for this type of high-definition television signal.

In FIG. 7, luminance signal Y, color difference signals PR and PR
are the filters (FIL) provided correspondingly.
)ly, IR and 1. After unnecessary bands are removed by
L) After adjusting the delay time with other color difference signals PR and Pit via 2y, the corresponding analog-to-digital converters (ADC) 3v, 3p* and 3PH, respectively
respectively at a predetermined sampling frequency (for example, the luminance signal Y
is sampled at 42 MHz, color difference signals PR and P are each 14 MHz), and then each sample value is
The coded luminance signal Y", the coded color difference signals PR° and PB are encoded into a PCM code consisting of bits, respectively.
Output as °.

As a result, the amount of information in a high-definition television signal is approximately 5
60 megabits (=8x (42+14+14)).

In order to configure a transmission line for transmitting such an amount of information using a unit transmission line having a transmission band of 135 megabits per second, for example, four lines (540 megabits per second) are insufficient, and five lines are required.

In order to compose such a transmission line with four unit transmission lines, it is necessary to reduce each sampling frequency, which results in deterioration of image quality only in the third unit.

[Problem to be solved by the invention]

As is clear from the above explanation, in conventional television signal encoding systems, each luminance signal Y, color difference signals P, l, and Pit constituting a television signal were equally sampled and PCM encoded. It requires a transmission band corresponding to the amount of information, does not necessarily make efficient use of the transmission path, and if the sampling frequency is forced to be reduced to reduce the amount of information, there is a risk that image quality will deteriorate. .

In the present invention, when PCM encoding a television signal,
The purpose is to make it possible to reduce the amount of information without deteriorating image quality.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, lOO is a PCM encoding circuit to which the present invention is applied.

200 is a synchronization signal detection means provided in the PCM encoding circuit 100 according to the present invention.

300 is code conversion means provided in the PCM encoding circuit 100 according to the present invention.

[Effect]

The PCM encoding circuit 100 is a television that is composed of a plurality of horizontal scanning signals each composed of a plurality of types of synchronization signals composed of a plurality of positive level signals and a plurality of negative level signals, and a video signal that does not contain a negative signal. Convert the signal to PCM code.

The synchronization signal detection means 200 detects a synchronization signal included in each horizontal scanning signal.

The code conversion means 300 identifies the type of synchronization signal detected by the synchronization signal detection means 200, and converts it into a predetermined code corresponding to the type.

Therefore, the PCM encoding circuit encodes only the video signal with PCM, converts the synchronization signal into a code, and does not perform PCM encoding, so the amount of information is reduced compared to the conventional method, which equally encodes the synchronization signal with PCM. , the required transmission path can be used efficiently.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing a television signal encoding method according to an embodiment of the present invention, FIG. 3 is a diagram showing an example of a luminance signal for -frames, and FIG. 4 is an example of a synchronization signal pattern. FIG. 5 is a diagram showing an example of the luminance signal and compression encoded luminance signal in FIG. 2, and FIG. 6 is a diagram showing an example of the operation process of the horizontal synchronization detection circuit in FIG. 2. It is a diagram. Note that the same reference numerals indicate the same objects throughout the figures.

In FIG. 2, only the part of the PCM encoding circuit lOO shown in FIG. 1 related to the luminance signal Y in the PCM encoding circuit shown in FIG. The synchronization signal detection means 2 in FIG.
00, the synchronization type detection circuit 20 provided as the code conversion means 300 in FIG. 1, and the selector (SEL) 50 provided as the PCM encoding circuit 100 are shown. There is.

Note that the parts related to the color difference signals PR and P are also omitted because they are the same as those in the luminance signal Y.

In FIG. 3, the luminance signal Y for -frame is 112
Consists of five horizontal scanning signals H4 (where i indicates 1 to 1125), horizontal scanning signals H7 to H4°, H556 to H6°2, and H11□1 to H02.
, is composed only of the synchronization signal S and does not include the video signal ■, and other horizontal scanning signals H4I to H3, 7 and H
603 to H, , o are synchronization signal S and video signal ■
It consists of

It is assumed that each horizontal scanning signal H, is sampled at 1320 sampling points P1 to P+219, respectively.

In the horizontal scanning signal H8 including the video signal ■, the video signal ■ exists within the range of sampling points PII5 to PIZ67, and the synchronization signal SA exists within the range of sampling points Po to P114 and P, □68 to PI319. exists in

The synchronization signal S included in each horizontal scanning signal H is composed of positive level and negative level signals having a predetermined combination, and the five types of synchronization signals Sa, Sll, Sc, shown in FIG. S.

and S.

The synchronization signal SA includes all horizontal scanning signals H including the video signal I, and horizontal scanning signals Hl to H4 not including the video signal
゜, H5511 to H56□, H569 to H6゜2, and L+z+ to HO25.The synchronization signal S is used for the horizontal scanning signal H8 that does not include the video signal I, and the synchronization signal Sc is , is used for the horizontal scanning signal H363 that does not include the video signal ■, and the synchronization signal S is used for the horizontal scanning signals H+ to H that do not include the video signal ■.
3 and H364 to H367, and the synchronization signal sE is the horizontal scanning signal H3 that does not include the video signal
It is used in 68.

Furthermore, the luminance signal Y corresponding to the video signal I does not include a negative signal level.

Therefore, the synchronizing signal S included in all the horizontal scanning signals H is at the three sample points shown in FIG. 4, that is, the sample point P. , p6
s. and P7. . Sample value V, . , v bso
and V 750 are synchronized by a combination of a negative level signal (-) and a signal of zero level or higher (+)
, , s, , s, and SE can be identified.

Therefore, a negative synchronization type code C8 is determined from 8 bits for each of the five types of synchronization signals S to SE, and in the horizontal scanning signal H where the video signal I is present, the video signal I is Sample points PIt5 to P1□6. The horizontal scanning signal H is sampled and PCM-encoded to have a positive sign, and in order to distinguish it from the negative synchronization type code C3 in the horizontal scanning signal H where the video signal
1□6. By transmitting an all-zero video signal ■4□ generated by PCM encoding all zero-level signals in place of the video signal ■, the receiving side can identify the synchronization type code CS and convert it to the original synchronization signal. SA to S. It becomes possible to restore the .

In FIG. 2, the horizontal synchronization detection circuit 10 includes a comparator (C
) 11, Multipipe Lake (MV) 12 and 14,
Flip-flop (FF) 13 and counter (CNT)
15, and the synchronization type detection circuit 20 includes a counter (CNT) 21, gates (G) 22 and 23, a shift register (SFR) 24, and a flip-flop (FF) 2.
5, gate 26, negative fixed partial code generator (NCG) 27
and an all-zero video signal generation unit (AZG) 28, and the memory control circuit 30 includes a flip-flop (FF
) 31, counter (CNT) 32, waveform shaping section (R3),
Consisting of gates 34, 35 and 36.

In the horizontal synchronization detection circuit 10, a comparator (C) 11 detects the negative part of the manually input luminance signal Y and outputs an output signal O.
l), transmitted to the multipipe lake (MV) 12. The multipipe rake (MV) 12 is activated at the falling edge of the transmitted output signal 01 to generate a positive pulse (output signal 02), and transmits it to the flip-flop (FF) 13. The flip-flop (FF) 13 is set at the falling edge of the transmitted output signal 02, sets the output signal ○ to logic II I ++, and converts the multipipe leak (MV
) 14 and a counter (CNT) 15. The counter (CNT) 15 starts counting the clock signal CLK (=42 MHz) inputted to the clock terminal CK when the output signal O4 inputted to the reset terminal R3T is set to logic "1 ++", When the count value reaches "1000", the flip-flop (FF) 13 is reset and the output signal 03 is set to logic "O". The multivibrator (MV) 14 is activated at the rise of the output signal 03 transmitted from the flip-flop (FF) 13, and outputs a positive pulse "output signal 04".

As described above, the horizontal synchronization detection circuit 10 detects the starting point of each horizontal scanning signal Hi, that is, the horizontal synchronization signal, from the luminance signal Y, and detects the horizontal synchronization signal from the counter (CNT) 21 via the signal line 91.
and 32, and the clock terminals CK of flip-flops (FF) 25 and 31.

Further, the output signal 01 of the comparator (C) 11 is connected to the signal line 92
The signal is also transmitted to the signal input terminal SF of the shift register (SFR) 24 via .

In the synchronization type detection circuit 20, a counter (CNT) 2
1 is initialized by the horizontal synchronization signal input from the horizontal synchronization detection circuit IO to the reset terminal R3T, and by counting the clock signal CLK input manually to the clock terminal CK, the sample point of each horizontal scanning signal H8 is determined. Po to P
I319 is identified, and sample point P11. PIZ67 is manually input to the gate (G) 22, and the sample point Po corresponding to the identification point of the synchronization signal S is
. , P6S. and P? S. game) (G)23.

The gate (G) 22 receives the sample points PII5 to PI267 from the counter (CNT) 21 and outputs a switching signal xI indicating the existence range of the video signal I, and outputs the switching signal xI to the selector ( SEL) 50, and the gate (G) 23 receives sample points P2O, p_bso and P? from the counter (CNT) 21. Every time 5° is input, the clock signal CLK is output and the shift register (SFR)
The signal is transmitted to the clock terminal CK of No. 24.

A shift register (SFR) 24 is a horizontal synchronization detection circuit 1
The sample point P2O of the output signal 01 input from the comparator (C) 11 to the signal input terminal Sl is initialized by the horizontal synchronization signal input from 0 to the reset terminal R3T.
P6S. and P 75G are shifted and held in synchronization with the clock signal CLK input to the clock terminal CK, and the holding results (sampled values V, ., v bso and V
75°) is transmitted to the flip-flop (FF) 25.

The flip-flop (FF) 25 is a shift register (S
The retention results (sample values V, ., V
aS. and V75°) in synchronization with the horizontal synchronization signal input from the horizontal synchronization detection circuit 10 to the clock terminal CK, and outputs the accumulation result as the lower three bits of the synchronization type code CS. It is transmitted to the selector (SEL) 50 along with the negative fixed code NFC1 outputted by the (NCG) 27, that is, the upper five bits of the synchronization type code CS, and is also transmitted to the gate 26.

The gate 26 receives samples (1f!Vwo, V6S (+ and V75
゜ indicates the zero level or higher (+) (for example, logic "'
1''), the switching signal X2 is output and transmitted to the selector (SEL) 50 via the signal line 94.

On the other hand, in the memory control circuit 30, a counter (CNT)
32 is initialized by the horizontal synchronization signal transmitted from the horizontal synchronization detection circuit 10 to the reset terminal R3T, counts the clock signal CLK input to the clock terminal CK, and connects the signal line 95 with the counted value as an address signal a. It is transmitted to the address terminals A of the video signal storage units (LM) 41 and 42 via the sample points PIIS to PIZ6? During this period, gate 36 is set to a conductive state.

In addition, the flip-flop (FF) 31 alternately sets the switching signal The gates 34 and 35 are alternately set to conductive state and cutoff state via
The two output terminals Do are alternately selected.

On the other hand, input terminals DI of the video signal storage units (LM) 41 and 42 are connected to analog-digital converters (AD
C) The encoded luminance signal Yo output from 3v is input.

Further, the clock signal CLK is waveform-shaped by a waveform shaping section (R3) 33, and then passes through either one of the gates 34 and 35, which are alternately set to a conductive state, to the video signal storage section (LM) 41 and The input video signal storage unit (LM) 41 or 42 is placed into a writing state, and the video signal storage unit (LM) 42 or 41 that is not manually input is placed into a read state. Set.

The video signal storage unit (LM) 41 or 42 set to the write state receives the encoded luminance signal Yo input to the input terminal DI.
is stored in accordance with the address signal a manually input to the address terminal A, and the video signal storage unit (
LM) 42 or 41 is the stored encoded luminance signal Y
o is extracted according to address signal a input to address terminal A.

The selector (SEL) 43 is a flip-flop (FF)
Since the video signal storage section (LM) 42 or 41 which is in the continuous state is selected by the switching signal X3 transmitted from the video signal storage section 31, the code extracted from the output terminal Do of the video signal storage section (LM) 42 or 41 is selected. The brightness signal Yo is transmitted to the selector (SEL) 50 via the selector (SEL) 43.

On the other hand, the clock signal CLK output from the waveform shaping section (R3) 33 is outputted from the sampling point P, which is the period in which the gate 36 is in a conductive state, that is, the period in which the video signal (■) of each horizontal scanning signal H exists.
1.5 to P1□6. is output as a strobe signal ST during this period.

The selector (SEL) 50 selects a flip-flop (FF) 25 and a negative fixed partial code generator (NCG) based on the switching signal X transmitted from the gate (G) 22 and the switching signal X2 transmitted from the gate 26. ) 27 is selected, and the compression coded luminance signal Y is selected.
If the switching signal X2 is input after outputting as fl, that is, if the synchronization signal SA is detected, the selector (
SEL) 43 to sample points P Its to P1□67 is selected and outputted as a compression encoded luminance signal YIf, and when the switching signal X2 is not input, that is, the synchronization signal S , ,S, ,S, and S are detected, the all-zero video signal generation unit (AZ
G) All-zero video signal A2 generated by 28 is selected among 1152 sample points, outputted as a compressed encoded luminance signal yIf, and other sample points [1320-(1152+1)=P
During the period 67), the strobe signal ST is not output from the gate 36, so the signal output from the selector (SEL) 50 is invalid.

As is clear from the above description, according to the present embodiment, the synchronization signal S of the encoded luminance signal Yo output from the analog-to-digital converter (ADC) 3Y (not shown) is converted to type A by the synchronization type detection circuit 20. The period of 1152 sample points, which is the range of existence of the video signal I, is identified as one of the synchronization signals S and E type synchronization signals S, and is converted into the corresponding synchronization type code CS consisting of 8 bits and output. If the video signal ■ exists, the encoded video signal ■ is output; if the horizontal scanning signal H8 does not include the video signal ■, the all-zero video signal generator (AZG) 28 outputs the all-zero video signal IAZ. Therefore, the compressed encoded luminance signal Y If output from the selector (SEL) 50 corresponds to 1153 sample points, and is equal to 1320 of the encoded luminance signal Yo. Compared to the sample points, the number of sample points is reduced by about 12.7%, that is, the amount of information is reduced.

FIG. 5 shows an example of the luminance signal Y and the corresponding compressed encoded luminance signal Y j+.

Note that FIGS. 2 to 6 are only one embodiment of the present invention, and for example, the subject of the present invention is not limited to the luminance signal Y, and may also target other color difference signals PR and P. Many other modifications may be considered, such as, but the effects of the present invention remain the same in any case.

Further, the present invention is not limited to the illustrated horizontal scanning signal H and various synchronization signals SA to St, and many other modifications may be considered, but in any case, the present invention may be applied. The effect remains the same.

[Effects of the Invention] As described above, according to the present invention, the PCM encoding circuit encodes only the video signal with PCM, converts the synchronization signal into a code, and converts the synchronization signal into a PCM code.
Since CM encoding is not performed, the amount of information is reduced compared to the conventional method in which synchronization signals are equally PCM encoded, and the required transmission path can be used efficiently.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing a television signal encoding system according to an embodiment of the present invention, and FIG.
4 is a diagram showing an example of a synchronization signal pattern; FIG. 5 is a diagram showing an example of the luminance signal and compression-encoded luminance signal in FIG. 2;
FIG. 6 is a diagram showing an example of the operation process of the horizontal synchronization detection circuit in FIG. 2, and FIG. 7 is a diagram showing an example of a conventional PCM encoding circuit. In the figure, lv S IPR, l gate is a filter (FI
L), 2y-mu□-22yang is a delay circuit (DIL), 37
．． 3□, 3□ are analog-digital converters (ADC),
10 is a horizontal synchronization detection circuit, 11 is a comparator (C), 12 and 14 are multi-by-break (MV), 13.25 and 31 are flip-flops (FF), 15.21 and 32 are counters (CNT), 22 .23.26.34
．． 35 and 36 are gates, 24 is a shift register (S
FR), 27 is a negative fixed partial code generator (NCG), 28
33 is an all-zero video signal generation unit (AZG), and 33 is a waveform shaping unit (
R3), 41 and 42 are video signal storage units (LM);
3 and 50 are selectors (SEL), 91 to 96 are signal lines, 100 is a PCM encoding circuit, 200 is a synchronization signal detection means, and 300 is 100.碌ωvts. Synchronous A full number pattern Figure 2
■ Presentation number ■

Claims (1)

[Scope of Claims] A television comprising a plurality of horizontal scanning signals each comprising a plurality of types of synchronization signals comprising a plurality of positive level and negative level signals and a video signal not including a negative level signal. A PCM encoding circuit (100) that converts a signal into a PCM code includes: a synchronization signal detection means (200) that detects a synchronization signal included in each of the horizontal scanning signals; and a synchronization signal detected by the synchronization signal detection means (200). code conversion means (300) for identifying the type of signal and converting it into a predetermined code corresponding to the type; A television signal encoding method characterized in that the output code is output as a PCM code of each horizontal scanning signal.