JPH0371749A - Atm cell insertion system - Google Patents

Abstract

PURPOSE:To easily realize a desired cell transfer characteristic by setting a delay of a cell on an asynchronous transfer mode(ATM) input highway and an insertion ratio of an insertion cell into optimum values with (n) (counter prescribed value of time measuring circuit). CONSTITUTION:When no idle cell exists in an ATM input highway 1 from production of an insertion cell till laps of a prescribed time, an insertion cell is inserted to a cell location at laps of a prescribed time and outputted as an ATM output highway 9, and a cell in the cell location inserted onto the ATM input highway 1 is awaited for one cell time by a 1st buffer 2. The cells of succeeding cell locations are outputted to the ATM output highway 9 with a deviated location by one each. The deviation is restored when an idle cell exists on the ATM input highway 1. Thus, the desired cell transfer characteristic is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an ATM cell insertion method in an Asynchronous Transfer Mode (ATM) switch.

[Conventional technology]

Conventionally, digital switching equipment has had a switching function using a circuit switching method or a packet switching method.

In the case of circuit-switched systems, the time slots have a time-division multiplexed highway, with fixed frames (typically 125μ
One call occupied a time slot at a predetermined time position every second period). In this case, in order to insert, for example, a signal into such a highway, a hardware circuit is provided to determine a signal time slot in advance, and the time slot is designed to be empty at the insertion location.

On the other hand, in the case of the packet switching method, the processing device performs the insertion of signals and the like as well as the switching, and traffic control for the insertion is easily performed.

In recent years, CCITT (International Telegraph and Telephone Consultative Committee) etc.
M is attracting attention as a method different from the circuit switching method and the packet switching method. In ATM, switching is realized by hardware, similar to the circuit switching system. The highway in ATM is different from the highway in circuit switching.

In ATM, information is transferred in a type of packet with a fixed length (approximately 40 to 120 bytes) called a cell. Cell locations are determined on ATM highways, and cells are entered only when information to be sent is generated.

When there is no information, the cell becomes an empty cell.

Conventionally, there has been no method of inserting signals into the ATM highway.

[Problem to be solved by the invention]

First, considering inserting a signal cell into the ATM highway, it is sufficient if there is an empty cell on the highway at the time of insertion, but if the usage rate is high and there are no empty cells, the insertion will have to wait forever. Another possible method is to forcefully insert signal cells by making the cells on the highway wait, but when there are many inserted cells, the delay of the cells on the highway increases.

Therefore, there is a problem that a cell insertion method with good characteristics cannot be realized using the normal method.

An object of the present invention is to solve this problem and provide an ATM cell insertion method that has not existed in the past.

[Means to solve the problem]

The ATM cell insertion method of the present invention includes an input highway for transferring ATM cells and an ATM cell inserted into the input highway.
A whose input is the inserted cell signal line from the circuit that generates cells, and whose output is the output highway that transfers ATM cells.
In the TM cell insertion circuit, A on the input highway
A first buffer that temporarily stores TM cells, a second buffer that temporarily stores inserted cells on the inserted cell signal line, a time measurement circuit, and an output control circuit, and the output control circuit When it is detected that the first buffer is empty for the first time after a predetermined period of time has elapsed from the time when it is recognized that there is an ATM cell in the buffer, the ATM cell to be inserted from the second buffer is inserted. If the first buffer is not empty until the predetermined time period has elapsed, the ATM cell to be inserted from the second buffer is sent to the output highway when the predetermined time period has elapsed; In this case, the ATM cell is inserted by sending the ATM cell from the first buffer to the output highway.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows the configuration of an ATM cell insertion circuit according to an embodiment of the present invention.

ATM input highway 1 is the inserted highway and is connected to first buffer 2 .

The first buffer 2 outputs the ATM internal highway 6 and the first buffer empty indication line 10, inputs the first buffer control line 11, stores the ATM input input highway 1, and When the control line 11 is logic "1", the accumulated cells are sequentially output to the ATM internal highway 6,
If there are no accumulated cells, empty cells are output to the ATM internal highway 6. The first buffer 2 outputs a logic "O" to the ATM internal highway 6 when the first buffer control line 11 is logic "O". If the first buffer 2 has accumulated cells, the first buffer empty indicator line 10
A logic "0" is output to the cell, and a logic "1" is output when there is no accumulated cell.

(Buffer free space is logic "1".>Cell generation circuit 3
is a circuit that generates cells to be inserted, such as a signal device, and is connected to the second buffer 5 via an inserted cell signal line 4. When the cell generating circuit 3 generates a cell to be inserted, it outputs the cell to the inserted cell signal line 4.

The second buffer outputs the inserted cell highway 7 and the second buffer empty indication line 12, and outputs the second buffer control line 13.
is input, cells arriving from the inserted cell signal line 4 are stored, and when the second buffer control line 13 is logic "1", the stored cells are outputted to the inserted cell highway 7. The second buffer 5 has a second buffer control line 13 with logic r OJ
In this case, the logic rQJ is output to the inserted cell highway 7.

The second buffer 5 outputs a logic "1" to the second buffer empty indicator line 12 when there are accumulated cells and the second buffer control line 13 is at logic rQJ; otherwise, Outputs logic r Q J.

(The buffer base is logic "1" and the logic is opposite to the first buffer empty display line 10.) The first OR circuit 8 connects the ATM internal highway 6 from the first buffer 2 and the The input cell highway 7 from the second buffer 5 is logically summed and outputted to the ATM output highway 9.

The time measurement circuit 16 is composed of a counter, etc., and has a second buffer empty display line 12 from the second buffer 5 as a measurement terminal (ENABLE), and a clock line 21 from a clock source (not shown) as a clock terminal. (CLOCK), input the third insertion instruction line 19 from the second OR circuit 18 to the reset terminal (lower R3), and connect the second insertion instruction line 19 from the overflow terminal (OV) to the second OR circuit 18. An insertion instruction line 17 is output. The time measurement circuit 16 can set a predetermined value in advance. In the time measurement circuit 16, the measurement terminal is logic "・1"
When , the counter is incremented by the clock from the clock terminal, and when the logic is rQJ, it is not incremented. The time measuring circuit 16 outputs a logic "1" to an overflow terminal when the counter value reaches a predetermined value, and otherwise outputs a logic r Q J. When the time measuring circuit 16 inputs logic "1" from the reset terminal, it resets the counter at the next clock to set the counter value to O, and in the case of logic "O", there is no effect.

The output control circuit 22 is an AND circuit 14. Second OR circuit 1
8. It is composed of a buffer control circuit 20. The AND circuit 14 inputs the first buffer empty display line 10 from the first buffer 2 and the second buffer empty display line 12 from the second buffer 5, performs the logical product ', and calculates the second It is output to the first insertion instruction line 15 connected to the OR circuit 18. The second OR circuit 18 connects the first insertion instruction line 15 from the AND circuit 14 and the second insertion instruction line 1 from the time measurement circuit 16.
7 as an input, performs a logical sum, and outputs the result to one third insertion instruction line connected to the time measurement circuit 16 and the buffer control circuit 20. The buffer control circuit 20 is the second OR circuit 1
The third insertion instruction line 19 from 8 is input, and the first buffer control line 11 to the first buffer 2 and the second buffer control line 13 to the second buffer 5 are output. When the third insertion instruction line 19 is a logic "1", the buffer control circuit 20 sets a logic "0" to the first buffer control line 11, and the second buffer control circuit 20 outputs a logic "0" to the first buffer control line 11. 13, and when the third insertion instruction line 19 is logic "O", logic rl is output to the first buffer control line 11, and logic "O" is output to the second buffer control line 13. " is output.

Next, the operation of this embodiment will be explained.

Initially, it is assumed that there is no inserted cell from the cell generation circuit 3 and that the time measurement circuit 16 is in an initial state.

At this time, since no cells are stored in the second buffer 5, the second buffer empty indicator line 12 becomes logic "0". Therefore, since the measurement terminal becomes the logic r□, the counter value of the time measurement circuit 16 remains O, and the second insertion instruction line 17 becomes the logic "0". Therefore, regardless of the logic value of the first buffer empty indicator line 10 from the first buffer 2, the first insertion instruction line 15 is also logic "0", and the second insertion instruction line 17 is also logic r□. Yes, and the third insertion instruction line is also logic "0". Therefore, the operation of the buffer control circuit 20 outputs a logic "1" to the first buffer control line 1 and a logic "0" to the second buffer control line 13. Therefore, since the first buffer control line 11 is logic "1", the first buffer 2 sequentially transfers the accumulated cells (empty cells if there are no accumulated cells) to the ATM internal highway 6.
Output to. Further, since the second buffer control line 13 is at logic "0", the second buffer 5 outputs logic "0" to the inserted cell highway 7. In the first OR circuit 8, since the inserted cell highway 7 is logic "O", the ATM internal highway 6 is outputted to the ATM output highway 9 as is. As mentioned above, if there are no cells to insert, the ATM
The input input way 1 is directly output to the ATM output highway 9.

Now suppose that a cell to be inserted occurs. Cells to be inserted are stored in the second buffer 5 from the cell generation circuit 3 via the inserted cell signal line 4. As a result, the second buffer empty indicator line 12 from the second buffer 5 becomes a logic "1".
Changes to The time measurement circuit 16 has a measurable terminal that is logic “1”.
”, the counter value starts clock incrementing. Even in this case, the second insertion instruction line 17 remains at logic "O" until the counter value reaches the predetermined value. Until the predetermined value is reached, the third insertion instruction line 19 is connected to the first insertion instruction line 15.
is output as is, and the first insertion instruction line 15 is the AND of the first buffer empty display line 10 and the second buffer empty display line 12 which is logic "1". When the first buffer empty indication line 10 from 2 becomes logic rlJ (meaning buffer empty), the -th insertion instruction line 15 and third insertion instruction line 19 become logic rlJ, and time measurement begins. Logic "1" is input to the reset terminal of the circuit 16, and the counter value becomes O at the next clock, and
First buffer control line 11 from buffer control circuit 20
is logic “O”, second buffer control line 13 is logic “1”
Therefore, the first buffer 2 outputs the logic "O" to the ATM internal highway 6, the second buffer 5 outputs the accumulated cells to the inserted cell highway 7, and the first OR circuit 8
Since the ATM internal highway 6 is at logic "O", the cells on the inserted cell highway 7 are output to the ATM output highway 9. At this time, the second buffer 5 simultaneously sets the second buffer empty indication line 12 to logic "O", so one third insertion instruction line becomes logic "0", and the first buffer control line 11 The logic of the second buffer empty indicator line 12 is inverted again, and the first OR circuit 8 again outputs the ATM internal highway 6 to the ATM output highway 9 at the next cell position.

In this way, if there is an empty cell on the ATM input highway 1 during the elapse of a predetermined period of time after the insertion cell is generated, the insertion cell is inserted into the first empty cell position and output as one ATM output highway.

If the first buffer empty front thread line 10 does not become logic "1" until the counter value reaches a predetermined value, logic "1" is output to the overflow terminal of the time measurement circuit 16, and the second insertion The instruction line 17 becomes logic "1", the third insertion instruction line 19 becomes logic "1", and the above-described operation is performed. This means that the ATM
If there are no empty cells in input way 1, an inserted cell is inserted at the cell position when a predetermined time has elapsed and is output as ATM output highway 1, and the cell is inserted into the inserted cell position on ATM input way 1. Cell is first buffer 2
Waits for one cell time.

Cells at subsequent cell positions are also output to the ATM output highway 9 at positions shifted by one. This deviation returns to the original state when an empty cell appears in ATM input way 1.

In this embodiment, a case is shown in which the predetermined value of the counter of the time measurement circuit 16 is set in advance, but the present invention also includes a case where it is dynamically set from a control device or the like.

〔Effect of the invention〕

As explained above, in the present invention, when the clock has a period of one cell and the predetermined value of the counter of the time measurement circuit is n, the AT
It is possible to guarantee a cell insertion rate of 100/n%, regardless of the M-input coverage rate (rate of non-empty cells). If the method prioritizes insertion, this ratio will be 100%, and ATM entry on the Kabaka Highway will be delayed up to infinity. Also, if you enter the ATM on the Kabaka Highway, there will be no delay when entering the ATM on the Kabaka Highway.
However, the insertion rate is not guaranteed and will be at least 0%. That is, according to the present invention, a flexible ATM cell insertion method can be realized.

Therefore, according to the ATM cell insertion method of the present invention, the delay of cells on the ATM input highway and the insertion rate of inserted cells are n
Since the optimum value can be set by , it is possible to easily realize desired cell transfer characteristics.

Input instruction line, 18...Second OR circuit, one...Third insertion instruction line, 20...Buffer control circuit, 21...
- Clock line, 22...output control circuit.

Claims (1)

[Claims] In an ATM cell insertion circuit that has an input highway for transferring ATM cells and an insertion cell signal line from a circuit that generates an ATM cell to be inserted into the input highway as input, and an output highway for transferring ATM cells as output, the input A first buffer for temporarily accumulating ATM cells on the highway, a second buffer for temporarily accumulating inserted cells on the inserted cell signal line, a time measurement circuit, and an output control circuit, the output control circuit comprising: The ATM cell should be inserted from the second buffer when it is first detected that the first buffer is empty between the time when it is recognized that there is an ATM cell in the second buffer and a predetermined period of time has elapsed. A
Sending the TM cell to the output highway, and if the first buffer does not become empty until the predetermined time elapses, sending the ATM cell to be inserted from the second buffer to the output highway when the predetermined time elapses. However, in other cases, the ATM cell is inserted by sending the ATM cell from the first buffer to the output highway.