JPH0371618U

JPH0371618U -

Info

Publication number: JPH0371618U
Application number: JP13265489U
Authority: JP
Priority date: 1989-11-15
Filing date: 1989-11-15
Publication date: 1991-07-19

Description

[Brief explanation of drawings]

第１図ａは本考案による平板形チツプコンデン
サの一実施例を示す平面図、第１図ｂは同図ａの
裏面図、第２図ａは第１図に示す平板形チツプコ
ンデンサをＦＥＴ回路に組込んだときの一部平面
図、第２図ｂは同図ａの断面図、第３図は平板形
チツプコンデンサをＦＥＴ回路に組込んだときの
回路図、第４図ａは従来の平板形チツプコンデン
サを示す平面図、第４図ｂは同図ａの裏面図、第
５図ａは第４図に示す平板形チツプコンデンサを
ＦＥＴ回路に組込んだときの一部平面図、第５図
ｂは同図ａの断面図である。１……ＦＥＴ、３……コンデンサ、３１……誘
電体部材、３２〜３６……電極、７……ＭＩＣ基
板。 Fig. 1a is a plan view showing an embodiment of the flat chip capacitor according to the present invention, Fig. 1b is a back view of Fig. Fig. 2b is a cross-sectional view of Fig. 2a, Fig. 3 is a circuit diagram when a flat chip capacitor is incorporated into an FET circuit, and Fig. 4a is a diagram of a conventional FET circuit. FIG. 4b is a plan view showing the flat chip capacitor, FIG. 4b is a back view of FIG. Figure 5b is a sectional view of figure a. 1... FET, 3... Capacitor, 31... Dielectric member, 32-36... Electrode, 7... MIC board.

Claims

[Scope of utility model registration request]

A flat dielectric member having a plurality of electrodes spaced apart from each other on one surface of the dielectric member, and other electrodes spaced apart from each other at positions corresponding to the electrodes on the other opposing surface. Chip capacitor.