JPH037068A - Multiple controller - Google Patents

Multiple controller

Info

Publication number
JPH037068A
JPH037068A JP13885989A JP13885989A JPH037068A JP H037068 A JPH037068 A JP H037068A JP 13885989 A JP13885989 A JP 13885989A JP 13885989 A JP13885989 A JP 13885989A JP H037068 A JPH037068 A JP H037068A
Authority
JP
Japan
Prior art keywords
control circuit
circuit
control
fault
failure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13885989A
Other languages
Japanese (ja)
Other versions
JP2667512B2 (en
Inventor
Yasuhiro Ando
康裕 安東
Yasuyuki Yamaguchi
山口 泰幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP13885989A priority Critical patent/JP2667512B2/en
Publication of JPH037068A publication Critical patent/JPH037068A/en
Application granted granted Critical
Publication of JP2667512B2 publication Critical patent/JP2667512B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To improve the availability of system of providing fault reset signals to all control circuits, based on fault signals fed from respective control circuits, upon fault of any control circuit and releasing fault mode automatically thereby ensuring multiplex configuration at all times. CONSTITUTION:Multiple controller comprises an automatic reset circuit 9 for detecting fault in multiple control circuits A6, B7 during operation of a power controller 2 through any one of the control circuits A6, B7 and providing fault reset signals to all multiple control circuits to interrupt the operational power source of the control circuit temporarily, a circuit 8 for selecting the reset circuit through function of the automatic reset circuit 9, and a circuit 80 for switching the control circuit based on a signal selected through the selecting circuit 8. By such arrangement, fault rest is executed automatically upon detection of a fault during operation of one control circuit and a sound control circuit is selected to resume operational control immediately.

Description

【発明の詳細な説明】 [発明の目的コ (産業上の利用分野) 本発明は、1つの制御対象に対して、複数の制御回路を
持ち、例えば1つの制御回路が運転制御中に故障検出し
た場合、自動的に故障リセットを実行し健全な制御回路
を選択して直ちに運転制御を再開する信頼性の高い多重
化制御装置に関する。
Detailed Description of the Invention [Purpose of the Invention (Field of Industrial Application) The present invention has a plurality of control circuits for one controlled object, and for example, one control circuit detects a failure during operation control. The present invention relates to a highly reliable multiplex control device that automatically performs a fault reset when a failure occurs, selects a healthy control circuit, and immediately resumes operation control.

(従来の技術) ここでは、制御対象としてサイリスク素子を用いた電力
変換器を用い、制御装置としてサイリスクの位相制御装
置を用いて説明する。電力変換器は、交流電力を直流に
変換する順変換器と、順変換器に流れる電流を検出する
変流器と、順変換器の出力電圧を検出する変圧器により
構成される。
(Prior Art) Here, a description will be given using a power converter using a Cyrisk element as a controlled object and a Cyrisk phase control device as a control device. A power converter includes a forward converter that converts alternating current power into direct current, a current transformer that detects the current flowing through the forward converter, and a transformer that detects the output voltage of the forward converter.

前記、位相制御装置は電圧制御回路又は、1!流副制御
路と、これらの出力によ)サイリスタの通電位相を制御
する位相制御回路と、前記、順変換器の電流及び、電圧
検出信号とより故障を検出する保護回路とKよシ構戒さ
れる。これらの基本動作については、例えば、「サイリ
スタ制御DCモータの運転と保守J (1!気書院発行
 上山直彦編)の第2章 P31−P57に詳細に述べ
られているので、ここでは、多重化制御の切り替えにつ
いて述べる。
The phase control device is a voltage control circuit or 1! A secondary control path, a phase control circuit that controls the energization phase of the thyristor (based on these outputs), a protection circuit that detects a failure based on the current and voltage detection signals of the forward converter, and be done. These basic operations are described in detail in, for example, "Operation and Maintenance of Thyristor Controlled DC Motors J (1! Published by Kishoin, edited by Naohiko Ueyama), Chapter 2, P31-P57. Let's talk about control switching.

1つの電力変換器に対して、2つの制御回路を設け、常
に1つの制御回路のみにより電力変換器を制御し、その
回路に異常が生じた場合、他の健全な制御回路に切ル替
え制御を継続する構成を第3図に示す。第3図において
、制御回路A6で運転中に異常が発生した場合、制御回
路A6の故障信号160が選択回路8に入力され、選択
回路8は、健全な制御回路B7を選択し切り替え回路8
0により、制御回路を前記制御回路B7に切り替える。
Two control circuits are provided for one power converter, and the power converter is always controlled by only one control circuit, and if an abnormality occurs in that circuit, control is switched to another healthy control circuit. FIG. 3 shows a configuration that continues. In FIG. 3, when an abnormality occurs in the control circuit A6 during operation, a failure signal 160 of the control circuit A6 is input to the selection circuit 8, and the selection circuit 8 selects a healthy control circuit B7 and switches the control circuit A6 to the switching circuit 8.
0 switches the control circuit to the control circuit B7.

これにより、電力変換器2の運転制御が継続される。こ
の時、前記制御回路A6の故障信号60により、表示回
路81は、制御回路A6の故障を表示する。この状態で
運転中に、制御回路B7で異常が発生すると、制御回路
A6及び、制御回路B7の2!故障として制御装置は、
電力変換器2の制御を停止する。また、1つの制御回路
異常により、電力変換器2の入力電流及び、出力電圧に
その影響が現れ、これらの異常動作を入力1!流につい
ては、変流器141及び、変流器B42により検出し、
出力電圧についてFit圧検出器A5J及び、電圧検出
器B54゛により検出すると、制御回路A6及び、制御
回路B7は同時に故障状態になり電力変換器2の制御を
停止する。
Thereby, the operation control of the power converter 2 is continued. At this time, the display circuit 81 displays the failure of the control circuit A6 based on the failure signal 60 of the control circuit A6. If an abnormality occurs in control circuit B7 during operation in this state, 2! of control circuit A6 and control circuit B7! The control device as a failure
Control of the power converter 2 is stopped. In addition, an abnormality in one control circuit affects the input current and output voltage of the power converter 2, and these abnormal operations are caused by input 1! The current is detected by a current transformer 141 and a current transformer B42,
When the output voltage is detected by the Fit pressure detector A5J and the voltage detector B54', the control circuit A6 and the control circuit B7 simultaneously go into a failure state and stop controlling the power converter 2.

(発明が解決しようとする課題) 以上のように、従来技術においては次のような問題があ
った。
(Problems to be Solved by the Invention) As described above, the prior art has the following problems.

(1)  制御対象である電力変換器2が共通であるた
め、一方の制御回路が異常を発生すると、電力変換器2
の入力電流及び、出力電圧に影響を及ぼし、その結果制
御回路A6及び、制御回路B7が同時に1に障状態とな
シミ力変換器2の制御が停止する。
(1) Since the power converter 2 that is the control target is common, if an abnormality occurs in one control circuit, the power converter 2
As a result, the control circuit A6 and the control circuit B7 are simultaneously in a fault state, and the control of the stain force converter 2 is stopped.

(2)制御回路が故障になると、人間系での故障復帰が
必要であった。
(2) When a control circuit fails, it is necessary for a human system to recover from the failure.

(3)制御回路1つが異常となり、他方に切り替えた直
後、その過渡変化により切り替光られた制御回路側で、
再度故障検出した場合、制御回路の2!故障となシミ力
変換器2の制御が停止する。
(3) Immediately after one control circuit becomes abnormal and switches to the other, the control circuit that was switched due to the transient change,
If the failure is detected again, the control circuit's 2! If there is a failure, the control of the stain force converter 2 will stop.

本発明は、従来技術の問題点を鑑みて成されたものであ
シ、1つの制御回路で異常が発生すると、その制御回路
からの故障信号により、多重化された全制御回路に故障
リセット信号を自動的に入力し、その後、選択回路によ
り正常な制御回路を選択し、電力変換器の運転制御を継
続し、また、前記故障リセット信号でも故障復帰しない
制御回路については、その制御回路の操作電源を短時間
遮断する事により、制御回路内部の全信号をイニシャラ
イズ(初期化)シ、故障信号を除去し、前記電力変換器
の制御を継続出来る多重化制御装置を提供することにあ
る。
The present invention was made in view of the problems of the prior art.When an abnormality occurs in one control circuit, a fault signal from that control circuit sends a fault reset signal to all multiplexed control circuits. is automatically input, and then a normal control circuit is selected by the selection circuit to continue operation control of the power converter, and for control circuits that do not recover from the fault even with the fault reset signal, the control circuit is operated. It is an object of the present invention to provide a multiplex control device which can initialize all signals inside a control circuit and remove a fault signal by cutting off the power supply for a short time, thereby continuing to control the power converter.

(問題を解決するための手段) pJ1図に本発明の構成を示す。制御回路A6及び、制
御回路B7は多重化された制御回路であシ、これら多重
化制御回路を切り替える切り替え回路80と、前記制御
回路により運転制御される電力変換器2と、この電力変
換器2の入力電流を検出する変流器A4J及び、変流器
B42と、前記、電力変換器2の出力電圧を検出する電
圧検出器A53及び、電圧検出器B54と、前記多重化
された制御回路人6及び、制御回路B7の何れか1つの
制御回路によりミ力変換器2を運転制御中、制御回路A
6及び、制御回路B7が故障したことを検出し、多重化
された全制御回路に故障リセット信号を出力し、また、
前記故障リセット信号入力後尚故障継続している制御回
路に対して制御回路の操作電源を短時間遮断する自動リ
セット回路9と、この自動リセット回路9の動作完了後
、尚制御回路が故障状態の時、制御回路異常と判断し表
示する表示回路81と、前記自動リセット回路9の作用
により、制御回路A 6.及び、制御回路B7が故障復
帰した場合、故障復帰した制御回路を選択する選択回路
8と、この選択回路8の選択信号により制御回路を切り
′替える切り替え回路80を具備している。
(Means for solving the problem) Figure pJ1 shows the configuration of the present invention. The control circuit A6 and the control circuit B7 are multiplexed control circuits, and include a switching circuit 80 for switching these multiplexed control circuits, a power converter 2 whose operation is controlled by the control circuit, and this power converter 2. a current transformer A4J and a current transformer B42 that detect the input current of the power converter 2, a voltage detector A53 and a voltage detector B54 that detect the output voltage of the power converter 2, and the multiplexed control circuit. While the power converter 2 is being controlled by any one of the control circuits 6 and B7, the control circuit A
6 and detects that the control circuit B7 has failed, outputs a failure reset signal to all multiplexed control circuits, and
An automatic reset circuit 9 cuts off the operating power of the control circuit for a short period of time for a control circuit that is still in failure after inputting the failure reset signal, and after the operation of this automatic reset circuit 9 is completed, it 6. By the action of the display circuit 81 which determines and displays an abnormality in the control circuit and the automatic reset circuit 9, the control circuit A 6. Furthermore, when the control circuit B7 recovers from the failure, it is provided with a selection circuit 8 that selects the control circuit that has recovered from the failure, and a switching circuit 80 that switches the control circuit according to the selection signal of the selection circuit 8.

(作用) 以上の構成により、片方の制御回路、例えば制御回路A
6が運転中に異常発生した場合、その故障信号eoVc
より多重化された制御回路A6及び、制御回路B7に、
故障リセット信号9oが自動リセット回路9よシ入力さ
れる。この故障リセット信号90完了後、前記自動リセ
ット回路9では、制御回路A6及び、制御回路B7が故
障状態か制御可能状態かを判断し、故障状態の制御回路
については、その?jU御回路の操作電源を短時間遮断
する電源イニシャライ、e信号(制御回路A6に対して
は電源イニシャライズ信号92、制御回路87に対して
は電源イニシャライズ信号91)を自動リセット回路9
が再び出力する。電源イニシャライズが実行された制御
回路では、制御信号がすべて初期化されるため、部品の
ハード的な故障以外は、すべての故障モードが解除され
、電力変換器2の運転制御が継続される。
(Function) With the above configuration, one control circuit, for example, control circuit A
6 when an abnormality occurs during operation, the failure signal eoVc
In the more multiplexed control circuit A6 and control circuit B7,
A fault reset signal 9o is input from the automatic reset circuit 9. After the failure reset signal 90 is completed, the automatic reset circuit 9 determines whether the control circuit A6 and the control circuit B7 are in a failure state or in a controllable state, and whether the control circuit in the failure state is in a controllable state or not. The automatic reset circuit 9 generates a power initialization signal (power initialization signal 92 for the control circuit A6 and a power initialization signal 91 for the control circuit 87) to cut off the operating power of the jU control circuit for a short time.
outputs again. In the control circuit in which the power supply initialization has been performed, all control signals are initialized, so that all failure modes are canceled except for a hardware failure of a component, and operation control of the power converter 2 is continued.

(実施例) 本発明の実施例を第1図に示す。制御回路A6及び、制
御回路B7は多重化された制御回路であシ、これら多重
化制御回路を切り替える切り替え回路80と、前記制御
回路により運転制御される電力変換器2と、この電力変
換器2の入力電流を検出する変流器A41及び、変流器
B42と、前記、電力変換器2の出力電圧を検出する電
圧検出器A5J及び、電圧検出器B54と、前記多重化
された制御回路A6及び、制御回路B7の何れか1つの
制御回路により電力変換器2を運転制御中、制御回路A
6及び、制御回路B7が故障したことを検出し、多重化
された全制御回路に故障リセット信号を出力し、また、
前記故障リセット信号入力後面故障継続している制御回
路に対して制御回路の操作電源を短時間遮断する自動リ
セット回路9と、この自動リセット回路9の動作完了後
、尚制御回路が故障状態の時、制御回路異常と判断し表
示する表示回路81と、前記自動リセット回路9の作用
により、制#回路A6及び、制御回路B7が故障復帰し
た場合、故障復帰した制御回路を選択する選択回USと
、この選択回路8の選択信号によう制御回路を切り替え
る切り替え回路80により構成される。また、前記自動
リセット回路9の詳細構成を第2図に示す。自動リセッ
ト回路9は、前記、制御回路A6からの故障信号60を
受けて、故障リセット信号90をOR回路97を介して
出力する故障リセット信号発生器6Iと、前記、制御回
路B7からの故障信号7Qを受けて、故障リセット信号
90t−OR回路97を介して出力する故障リセット信
号発生器71と、前記、OR回路97の出力信号である
故障リセット信号90の完了時に、前記、制御回路A6
からの故障信号6θを確認し、故障状態であれば電源イ
ニシャライズ信号92を出力する電源イニシャライズ信
号発生器62と、同様に、前記、OR回路97の出力信
号である故障リセット信号9oの完了時に、前記、制御
回路B7からの故障信号70を確認し、故障状態であれ
ば電源イエシャ2イズ信号91を出力する電源イニシャ
ライズ信号発生器72と、前記、電源イニシャライズ信
号92の完了時に、前記、制御回路A6からの故障信号
5θを確認し、故障状態であれば制御回路A6の故障表
示信号93を出方する故障検出器A6jと、前記、電源
イニシャライ、e宿号9ノの完了時に、前記、制御回路
B7からの故障信号70を確認し、故障状態であれば制
御回路B7の故障表示信号94を出方する故障検出B 
B 7 sによ)構成される。
(Example) An example of the present invention is shown in FIG. The control circuit A6 and the control circuit B7 are multiplexed control circuits, and include a switching circuit 80 for switching these multiplexed control circuits, a power converter 2 whose operation is controlled by the control circuit, and this power converter 2. a current transformer A41 and a current transformer B42 that detect the input current of the power converter 2, a voltage detector A5J and a voltage detector B54 that detect the output voltage of the power converter 2, and the multiplexed control circuit A6. And, while the power converter 2 is being controlled by any one of the control circuits B7, the control circuit A
6 and detects that the control circuit B7 has failed, outputs a failure reset signal to all multiplexed control circuits, and
An automatic reset circuit 9 that cuts off the operating power of the control circuit for a short time after the failure reset signal is inputted to the control circuit that continues to fail; , a display circuit 81 that determines and displays a control circuit abnormality, and a selection circuit US that selects the control circuit that has recovered from failure when the control circuit A6 and control circuit B7 recover from failure due to the action of the automatic reset circuit 9. , a switching circuit 80 that switches the control circuit according to the selection signal of the selection circuit 8. Further, a detailed configuration of the automatic reset circuit 9 is shown in FIG. The automatic reset circuit 9 includes a fault reset signal generator 6I that receives a fault signal 60 from the control circuit A6 and outputs a fault reset signal 90 via an OR circuit 97, and a fault signal generator 6I that outputs a fault reset signal 90 via an OR circuit 97, and a fault signal from the control circuit B7. 7Q, the fault reset signal generator 71 outputs the fault reset signal 90t via the OR circuit 97, and upon completion of the fault reset signal 90, which is the output signal of the OR circuit 97, the control circuit A6
The power supply initialization signal generator 62 checks the fault signal 6θ from the circuit and outputs the power supply initialization signal 92 if it is in a fault state, and similarly, upon completion of the fault reset signal 9o, which is the output signal of the OR circuit 97, a power supply initialization signal generator 72 that checks the failure signal 70 from the control circuit B7 and outputs a power supply initialization signal 91 if the failure state occurs; and upon completion of the power supply initialization signal 92, the control circuit A failure detector A6j that checks the failure signal 5θ from A6 and outputs a failure indication signal 93 of the control circuit A6 if it is in a failure state; Failure detection B that checks the failure signal 70 from the circuit B7 and outputs a failure indication signal 94 of the control circuit B7 if it is in a failure state.
B 7 s).

以上の構成にょシ、片方の制御回路、例えば制御回路A
6が運転中に異常発生した場合、その故障信号60によ
り故障リセット信号発生器6ノから、多重化された制御
回路A6及び、制御回路B7に、故障リセット信号9o
が入力される。この故障リセット信号9o完了後、前記
自動リセット回路9では、制御回路A6及び、制御回路
B7が故障状態か制御可能状態かを電源イニシャライズ
信号発生器A62及び、電源イニシャライズ信号発生器
B72により判断し、故障状態の制御回路については、
その制御回路の操作′!ItRを短時間遮断する電源イ
ニシャライズ宿号(制#回路A6に対しては電源イニシ
ャライズ信号92、制御回路B7に対しては電源イニシ
ャライズ信号9ノ)を電源イニシャライズ信号発生器1
62及び、電源イニシャライズ信号発生器B72により
出力する。電源イニシャライズが実行された制御回路で
は、制御信号がすべて初期化されるため、部品のハード
的な故障以外は、すべての故障モードが解除され、電力
変換器2の運転制御が継続される。
In the above configuration, one control circuit, for example, control circuit A
6 when an abnormality occurs during operation, the fault signal 60 sends a fault reset signal 9o from the fault reset signal generator 6 to the multiplexed control circuit A6 and control circuit B7.
is input. After the failure reset signal 9o is completed, the automatic reset circuit 9 determines whether the control circuit A6 and the control circuit B7 are in a failure state or a controllable state using a power supply initialization signal generator A62 and a power supply initialization signal generator B72, For control circuits in fault condition,
Operation of that control circuit'! A power initialization signal (power initialization signal 92 for control circuit A6, power initialization signal 9 for control circuit B7) that interrupts ItR for a short time is sent to power initialization signal generator 1.
62 and a power supply initialization signal generator B72. In the control circuit in which the power supply initialization has been performed, all control signals are initialized, so that all failure modes are canceled except for a hardware failure of a component, and operation control of the power converter 2 is continued.

以上のように、本発明は以下の効果を得ることができる
As described above, the present invention can obtain the following effects.

(1) 多重化され六制御回路において、制御回路が異
常となっfc場合でも故障復帰を自動的に行える。
(1) In the six multiplexed control circuits, even if the control circuit becomes abnormal and fc occurs, failure recovery can be automatically performed.

(2)  自動的に故障復帰するため、多重化構成を最
大限保つことができ、信頼性の大幅な向上が実現できる
(2) Since failure recovery is automatic, the multiplexed configuration can be maintained to the maximum extent possible, and reliability can be significantly improved.

(3)  前記(2)項の効果により、本構成の制御装
置を適用したシステムの稼動率が大幅に向上する。
(3) Due to the effect of item (2) above, the operating rate of the system to which the control device of this configuration is applied is significantly improved.

(4)1つの制御回路の異常により、電力変換器の入力
電流及び、出力電圧に影響が発生し、多重化制御回路す
べてが故障検出しても、自動故障リセットすることによ
りミ力変換器の運転制御を継続することができる。
(4) Even if an abnormality in one control circuit affects the input current and output voltage of the power converter, and all multiplexed control circuits detect a failure, automatic failure reset will cause the power converter to Operation control can be continued.

[発明の効果] 本発明によ5.1つの制御対象に対して制御回路が多重
化され、常に1つの制御回路で制御対象を運転制御する
制御装置において、倒れの制御回路が故障しても、それ
ぞれの制御回路から出力される故障信号により、すべて
の制御回路に故障リセット信号または、電源イニシャラ
イズ信号を入力し、故障モードを自動的に解除するため
、多重化構成を常に確保でき、システム稼動率の高い、
高信頼性の多重化制御装置を提供できる。特に、制御対
象が多重化制御回路に対して共通な場合、1つの制御回
路の異常が制御対象の入出力に影響を及tzシ、その結
果、前記制御対像の7人出力量を検出している検出器す
べてが同時に異常信号を検出し、多重化制御回路すべて
が同時に異常となることがある。このような状態に於り
ても、前記故障リセット信号及び、電源イニシャライズ
信号により、制御対象の運転制御を継続できる。
[Effects of the Invention] According to the present invention, 5. In a control device in which control circuits are multiplexed for one control object and the operation of the control object is always controlled by one control circuit, even if the collapse control circuit fails, In response to the failure signal output from each control circuit, a failure reset signal or power supply initialization signal is input to all control circuits and the failure mode is automatically released, so a multiplexed configuration can always be ensured and system operation can be maintained. high rate,
A highly reliable multiplex control device can be provided. In particular, when the controlled object is common to multiplexed control circuits, an abnormality in one control circuit will affect the input/output of the controlled object, and as a result, the output amount of the seven control objects will be detected. All the detectors in the control circuit may simultaneously detect an abnormal signal, and all multiplex control circuits may become abnormal at the same time. Even in such a state, the operation control of the controlled object can be continued using the failure reset signal and the power supply initialization signal.

【図面の簡単な説明】[Brief explanation of the drawing]

@1図は本発明の一実施例を示す構成図、第2図は第1
図の自動リセット回路の詳細例を示すブロック図、第3
図は従来装置の構成図である。 !・・・交流電源、2・・・電力変換器、3・・・負荷
、4・・・基準設定器、6・・・制御回路、As7・・
・制御回路B、8・・・選択回路、9・・・自動リセッ
ト回路、41・・・変流器A142・・・変流器B、4
3.44・・・整流器、51h、51b、52g、52
b=抵抗器、53・・・電圧検出器A、54・・・電圧
検出器B160・・・故障信号A、70・・・故障信号
B、80・・・切り替え回路、81・・・表示回路、6
1・・・故障リセット信号発生器A、71・・・故障リ
セット信号発生器B、62・・・電源イニシャライズ信
号発生器A172・・・電源イニシャライズ信号発生器
B163・・・故障検出器A、73・・・故障検出器B
097・・・OR回路、90・・・故障リセット信号、
91・・・電源イニシャライズ信号A192・・・電源
イニシャライズ信号B、93・・・故障表示信号A19
4・・・故障表示信号B0第1図 1 第 2 図 第 図
@Figure 1 is a configuration diagram showing one embodiment of the present invention, and Figure 2 is the first embodiment.
A block diagram showing a detailed example of the automatic reset circuit in Figure 3.
The figure is a configuration diagram of a conventional device. ! ...AC power supply, 2...Power converter, 3...Load, 4...Reference setter, 6...Control circuit, As7...
・Control circuit B, 8... Selection circuit, 9... Automatic reset circuit, 41... Current transformer A142... Current transformer B, 4
3.44... Rectifier, 51h, 51b, 52g, 52
b=Resistor, 53... Voltage detector A, 54... Voltage detector B160... Failure signal A, 70... Failure signal B, 80... Switching circuit, 81... Display circuit ,6
1...Fault reset signal generator A, 71...Fault reset signal generator B, 62...Power initialization signal generator A172...Power initialization signal generator B163...Fault detector A, 73 ...fault detector B
097...OR circuit, 90...failure reset signal,
91...Power supply initialization signal A192...Power supply initialization signal B, 93...Failure display signal A19
4...Failure display signal B0 Figure 1 Figure 1 Figure 2 Figure

Claims (1)

【特許請求の範囲】[Claims] 多重化された制御回路と、これら多重化制御系を切り替
える切り替え回路と、前記制御回路により運転制御され
る制御対象と、この制御対象の動作量を検出する検出器
を有する多重化制御装置において、前記多重化された制
御系の何れか1つの制御回路、又は全ての制御回路によ
り制御対象を運転制御中、該制御回路が故障を検出した
ことを検出する第一の手段、この第一の手段の信号を受
けて多重化された全制御回路に故障リセット信号を出力
する第2の手段、前記故障リセット信号入力後故障復帰
した制御回路を選択する第3の手段、前記故障リセット
信号入力後尚故障継続している制御回路に対して制御回
路の操作電源を短時間遮断する第4の手段、この第4の
手段の動作完了後、尚制御回路が故障状態の時、制御回
路異常と判断する第5の手段を具備する事を特徴とする
多重化制御装置。
A multiplexed control device including multiplexed control circuits, a switching circuit for switching these multiplexed control systems, a controlled object whose operation is controlled by the control circuit, and a detector that detects the amount of operation of this controlled object, A first means for detecting that a control circuit has detected a failure during operation control of a controlled object by any one control circuit or all the control circuits in the multiplexed control system; a second means for outputting a fault reset signal to all multiplexed control circuits in response to the signal; a third means for selecting a control circuit that has recovered from a fault after inputting the fault reset signal; A fourth means of cutting off the operating power of the control circuit for a short period of time for a control circuit that continues to fail; after the operation of this fourth means is completed, if the control circuit is still in a failure state, it is determined that the control circuit is abnormal; A multiplex control device characterized by comprising a fifth means.
JP13885989A 1989-05-31 1989-05-31 Multiplex controller Expired - Lifetime JP2667512B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13885989A JP2667512B2 (en) 1989-05-31 1989-05-31 Multiplex controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13885989A JP2667512B2 (en) 1989-05-31 1989-05-31 Multiplex controller

Publications (2)

Publication Number Publication Date
JPH037068A true JPH037068A (en) 1991-01-14
JP2667512B2 JP2667512B2 (en) 1997-10-27

Family

ID=15231811

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13885989A Expired - Lifetime JP2667512B2 (en) 1989-05-31 1989-05-31 Multiplex controller

Country Status (1)

Country Link
JP (1) JP2667512B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020161945A1 (en) * 2019-02-05 2020-08-13 日立オートモティブシステムズ株式会社 Power conversion device
WO2022003812A1 (en) * 2020-06-30 2022-01-06 三菱電機株式会社 Power conversion device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020161945A1 (en) * 2019-02-05 2020-08-13 日立オートモティブシステムズ株式会社 Power conversion device
JP2020127291A (en) * 2019-02-05 2020-08-20 日立オートモティブシステムズ株式会社 Electric power conversion device
US11611292B2 (en) 2019-02-05 2023-03-21 Hitachi Astemo, Ltd. Power conversion device
WO2022003812A1 (en) * 2020-06-30 2022-01-06 三菱電機株式会社 Power conversion device

Also Published As

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