JPH09322524A - Gate controller of thyristor bulb - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make one gate pulse generator in order continuously operate even if the other gate pulse generator gets out of order, by a method in which two sets of pulse generating means, current application period signal abnormality detecting means and gate pulse stopping means are respectively provided. SOLUTION: The output of an AND circuit 3A is inputted to a one-shot circuit 4A through an AND circuit 43A. The output of a flip-flop circuit 42A of a current application period signal abnormality detection circuit 40A is connected to the other input terminal of the AND circuit 43A through a reverse circuit 44A. The AND circuit 43A has a function which stops a gate pulse by which the supply of a light ignition signal to a thyristor bulb is stopped in accordance with the output of the current application period signal abnormality detection circuit 40A. With this constitution, the operation of a gate pulse generator out of order is stopped and thyristor bulb can continue operation by the other gate pulse generator in order.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate control device for a thyristor valve, which supplies a gate pulse to a thyristor valve constituted by connecting a plurality of thyristors used for DC power transmission or the like in series or in parallel.

[0002]

2. Description of the Related Art A gate control device for a thyristor valve connected to an electric power system such as a DC power transmission system may be constructed in a normal dual system because a high reliability is required of the system.
Further, when the thyristor valve is an optical trigger thyristor (hereinafter simply referred to as an optical thyristor), the output to the thyristor valve of the gate control device uses a narrow gate pulse from the viewpoint of the life of the light source, or an electric trigger thyristor. In some cases, narrow gate pulses are often used from the viewpoint of saving power on the high potential side.

FIG. 7 is a block diagram showing an embodiment of a conventional dual gate control device for a thyristor valve. In the figure, only the A system is shown and the B system is omitted, but the one having B added instead of the subscript A is the B system gate pulse generator, and therefore has the same configuration as the A system gate pulse generator. Therefore, the following description will be given mainly with reference to the A-system gate pulse generator.

The A-system gate pulse generator 1A includes a flip-flop circuit 2A, an AND circuit 3A, and a one-shot circuit 4.
A, amplifier circuit 5A, switching element 6A, optical thyristor trigger LEDs 7A-1 to 7A-N, DC power supply 9
A, a pulse generating means including a resistor 10A, an on-delay circuit 17A, a control circuit 19A, opto-electrical signal conversion circuits 32A-1 to 32A-N, an opto-electrical signal conversion circuit 33A, and an OR circuit 34A. There is.

The thyristor bulb 25 comprises N optical thyristors 26-1 to 26-N, voltage dividing resistors 27-1 to 27-N,
It is composed of forward voltage detectors 28-1 to 28-N, reverse voltage detector 29, and the like.

The forward voltage detection circuits 28-1 to 28-N in the A-system gate pulse generator 1A, the B-system gate pulse generator 1B and the thyristor valve 25 are lighted by the two-branch light guides 35-1 to 35-N. Electric signal conversion circuit 32A-1
32A-N and B system optical-electrical signal conversion circuit 32B-1
~ 32B-N. Further, the reverse voltage detector 2
Reference numeral 9 is connected to the optical-electrical signal conversion circuit 33A and the B-system optical-electrical signal conversion circuit 33B by a two-branch light guide 36. Further, the optical thyristor trigger LEDs 7A-1 to 7A-N of the A-system gate pulse generator 1A and the optical thyristor trigger LED 7B of the B-system gate pulse generator 1B.
-1 to 7B-N are 2-branch light guides 30-1 to 3 respectively
The optical thyristor 2 in the thyristor bulb 25 is 0-N.
6-1 to 26-N.

Optical thyristor 26 of thyristor bulb 25
-26-N when forward voltage is applied to forward voltage detector 2
The forward voltage signal is detected by 8-1 to 28-N. The detected forward voltage signal is the light guide 35-1 as an optical signal.
Through 35-N, optical-electrical signal conversion circuit 32A-1
32A-N. Opto-electrical signal conversion circuit 32A
The forward voltage signal input to the -1 to 32A-N is the OR circuit 3
4A, and is output as a forward voltage signal FV of the thyristor valve 25.

On the other hand, the phase control signal PHS, which is output from the control circuit 19A and indicates the conduction period of the thyristor valve 25, is output.
Is input to the flip-flop 2A. The thyristor valve energization period command signal (hereinafter simply referred to as PHS ′) and the forward voltage signal FV, which are the outputs of the flip-flop 2A, are A
It is input to the ND circuit 3A, and when the AND condition is satisfied, its output is input to the one-shot circuit 4A. The one-shot circuit 4A outputs a pulse signal, the amplifier circuit 5A amplifies the signal, and outputs this signal as a firing command to drive the switching element 6A.
When the switching element 6A is turned on, the optical thyristor trigger LEDs 7A-1 to 7AN generate an optical signal by the current from the DC power source 9A, and the two-branch light guides 30-1 to 30-3.
Optical thyristor 26 as an optical gate pulse through 0-N
-1 to 26-N, the thyristor valve 25 is turned on.

When the optical thyristors 26-1 to 26-N are ignited, the forward voltage applied to the optical thyristors 26-1 to 26-N becomes almost 0, so that the condition of the AND circuit 3A is not satisfied. The optical gate pulse is no longer output. That is,
When the forward voltage is applied to the thyristor bulb 25, PHS 'becomes "1", or when the forward voltage is applied to the thyristor bulb 25 while PHS' is "1", the optical gate A pulse is output and the thyristor valve 25 is ignited.

Optical thyristor 26 of thyristor bulb 25
When a reverse voltage is applied to -1 to 26-N, the optical thyristor 2
6-1 to 26-N are extinguished, and by the reverse voltage detector 29,
The reverse voltage is detected and transmitted as an optical signal by the light guide 36 to the opto-electrical signal conversion circuit 33A of the photoelectric converter 31A. The reverse voltage signal RV converted into an electric signal by the opto-electrical signal conversion circuit 33A is input to the on-delay circuit 17A as the reverse voltage signal RV of the thyristor valve 25.

When the width of the reverse voltage signal RV is longer than the time period T1 of the on-delay circuit 17A while PHS is "0", the output of the on-delay circuit 17A becomes "1" and the flip-flop 2A is reset. The output PHS 'is set to "0". When PHS 'becomes "0", the condition of the AND circuit 3A is not satisfied even if the forward voltage signal FV becomes "1", so that the optical gate pulse is not generated. Therefore, the optical thyristors 26-1 to 26-N do not fire and remain in this state until the PHS signal from the control circuit 19A becomes "1" in the next cycle. The time delay T of the on-delay circuit 17A
1 is usually 400 μs to 1000 μs and is determined in consideration of the turn-off time of the optical thyristors 26-1 to 26-N.

As mentioned above, the gate pulse generator is
With the dual system of A and 1B, even if the optical gate pulse from one gate pulse generator disappears, the operation can be continued if the other gate pulse generator is normal. The reliability can be improved.

[0013]

However, the conventional gate control device having such a structure has the following problems. This will be described with reference to FIG. 7 and FIG. 8 showing the time chart.

Due to an abnormality in the circuit of the A-system gate pulse generator 1A (for example, failure of the flip-flop 2A) due to some cause, the flip-flop 2 after time t0.
Suppose PHS'-A, which is the output of A, remains at "1". When this happens, the thyristor valve 2
When a forward voltage is applied to 5 and the forward voltage signal FV-A is input to the AND circuit 3A, the AND condition is satisfied immediately, and PH
Irrespective of the S signal, that is, the optical gate pulse GP-A is generated while the phase control does not work and the thyristor valve 25 is ignited at time t1. When the thyristor valve 25 is ignited, the forward voltage disappears. On the other hand, in the B system, after time t1, for example, at time t2, even if PHS'-B is "1", the forward voltage signal F
Since V-B is "0", the AND condition of the B-system AND circuit 3B is not satisfied and the optical gate pulse GP-B is not generated.

In the DC power transmission system, the thyristor valve 25 continues to be turned on by the A-system gate pulse generator 1A in an uncontrolled state, so that the operation as it is will cause an unbalance of three phases and an increase in harmonic current with respect to the AC system. Therefore, it is stopped by a protection relay of the main circuit such as a commercial frequency intrusion protection relay (not shown).

That is, even if a dual system is constructed as the gate control device, there is a problem that the motion of the abnormal system spreads to the sound system and the system is stopped. The object of the present invention is to prevent the gate pulse generator from failing to protect the other gate pulse generator even if the other gate pulse generator cannot normally generate a gate due to the failure of the other gate pulse generator. A sound gate pulse generator is to provide a gate control device of a thyristor valve which does not stop as a system capable of continuing operation.

[0017]

In order to achieve the above object, a gate control device for a thyristor valve according to a first aspect of the present invention comprises an energization period command signal for the thyristor valve and a forward voltage signal for the thyristor valve. Pulse generating means for supplying a light ignition signal to the thyristor valve under an AND condition, energizing period signal abnormality detecting means for detecting that the energizing period command signal continues for a predetermined time period or longer, and energizing period signal abnormality detecting means And a gate pulse stopping means for stopping the supply of the light ignition signal to the thyristor valve by the output of the above, and two sets of these means are provided to form a dual system.

According to another aspect of the present invention, there is provided a gate control device for a thyristor valve, wherein a light ignition signal is sent to the thyristor valve under an AND condition between a thyristor valve energization period command signal and a thyristor valve forward voltage signal. For supplying the pulse signal to the thyristor valve by the output of the energization period signal abnormality detection means for detecting that the energization period command signal has continued for a first predetermined time period or longer. Gate pulse stopping means for stopping the supply of the ignition signal, monitor means for generating a pulse signal synchronized with the output of the pulse generating means, and longer than the first predetermined time period after the pulse signal of the monitor means disappears. Gate pulse open phase detecting means for generating a gate pulse open phase signal when the pulse signal is not generated for the second predetermined time period or longer. And the gate pulse phase loss detection means,
The present invention is provided with a protection unit that receives an output signal from the energization period abnormality detection unit or the like and determines whether or not to stop the operation of the thyristor valve, and two sets of each of these units are provided to constitute a dual system. And

Further, a gate control device for a thyristor valve according to the invention described in claim 3 transmits / receives a signal to / from the protection system according to claim 2 between itself and another system, thereby It is characterized by having a function to judge whether to stop or continue the operation of the system in consideration of the state of the system.

Furthermore, in the gate control device for a thyristor valve according to the invention as defined in claim 4, the bypass period command signal for the thyristor valve or the thyristor valve is added to the electrical period signal abnormality detecting means according to claim 2. It is characterized in that an interlock means for locking the operation of the energization period signal abnormality detection means is provided on condition that the voltage of the AC system is equal to or lower than a predetermined value.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION The invention described in claim 1 will be described below with reference to FIG. 1 in which the same reference numerals are given to those having the same functions as in FIG. It should be noted that the A-based gating generator 1A
Since the B-system gate pulse generator 1B (not shown) has the same structure, the B-system gate pulse generator is omitted as in FIG.

The output of the flip-flop 2A is input to the AND circuit 3A and, at the same time, to the PHS 'continuous abnormality detecting circuit 40A (hereinafter, referred to as energization period signal abnormality detecting circuit). The energization period signal abnormality detection circuit 40A has a time limit T3.
ON delay circuit 41A and flip-flop circuit 42
It is composed of A.

Here, the time limit T3 of the on-delay circuit 41A
Is, for example, a commutation failure of the thyristor valve 25 may occur due to a transient voltage drop of the AC system.
In such a case, T3 is set to a time period longer than 1.5 times the cycle of the frequency of the AC system so that the energization period signal abnormality detection circuit 40A does not perform unnecessary operation.

The output of the AND circuit 3A is the AND circuit 43A.
Is input to the one-shot circuit 4A via. Also AND
The other input of the circuit 43A is connected to the output of the flip-flop circuit 42A of the conduction period signal abnormality detection circuit 40A via the inverting circuit 44A. The AND circuit 43A is
It has a function of stopping the gate pulse for stopping the supply of the light ignition signal to the thyristor valve by the output of the energization period signal abnormality detection circuit 40A.

Next, the gate of the thyristor valve shown in FIG.
The operation of the control device will be described with reference to the time chart of FIG. In FIG. 2, GP-A (GP-B), aA
(AB), bA (bB), PF-A (PF-B), cA
(CB) and PHSF-A (PHSF-B) are waveforms for explaining the operation of the embodiment shown in FIGS.

The PHS'-A output from the flip-flop circuit 2A becomes "1" after time t0 due to an abnormality in the circuit of the A-system gate pulse generator 1A (for example, failure of the flip-flop 2A) due to some cause. Suppose that it has been left as. When this happens, a forward voltage is applied to the thyristor valve 25, and the forward voltage signal FV-A becomes AN.
As soon as it is input to the D circuit 3A, the AND condition is satisfied,
An optical gate pulse GPM-A is generated irrespective of the phase control signal PHS (in a state where the phase control does not work) to fire the thyristor valve 25 at time t1. When the thyristor valve 25 is ignited, the forward voltage disappears.

On the other hand, the B system is, for example, time t2 after time t1.
Since the forward voltage signal FV-B is "0" even if the output PHS'-B of the flip-flop circuit 2B is "1", AN
The AND condition of the D circuit 3B is not satisfied, and the optical gate pulse G
P-B does not occur.

However, P of the A-system gate pulse generator 1A
Time t when the period during which HS'-A is "1" is T3 or more
In 3, the output CA of the on-delay circuit 41A is "1".
Then, the flip-flop circuit 42A is set and the output PHSF-A of the flip-flop circuit 42A is set to "1". This signal is input to the protection circuit 18A and appropriately protected, and at the same time, the output P of the flip-flop circuit 42A is output.
HSF-A is input to the inverting circuit 44A and is input to the inverting circuit 44A.
Output becomes "0". The output of the inverting circuit 44A is AND
Since one input of the circuit 43A is input, the output of the AND circuit 43A becomes "0" regardless of what signal is input to the other input.

After time t3, LE for optical thyristor trigger
D7A-1 to 7A-N do not emit light. Therefore, at time t4 when the forward voltage is applied to the thyristor valve 25, the optical gate pulse is not output from the A system gate pulse generator 1A and the thyristor valve 25 is not turned on.

At time t5, the phase control signal PHS-B, which is output from the control circuit 19B and indicates the conduction period of the thyristor valve 25, is input to the flip-flop circuit 2B. Output PHS'-B of flip-flop circuit 2B
And the forward voltage signal FV-B are input to the AND circuit 3B, and when the AND condition is satisfied, the output is input to the one-shot circuit 4B via the AND circuit 43B.

The one-shot circuit 4B outputs a pulse signal, the amplifier circuit 5B amplifies the signal, and outputs this signal as an ignition command to drive the switching element 6B. When the switching element 6B is turned on, the optical thyristor trigger LEDs 7B-1 to 7B-N generate an optical signal by the current from the DC power source 9B and pass through the two-branch light guides 30-1 to 30N as an optical gate pulse to form an optical thyristor 26-1. 26-N, the optical thyristors 26-1 to 26-N are ignited, that is, the thyristor valve 25 is turned on at a normal timing, so that the operation can be continued and the system does not stop.

In the above description, the A system gate pulse generator 1
Although the case of the PHS'-A abnormality of A has been described, the same applies to the abnormality of the B-system gate pulse generator 1B.
Next, a gate control device for a thyristor valve according to the second and third aspects of the present invention will be described with reference to FIG. 3 in which the same parts as those in FIG.

The embodiment shown in FIG. 3 differs from the embodiment shown in FIG. 1 in that a monitor means for generating a pulse signal GPM-A synchronized with the optical gate pulse and a predetermined time period after the pulse signal GPM-A of the monitor means disappears. When the pulse signal is not generated for (T2) or more, the gate pulse open phase detecting means 13A for generating the gate pulse open phase signal PF-A is added.

The monitor means is an LE for optical thyristor trigger.
An optical gate pulse monitor LED 8A connected in series to D7A-1 to 7A-N, and a light guide 11A for transmitting an optical signal of the optical gate pulse monitor LED 8A,
The optical / electrical signal conversion circuit 12A converts the transmitted optical signal into an electric signal.

Further, the gate pulse open phase detecting means 13A is
An inversion circuit 14A to which the output signal of the opto-electrical signal conversion circuit 12A is applied, an on-delay circuit 15 to which the output signal of this inversion circuit 14A is applied, and an on-delay circuit 15
It comprises a flip-flop circuit 16A set by

Here, the time limit T3 of the on-delay circuit 41A
Is set shorter than the time limit T2 of the on-delay circuit 15A. In addition, since the commutation failure of the thyristor valve 25 may occur due to a transient voltage drop of the AC system, the cycle of the frequency of the AC system is controlled so that the energization period signal abnormality detection circuit 40A does not operate unnecessarily at such time. 1.5
Set T3 for a time period longer than double.

Next, the operation of the embodiment of FIG. 3 will be described with reference to the time chart of FIG. It is assumed that PHS'-A has a continuous "1" failure at time t0, and at time t3 when this period is T3 or more, the output CA of the on-delay circuit 41A becomes "1" and the flip-flop circuit 42A is set. Output of the circuit 42A PHSF-A
Is “1”. This signal is input to the protection circuit 18A and appropriately protected, and is also input to the inverting circuit 44A and the output of the inverting circuit 44A becomes "0". Inversion circuit 44
Since the output of A is input to one input of the AND circuit 43A, the output of the AND circuit 43A becomes "0" regardless of what signal is input to the other input.

After time t3, LE for optical thyristor trigger
D7A-1 to 7A-N do not emit light. Therefore, at time t4 when the forward voltage is applied to the thyristor valve 25, the optical gate pulse is not output from the A system gate pulse generator 1A and the thyristor valve 25 is not turned on.

At time t5, the phase control signal PHS-B output from the control circuit 19B, which indicates the conduction period of the thyristor valve 25, is input to the flip-flop circuit 2B. Output PHS'-B of flip-flop circuit 2B
And the forward voltage signal FV-B are input to the AND circuit 3B, and when the AND condition is satisfied, the output is input to the one-shot circuit 4B via the AND circuit 43B.

The one-shot circuit 4B outputs a pulse signal, the amplifier circuit 5B amplifies the signal, and outputs this signal as a firing command to drive the switching element 6B. When the switching element 6B is turned on, the optical thyristor trigger LEDs 7B-1 to 7B-N generate an optical signal by the current from the DC power source 9B and pass through the two-branch light guides 30-1 to 30N as an optical gate pulse to form an optical thyristor 26-1. 26-N, the optical thyristors 26-1 to 26-N are fired, that is, the thyristor bulb 25 is turned on at a normal timing.

The gate pulse open phase detection circuit 13B has a time limit T
An optical gate pulse is output before reaching 2, and at time t5 G
Since PM-B becomes "1" and aB becomes "0", the on-delay circuit 15B does not time up, so the flip-flop circuit 16B is not set and PF-B remains "0". Therefore, after time t5, the thyristor valve 2
In No. 5, the optical gate pulse from the B-system gate pulse generator 1B turns on at a normal timing, so that the operation can be continued without stopping the system.

In this way, the energization period signal abnormality detection circuit 4
When 0A operates, the normal B is the same as in the embodiment of FIG.
Operation can be continued with the system gate pulse generator 1B. In the above description, the case of the PHS'-A abnormality of the A system gate pulse generator 1A has been described, but the same applies to the B system gate pulse generator 1B abnormality.

On the other hand, the switching element 6A, the optical thyristor trigger LEDs 7A-1 to 7A-N, the optical gate pulse monitor LED 8, the DC power source 9A, and the current adjusting resistor 10
It is assumed that the optical gate pulse disappears due to the open circuit failure of the series circuit composed of A.

When such a failure occurs, the operation is continued by the sound B system gate pulse generator 1B,
The system never stops. On the side of the failed A-system gate pulse generator 1A, the on-delay circuit 15A starts time-up from the time when the optical gate pulse GPM-A disappears, and the flip-flop circuit 16A is set and the gate pulse is missing at the time when the time T2 has elapsed. The phase signal PF-A is added to the protection circuit 18A, appropriate protection interlocking is performed, and the A system gate pulse generator 1A is stopped.

The fact that the A system gate pulse generator 1A has stopped operating is transmitted to the protection circuit 18B on the B system gate pulse generator 1B side, and the B system gate pulse generator 1B is also provided.
The fact that the side has stopped operating is also transmitted to the protection circuit 18A on the side of the A-system gate pulse generator 1A.

Thus, if a failure also occurs on the B system gate pulse generator 1B side during the operation stop of the A system gate pulse generator 1A, a procedure for stopping the entire system or an appropriate procedure therefor is taken. Protection interlocking can be performed.

Next, another embodiment of the invention described in claim 3 will be described with reference to FIG. 4 in which the same parts as those in FIG. The embodiment of FIG. 4 is a relay switch in which the portion of FIG. 3 where the generation of the optical gate pulse to the thyristor valve 25 is performed by the logic circuit is connected in parallel with the LEDs 7A-1 to 7A-N for the optical thyristor It has been replaced.

The output of the AND circuit 3A is input to the one-shot circuit 4A. The amplifier circuit 45A drives the relay circuit 46A when the input becomes "1". Relay circuit 4
A contact point of 6A is LED 7A-1 for optical thyristor trigger
7A-N anode side is connected to common potential.

Here, the operation of the A system will be described, but B
The system is similar. PHSF-A is "0" when the energization period signal abnormality detection circuit 40A does not detect an abnormality. Therefore, the output of the amplifier circuit 45A is also "0", and the contact of the relay circuit 46A is open. Therefore, a current flows through the optical thyristor trigger LEDs 7A-1 to 7A-N in accordance with the ON operation of the switching element 6A, and a light gate pulse is given to the thyristor valve 25 to operate normally.

Next, the operation at the time of abnormality will be described with reference to the time chart of FIG. It is assumed that PHS'-A has a continuous "1" failure at time t0, and the output C of the on-delay circuit 41A at time t3 when this period becomes T3 or more.
A becomes "1" and the flip-flop circuit 42A is set to set the output PHSF-A of the flip-flop circuit 42A to "1". This signal is input to the protection circuit 18A and appropriately protected, and at the same time, the relay circuit 46A is driven via the amplifier circuit 45A, and the contact of the relay circuit 46A is closed. Therefore, the LEDs 7A-1 to 7A-N for the optical thyristor trigger are short-circuited between the anode and the cathode, so that even if the switching element 6A is driven, the current flows through the contact of the relay circuit 46A, and the LED for the optical thyristor trigger L
No current flows through the EDs 7A-1 to 7A-N, and no optical gate pulse is output.

After time t3, LE for optical thyristor trigger
D7A-1 to 7A-N do not emit light. Therefore, at time t4 when the forward voltage is applied to the thyristor valve 25, the optical gate pulse is not output from the A system gate pulse generator 1A and the thyristor valve 25 is not turned on. The subsequent operation is
This is similar to the embodiment of FIG.

Next, still another embodiment of the present invention will be described with reference to FIG. 5 in which the same parts as those in FIG. 3 are designated by the same reference numerals. In the embodiment of FIG. 5, the portion where the generation of the optical gate pulse to the thyristor bulb 25 is performed by the logic circuit in FIG.
It is replaced with a relay switch connected in series with A-1 to 7AN. The output of the AND circuit 3A is input to the one-shot circuit 4A. The inverting amplifier circuit 47A drives the relay circuit 46A when the input becomes "0".
A contact of relay circuit 46A is LE for optical thyristor trigger
Anode side of D7A-1 to 7A-N and current adjusting resistor 10
Connected between A.

PHSF-A is "0" when the energization period signal abnormality detection circuit 40A detects no abnormality.
Therefore, the output of the inverting amplifier circuit 47A is "1", and the contact of the relay circuit 46A is closed. Therefore, a current flows through the optical thyristor trigger LEDs 7A-1 to 7A-N in accordance with the ON operation of the switching element 6A, and a light gate pulse is given to the thyristor valve 25 to operate normally.

PHS'-A has a continuous "1" failure,
When this period becomes T3 or more, the output CA of the on-delay circuit 41A becomes "1" and the flip-flop circuit 42A is set to set the output PHSF-A of the flip-flop circuit 42A to "1". This signal is input to the protection circuit 18A for proper protection, and the output of the inverting circuit 47A becomes "0", and the contact of the relay circuit 46A opens. Therefore, the LEDs 7A-1 to 7AN for the optical thyristor trigger are disconnected from the DC power source 9A and the LEDs for the optical thyristor trigger are separated.
Although no current flows through 7A-1 to 7A-N and no optical gate pulse is output, the operation is continued by the normal B-system gate pulse generator 1B, as described above.

Next, an embodiment of the invention described in claim 4 will be described with reference to FIG. 6 in which elements having the same functions as those in FIG. In the embodiment of FIG. 6, a lock circuit including a NOR circuit 48A and an AND circuit 49A is provided in the energization period signal abnormality detection circuit 40A in FIG.

The bypass pair command signal BPP output from the control circuit 19A is input to the NOR circuit 48A.
Further, the AC voltage drop signal 27 which becomes "1" when the AC voltage applied to the thyristor valve 25 becomes a predetermined value or less is also output from the control circuit 18A and input to the NOR circuit 48A. The output of the NOR circuit 48A is input to the AND circuit 49A. The output signal PHS 'of the flip-flop circuit 2A is input to the other input of the AND circuit 49A.
The output of the AND circuit 49A is the energization period signal abnormality detection circuit 4
It is connected to the on-delay circuit 41A in 0A.

The operation of the A system will be described below, but the same applies to the B system. Since the thyristor valve 25 normally has a conduction width of 120 degrees, the width of the output PHS of the control circuit 19A is also 1
It is 20 degrees.

However, there is an operation in which the thyristor valves connected to the same AC input, called a bypass pair, are simultaneously energized when the device is started or stopped. Such bypass pair operation may be on the order of seconds from several tens of ms, and therefore PHS and PHS 'may also have a width of several tens ms to several seconds. In such a case, in the above-described embodiment, the energization period signal abnormality detection circuit 40A may cause an unnecessary operation and stop the optical gate pulse.

Therefore, when the bypass pair operation is performed, the BPP output from the control circuit 19A becomes "1" so that the output of the NOR circuit 48A becomes "0" and the output of the AND circuit 49A also becomes "0". Therefore, since the input of the on-delay circuit 41A is "0" regardless of PHS ', the energization period signal abnormality detection circuits 40A and 40B do not operate unnecessarily during the bypass pair operation.

When an AC system accident occurs, it may take a long time to recover from the accident and the AC voltage applied to the thyristor valve 25 may drop, or the AC voltage may not be applied at all. In such a case, since the margin angle of the thyristor valve 25 is insufficient, the signal width of the reverse voltage signal RV becomes T1 or less, the output of the on-delay circuit 17A does not become "1", and the flip-flop circuit 2A cannot be reset. is there. In such a case, in the above-described embodiment, the energization period signal abnormality detection circuit 40A may cause an unnecessary operation and stop the optical gate pulse. Therefore, when the AC voltage applied to the thyristor valve 25 drops or is not applied at all, the AC voltage drop signal 27 output from the control circuit 19A becomes "1", so that the output of the NOR circuit 48A is " The output of the AND circuit 49A also becomes "0". Therefore, since the input of the on-delay circuit 41A is "0" regardless of the output signal PHS 'of the flip-flop circuit 2A, the energization period signal abnormality detection circuit 40A lowers the AC voltage applied to the thyristor valve 25, or There is no unnecessary operation when no voltage is applied.

[0061]

As described above, according to the invention described in claim 1, in the gate control device of the thyristor valve constituted by the dual gate pulse generator, the energization of one gate pulse generator is performed. In the failure mode where the forward voltage signal of the thyristor valve becomes abnormal due to the continuous abnormality of the period signal and the other gate pulse generator cannot generate normally, the faulty gate pulse generator is stopped and the other healthy gate pulse generator is used. It is possible to provide a gate control device for a thyristor valve capable of continuing the operation of the thyristor valve.

According to the invention of claim 2, in addition to the effect of the invention of claim 1, even if a gate pulse open phase failure occurs, the failed gate pulse generator is stopped, and It is possible to provide a gate control device for a thyristor valve capable of continuing the operation of the thyristor valve by using the sound gate pulse generator.

Furthermore, according to the invention of claim 3, in addition to the effects of the inventions of claims 1 and 2, gate control of a thyristor valve constituted by a dual-system gate pulse generator. The device can be used effectively.

Furthermore, according to the invention of claim 4,
In addition to the effects of the first and second aspects of the present invention, the gate pulse generator is unnecessarily used even when the bypass pair operation is performed or the AC voltage applied to the thyristor valve is reduced or is not applied at all. It is possible to provide a gate control device for a thyristor valve that does not stop the operation.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the invention described in claim 1.

FIG. 2 is a time chart for explaining the operation of FIG.

FIG. 3 is a configuration diagram showing an embodiment of the invention described in claims 2 and 3;

FIG. 4 is a configuration diagram showing another embodiment of the invention according to claim 3;

FIG. 5 is a configuration diagram showing still another embodiment of the invention according to claim 3;

FIG. 6 is a configuration diagram showing an embodiment of the invention described in claim 4;

FIG. 7 is a configuration diagram of a gate control device for a conventional thyristor valve.

FIG. 8 is a time chart for explaining the operation of FIG.

[Explanation of symbols]

 1A ... A system gate pulse generator 1B ... B system gate pulse generator 2A, 2B ... Flip-flop 3A, 3B ... AND circuit 4A, 4B ... One shot circuit 5A, 5B ... Amplifier circuit 6A, 6B ... Switching element 7A-1 ~ 7A-N ... LED for optical thyristor trigger 7B-1 ~ 7B-N ... LED for optical thyristor trigger 8A, 8B ... LED for optical gate pulse monitor 9A, 9B ... DC power supply 10A, 10B ... Current adjusting resistor 11A, 11B ... Light guides 12A, 12B ... Opto-electric signal conversion circuits 13A, 13B ... Gate pulse open phase detection circuits 14A, 14B ... One-shot circuits 15A, 15B ... Inversion circuits 16A, 16B ... Flip-flop circuits 17A, 17B ... On-delay circuit 18A , 18B ... protection circuit 19A, 19B ... control circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication H02M 7/155 8726-5H H02M 7/155 C

Claims (4)

[Claims] 1. A pulse generating means for supplying a light ignition signal to the thyristor valve under an AND condition between a thyristor valve energization period command signal and a thyristor valve forward voltage signal, and the energization period command signal having a predetermined time or more. An energization period signal abnormality detecting means for detecting continuation, a gate pulse stopping means for stopping the supply of the light ignition signal to the thyristor valve by the output of the energization period signal abnormality detecting means, and these means respectively A gate control device for a thyristor valve, which is configured as a set and configured as a dual system. 2. A pulse generating means for supplying a light ignition signal to the thyristor valve under an AND condition of an energization period command signal of the thyristor valve and a forward voltage signal of the thyristor valve, and the energization period command signal is a first signal. An energization period signal abnormality detecting means for detecting continuation for a predetermined time or more, a gate pulse stopping means for stopping the supply of the light ignition signal to the thyristor valve by the output of the energization period signal abnormality detecting means, and the pulse generation Monitor means for generating a pulse signal synchronized with the output of the means, and the first means after the pulse signal of the monitor means disappears
Gate pulse open phase detection means for generating a gate pulse open phase signal when a pulse signal is not generated for a second predetermined time longer than the predetermined time limit, the gate pulse open phase detection means, and the energization period abnormality detection. A thyristor valve characterized by comprising a protection means for judging whether or not to stop the operation of the thyristor valve by receiving an output signal from the means, etc. Gate control device. 3. The protection means exchanges signals between the own system and the other system to judge whether to stop or continue the operation of the system in consideration of the states of the own system and the other system. The gate control device for the thyristor valve according to claim 2. 4. The energization period signal abnormality detection means operates on the condition that the bypass pair command signal of the thyristor valve or the voltage of the AC system applied to the thyristor valve is equal to or less than a predetermined value. The gate control device for a thyristor valve according to claim 2, further comprising an interlock means for locking the operation.