JPH0369253U - - Google Patents
Info
- Publication number
- JPH0369253U JPH0369253U JP1989131169U JP13116989U JPH0369253U JP H0369253 U JPH0369253 U JP H0369253U JP 1989131169 U JP1989131169 U JP 1989131169U JP 13116989 U JP13116989 U JP 13116989U JP H0369253 U JPH0369253 U JP H0369253U
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- substrate
- capacitors
- dielectric film
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
第１図は本考案の一実施例を示す断面図、第２
図は典型的なＤＲＡＭの１記憶素子の回路構成を
示す回路図、第３図及び第４図は各々従来例を示
す断面図である。
１……基板、２……第１誘電体膜、４……第１
対向電極、５……第２誘電体膜、７……第２対向
電極、８ａ及び８ｂ……キヤパシタ、１５……ト
ランジスタ。
Fig. 1 is a sectional view showing one embodiment of the present invention;
The figure is a circuit diagram showing the circuit configuration of one storage element of a typical DRAM, and FIGS. 3 and 4 are cross-sectional views each showing a conventional example. 1...Substrate, 2...First dielectric film, 4...First
Counter electrode, 5... Second dielectric film, 7... Second counter electrode, 8a and 8b... Capacitor, 15... Transistor.
Claims (1)
膜を挟んで複数の対向電極を積層して複数のキヤ
パシタを形成すると共に、最上位の対向電極上に
絶縁膜を形成してこの絶縁膜上に多結晶シリコン
からなるＭＯＳトランジスタを形成し、上記キヤ
パシタの各々の一方の電極を上記トランジスタに
接続し、他方の電極を上記基板と同電位にするこ
とを特徴とする半導体記憶装置。 On the dielectric film formed on the surface of the substrate, a plurality of counter electrodes are stacked with the dielectric film in between to form a plurality of capacitors, and an insulating film is formed on the uppermost counter electrode to achieve this insulation. A semiconductor memory device characterized in that a MOS transistor made of polycrystalline silicon is formed on a film, one electrode of each of the capacitors is connected to the transistor, and the other electrode is set to the same potential as the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989131169U JPH0369253U (en) | 1989-11-10 | 1989-11-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989131169U JPH0369253U (en) | 1989-11-10 | 1989-11-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0369253U true JPH0369253U (en) | 1991-07-09 |
Family
ID=31678692
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989131169U Pending JPH0369253U (en) | 1989-11-10 | 1989-11-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0369253U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015079974A (en) * | 2010-04-09 | 2015-04-23 | 株式会社半導体エネルギー研究所 | Semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60236261A (en) * | 1984-04-25 | 1985-11-25 | シーメンス、アクチエンゲゼルシヤフト | 1-transistor memory cell and method of producing same |
| JPS614271A (en) * | 1984-06-14 | 1986-01-10 | インタ−ナシヨナル ビジネス マシ−ンズ コ−ポレ−シヨン | Memory cell |
-
1989
- 1989-11-10 JP JP1989131169U patent/JPH0369253U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60236261A (en) * | 1984-04-25 | 1985-11-25 | シーメンス、アクチエンゲゼルシヤフト | 1-transistor memory cell and method of producing same |
| JPS614271A (en) * | 1984-06-14 | 1986-01-10 | インタ−ナシヨナル ビジネス マシ−ンズ コ−ポレ−シヨン | Memory cell |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2015079974A (en) * | 2010-04-09 | 2015-04-23 | 株式会社半導体エネルギー研究所 | Semiconductor device |
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