JPH036923A - Data transmission equipment - Google Patents

Data transmission equipment

Info

Publication number
JPH036923A
JPH036923A JP1140742A JP14074289A JPH036923A JP H036923 A JPH036923 A JP H036923A JP 1140742 A JP1140742 A JP 1140742A JP 14074289 A JP14074289 A JP 14074289A JP H036923 A JPH036923 A JP H036923A
Authority
JP
Japan
Prior art keywords
low frequency
bit
data
circuit
main information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1140742A
Other languages
Japanese (ja)
Inventor
Mitsugi Tanaka
貢 田中
Motoichi Kashida
樫田 素一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP1140742A priority Critical patent/JPH036923A/en
Publication of JPH036923A publication Critical patent/JPH036923A/en
Pending legal-status Critical Current

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  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To form a transmission data whose low frequency band is effectively suppressed by providing a 1st low frequency suppression means suppressing a low frequency band of main information, a 2nd low frequency suppression means suppressing a low frequency band of sub information, and an output means synthesizing and outputting outputs of the 1st and 2nd low frequency suppression means. CONSTITUTION:A mapping coding circuit 12 applies mapping coding to a main information data inputted from an input terminal 10 to suppress its low frequency component. An error correction coding circuit 14 divides an output of the mapping coding circuit 12 with a generation polynomial and outputs the residue as a check bit, that is, a sub information data. Then a 8-9 conversion circuit 16 the bit of the sub information data from 8-bit into 9-bit. An addition circuit 18 adds the check bit from the 8-9 conversion circuit 16 to the main information data from the mapping coding circuit 12 to output a code word in P-bit as a whole. Thus, the transmission data whose low frequency component is sufficiently suppressed is formed and data transmission with high density is attained.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は情報データを伝送するデータ伝送装置に関する
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transmission device for transmitting information data.

[従来の技術] ディジタル信号の伝送系、例えば磁気記録再生系では一
般に、直流成分を再生できない。従って、伝送データの
低域成分を抑圧する方式が各種提案されている。例えば
、nビット・データをnビット・データに変換するn 
/ nマツピング符号化があるが、これは、隣接するデ
ータ間に相関がある場合に適用できるものであり、誤り
検出訂正符号などのような副情報、その他の付加情報を
付加する場合、データ間に相関性がないので、マツピン
グを行なっても低域抑圧効果が低い。
[Prior Art] Digital signal transmission systems, such as magnetic recording and reproducing systems, generally cannot reproduce DC components. Therefore, various methods have been proposed for suppressing the low-frequency components of transmission data. For example, to convert n-bit data to n-bit data, n
/n mapping coding, which can be applied when there is a correlation between adjacent data, and when adding side information such as an error detection and correction code or other additional information, it is possible to Since there is no correlation between the two, the low frequency suppression effect is low even if mapping is performed.

[発明が解決しようとする課題] これに対して、mビット・データをn (>m)ビット
・データに符号語全体として変換する方法(例えば、8
−9変換)や、副情報を適当に分散させる方法が考えら
れるが、前者の場合、例えば8ビツトのデータを9ビツ
トのデータに変換するので、冗長度が増え、ビット・レ
ートの増加を招くという欠点がある。また後者の場合、
例えば生成されたパリティを、低域成分が抑圧されるよ
うに分散させる方法をとるが、そうすると、データ符号
長が短い場合などにパリティが多くなるので充分な低域
抑圧効果を得られないという欠点がある。
[Problems to be Solved by the Invention] In contrast, a method of converting m-bit data to n (>m)-bit data as an entire code word (for example, 8
-9 conversion) or a method of distributing the side information appropriately, but in the former case, for example, 8-bit data is converted to 9-bit data, which increases redundancy and causes an increase in the bit rate. There is a drawback. Also, in the latter case,
For example, a method is used in which the generated parity is distributed so that low-frequency components are suppressed, but this has the disadvantage that if the data code length is short, the amount of parity increases, making it impossible to obtain a sufficient low-frequency suppression effect. There is.

本発明は、上記のように副情報を持つ情報デー夕を、充
分に低域を抑圧して伝送できるデータ伝送装置を提示す
ることを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a data transmission device that can transmit information data having sub-information as described above while sufficiently suppressing the low frequency range.

[課題を解決するための手段] 本発明に係るデータ伝送装置は、主情報及び、当該主情
報に応じて生成される副情報を伝送するデータ伝送装置
であって、主情報を低域抑圧する第1の低域抑圧手段と
、当該副情報を低域抑圧する第2の低域抑圧手段と、当
該第1及び第2の低域抑圧手段の出力を合成して出力す
る出力手段とを具備することを特徴とする。
[Means for Solving the Problems] A data transmission device according to the present invention is a data transmission device that transmits main information and sub information generated according to the main information, and suppresses low frequencies of the main information. It includes a first low frequency suppression means, a second low frequency suppression means for suppressing the low frequency range of the sub information, and an output means for combining and outputting the outputs of the first and second low frequency suppression means. It is characterized by

[作用] 上記第1及び第2の低域抑圧手段により、主情報及び副
情報を個別に且つ夫々に適した方法で低域抑圧できる。
[Operation] The first and second low-frequency suppressing means can suppress the low-frequency range of the main information and the sub-information individually and in a method suitable for each.

従って、冗長度の増加を最低限に抑えて、全体として低
域を効果的に抑圧した伝送データを形成できる。
Therefore, it is possible to minimize the increase in redundancy and to form transmission data that effectively suppresses the low frequency range as a whole.

[実施例] 以下、図面を参照して本発明の詳細な説明する。[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

第1図は本発明の一実施例の概略構成ブロック図を示す
。10は伝送しようとするデータの入力端子、12はマ
ツピング符号化回路、14は誤り訂正符号生成回路、1
6は8ビツト・データを9ビツト・データに変換する8
−9変換回路、18はマツピング符号化回路12の出力
(主情報)に8−9変換回路16の出力(副情報)を付
加する付加回路、20は伝送路に接続する出力端子、2
2はクロック・パルス発振回路、24はクロック・パル
ス発振回路22からのクロック・パルスに従い、回路1
2,14,16.18に供給するタイミング信号を発生
するタイミング発生回路である。
FIG. 1 shows a schematic block diagram of an embodiment of the present invention. 10 is an input terminal for data to be transmitted; 12 is a mapping encoding circuit; 14 is an error correction code generating circuit;
6 converts 8-bit data to 9-bit data 8
-9 conversion circuit; 18 is an additional circuit that adds the output (sub information) of the 8-9 conversion circuit 16 to the output (main information) of the mapping encoding circuit 12; 20 is an output terminal connected to the transmission line;
2 is a clock pulse oscillation circuit, and 24 is a clock pulse oscillation circuit according to the clock pulse from the clock pulse oscillation circuit 22.
This is a timing generation circuit that generates timing signals to be supplied to 2, 14, 16, and 18.

マツピング符号化回路12は入力端子10から入力する
主情報データをマツピング符号化する。
The mapping encoding circuit 12 maps and encodes the main information data input from the input terminal 10.

主情報データが例えば画像データの場合には、その性質
を利用した符号化を行ない、低域成分を抑圧する。
If the main information data is, for example, image data, encoding is performed using its properties to suppress low-frequency components.

誤り訂正符号化回路14はマツピング符号化回路12の
出力を生成多項式で除算し、その剰余を検査ビット、即
ち副情報データとして出力する。
The error correction encoding circuit 14 divides the output of the mapping encoding circuit 12 by the generator polynomial and outputs the remainder as check bits, ie, sub information data.

そして、8−9変換回路16はこの副情報データを8ビ
ツトから9ビツトに変換する。
Then, the 8-9 conversion circuit 16 converts this sub information data from 8 bits to 9 bits.

8−9変換回路16では、256個の8ビツト・ディジ
タル・データに対して、512個の9ビツト・ディジタ
ル・データのうちの256個を割り当てるものであり、
512個の9ビツト・データから256個を選択する基
準としては例えば、CD S (Codeword D
igital Sum)の絶対値が小さいものから選択
する。即ち、9ビツト・データで、CDSが+1又は−
1になるデータが252個であり、このうち、ランレン
グス制限を5とすると、該当するものが222個になり
、残りの34個はI CDS l =3のものから補う
。このような基準により、低域成分の抑圧された256
@の9ビツト・データを選択できる。
The 8-9 conversion circuit 16 allocates 256 pieces of 512 pieces of 9-bit digital data to 256 pieces of 8-bit digital data.
As a criterion for selecting 256 pieces of 9-bit data from 512 pieces of 9-bit data, for example, CD S (Codeword D
Select from the one with the smallest absolute value of (digital Sum). That is, with 9-bit data, CDS is +1 or -
There are 252 pieces of data that become 1, and among these, if the run length limit is 5, there are 222 pieces of data, and the remaining 34 pieces are supplemented from those with I CDS l =3. Based on these standards, 256
9-bit data of @ can be selected.

8−9変換回路16の回路例を第2図に示す。A circuit example of the 8-9 conversion circuit 16 is shown in FIG.

変換ROM26は上述の8ビツト・データと選択された
9ビツト・データとの変換テーブルを記憶しており、誤
り訂正符号生成回路14の出力は変換ROM26により
9ビツトに変換され、その9ビツト出力は、パラレル・
シリアル変換回路28によりシリアル信号に変換され、
NRZI変換回路30によってNRZI符号に変換され
る。このNRZ I符号が付加回路18に供給される。
The conversion ROM 26 stores a conversion table between the above-mentioned 8-bit data and the selected 9-bit data, and the output of the error correction code generation circuit 14 is converted into 9-bit data by the conversion ROM 26, and the 9-bit output is ,parallel·
It is converted into a serial signal by the serial conversion circuit 28,
It is converted into an NRZI code by the NRZI conversion circuit 30. This NRZ I code is supplied to an additional circuit 18.

付加回路18は、マツピング符号化回路12からの主情
報データ(Kビット)に、8−9変換回路16からの検
査ビット、即ち副情報データ(Lビット)を付加して、
全体でPビットの符合語を出力する。付加回路18の出
力構成を第3図に示す。
The addition circuit 18 adds the check bits, that is, the sub information data (L bits) from the 8-9 conversion circuit 16 to the main information data (K bits) from the mapping encoding circuit 12,
A total of P bits of code words are output. The output configuration of the additional circuit 18 is shown in FIG.

このようにして、主情報データと、当該主情報データに
応じて生成された副情報データとの両方について、低域
成分を充分に抑圧した伝送データを形成でき、高密度の
データ伝送が可能になる。
In this way, it is possible to form transmission data that sufficiently suppresses low-frequency components for both the main information data and the sub-information data generated according to the main information data, enabling high-density data transmission. Become.

8−9変換、より一般的にはm−n変換により副情報デ
ータの部分で冗長度が増し、伝送ビット・レートの増大
を招くが、この影響は副情報データのみにとどまるので
、伝送ビット・レートの増加は微少である。また、副情
報データについて低域成分を抑圧する方法は、8−9変
換に限らず、他の変換方式でもよい。
8-9 conversion, more generally m-n conversion, increases the redundancy in the side information data part, leading to an increase in the transmission bit rate, but this effect is limited to only the side information data, so the transmission bit rate increases. The increase in rate is minimal. Furthermore, the method for suppressing low-frequency components of the sub information data is not limited to 8-9 conversion, but may be any other conversion method.

[発明の効果] 以上の説明から容易に理解できるように、本発明によれ
ば、主情報及び副情報の両方について低域成分を充分効
果的に抑圧できる。
[Effects of the Invention] As can be easily understood from the above description, according to the present invention, low frequency components of both main information and sub information can be suppressed sufficiently effectively.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の概略構成ブロック図、第2
図は8−9変換回路16の回路構成例、第3図は付加回
路18の出力のデータ・フレーム構造図である。
FIG. 1 is a schematic block diagram of an embodiment of the present invention, and FIG.
The figure shows an example of the circuit configuration of the 8-9 conversion circuit 16, and FIG. 3 is a diagram showing the data frame structure of the output of the additional circuit 18.

Claims (1)

【特許請求の範囲】[Claims] 主情報及び、当該主情報に応じて生成される副情報を伝
送するデータ伝送装置であって、主情報を低域抑圧する
第1の低域抑圧手段と、当該副情報を低域抑圧する第2
の低域抑圧手段と、当該第1及び第2の低域抑圧手段の
出力を合成して出力する出力手段とを具備することを特
徴とするデータ伝送装置。
A data transmission device that transmits main information and sub-information generated according to the main information, comprising a first low-frequency suppressing means for suppressing low frequencies of the main information, and a first low-frequency suppressing means for suppressing low frequencies of the sub-information. 2
1. A data transmission device comprising: low frequency suppression means; and output means for combining and outputting the outputs of the first and second low frequency suppression means.
JP1140742A 1989-06-02 1989-06-02 Data transmission equipment Pending JPH036923A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1140742A JPH036923A (en) 1989-06-02 1989-06-02 Data transmission equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1140742A JPH036923A (en) 1989-06-02 1989-06-02 Data transmission equipment

Publications (1)

Publication Number Publication Date
JPH036923A true JPH036923A (en) 1991-01-14

Family

ID=15275663

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1140742A Pending JPH036923A (en) 1989-06-02 1989-06-02 Data transmission equipment

Country Status (1)

Country Link
JP (1) JPH036923A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6173424A (en) * 1984-09-19 1986-04-15 Hitachi Ltd Conversion system of binary data

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6173424A (en) * 1984-09-19 1986-04-15 Hitachi Ltd Conversion system of binary data

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