JPH0369100A - Redundant program circuit - Google Patents

Abstract

PURPOSE:To detect defective operation without fail when it takes long time to raise a power source, and to enable reproducing by executing control by using a switching circuit which turns ON/OFF the source potential of an MOSFET for feedback by a signal for inspection. CONSTITUTION:When a circuit is inspected, an MOSFET-T2 is turned OFF by setting the potential of a pad part 3 to be 'L'. Then, most of all electric charged to be injected from the power source to the input of an inverter 2 are held. At such a time, when a fuse 1 is not completely cut, the electric charges injected through the fuse 1 to the input of the inverter 2 does not discharge to a grounding line and an input potential is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a redundant program circuit, and more particularly to a redundant program circuit that selects memory cells of redundant bits in a semiconductor integrated circuit device.

[Conventional technology]

Conventionally, such semiconductor integrated circuit devices have a plurality of memory cells and redundant bit memory cells formed on a semiconductor substrate, and a redundancy program circuit is used as a circuit for selecting and testing the redundant bit memory cells.

FIG. 3 is a redundant program circuit diagram showing an example of such a conventional system.

As shown in FIG. 3, the conventional redundant program circuit includes a phase section 1 formed of polycrystalline silicon on a semiconductor substrate and configured to be able to be cut by trimming with a laser beam after the semiconductor chip is manufactured. , an inverter circuit 2 with a high logic threshold value, and an n-channel MOSFET T1 for feedback. Such a redundant program circuit includes phase section 1
If not disconnected, phase 1 is connected to the input of inverter 2.
A high level is supplied via.

Therefore, the output of inverter 2 becomes low level, and MO
Since SFET Tl is cut off, the input high level of inverter 2 is compensated. On the other hand, if phase 1 is disconnected, inverter 2 cannot allow its input to exceed its logic threshold and the output
Since the voltage is higher than the threshold value of T Tl, the input of the inverter 20 is fixed at a low level and the output is fixed at a high level.

As a result, the output of inverter 2 is fixed at high level and low level, respectively, depending on whether phase 1 is disconnected or not, so the output of inverter 2 can be used as a decode signal or enable signal for redundant bit selection. It has become.

[Problem to be solved by the invention]

In the conventional redundancy program circuit described above, the input voltage of the inverter 2 meets the potential condition set by phase l and M
Since the configuration is determined only by the feed voltage of OSFET Tl, if the disconnection of phase 1 is not complete, there will be a condition where the power line and the inverter 20 input are connected with high resistance. In this case, the input potential of the inverter 2 increases following the rise of the power supply voltage. A case in which the cutting in phase 1 is not complete will be described below.

FIG. 4 is a voltage characteristic diagram of each part when the power supply voltage rises steeply in FIG. 3.

As shown in FIG. 4, since the input IN2 of the inverter 2 has a high resistance between it and the power supply line, it rises slowly with respect to the rise of the power supply voltage.

However, since the logic threshold of inverter 2 rises in proportion to the power supply voltage, if the value of the high resistance is large or if the power supply voltage rises very quickly, the input level of inverter 2 will rise proportionally to the power supply voltage. cannot exceed the logic threshold of p-chTr of inverter 2, and at time tl, the difference between the power supply level and the input level of inverter 2 becomes
7, the output level of inverter 2 OUT 2
starts to rise gradually. Furthermore, the output OU of inverter 2
When T 2 exceeds the threshold value of MOSFET Tl at time t2, MOSFET Tl is turned on and the input potential IN2 of inverter 2 decreases.

That is, regarding inverter 2, input IN2 is low;
Output OUT! reaches a high stable state.

Therefore, under this condition, a normal output result of the redundancy program circuit is obtained in response to phase disconnection, and no defective operation occurs.

FIG. 5 is a voltage characteristic diagram of each part when the power supply voltage in FIG. 3 rises gradually.

As shown in FIG. 5, when the power supply voltage rises slowly, the input potential IN2 of inverter 2 rises almost simultaneously with the power supply potential and exceeds the logic threshold, so the output of inverter 2 is at a low level. A stable state is reached. As a result, the output of the redundancy program circuit becomes inverted data with respect to programming, and a defect occurs in which the memory cell of the redundant bit that should be selected cannot be selected.

Incidentally, electrical characteristic testing equipment for integrated circuit devices that perform TTL, ECL, or CML logic input/output operations typically perform binary digital measurements. Furthermore, there are restrictions on the voltage rise time of the driver that drives the power supply voltage, and it is not possible to take a sufficiently long time. Therefore, there is a drawback that it is extremely difficult to detect the above-mentioned malfunction.

An object of the present invention is to provide a redundant program circuit that can reliably detect and reproduce malfunctions that occur when the power source startup time is long.

[Means to solve the problem]

The redundant program circuit of the present invention includes a phase whose one end is connected to a power supply line, an inverter whose other end is connected to an input side, a drain of which is connected to the input side of the inverter, and an output side of the inverter is a gate. Feedback n-channel type MOS FET connected to
and a switching circuit connected between the ground of the feedback n-channel MOSFET and ground, and turned on and off by a test signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a redundant program circuit diagram showing a first embodiment of the present invention.

As shown in FIG. 1, this embodiment includes a phase portion l formed of polycrystalline silicon on a semiconductor substrate, and an inverter circuit connected to one end of this phase portion l and having a high logic threshold value. 2, the gate is connected to the output side of this inverter circuit 2, and the drain is connected to the inverter 2.
n-channel type M for feedback connected to the input side of
An OS FET Tl, an n-channel MOSFET T2 for switching connected between the source of this MOSFET Tl and ground, and a MOSFET T2 for inputting redundant program circuit test signals from the outside.
The metal pad part 3 connected to the gate, the power supply and the MOS
The resistance value connected between the gates of FET T2 is IOM
It has a resistance R1 of about Ω.

In the redundant program circuit having such a configuration, the pad portion 3
When no signal is applied to the gate of MOSFET T2, a high-level voltage is applied to the gate of MOSFET T2 via resistor R1, so MOSFET T2 turns on and the third
The operation is similar to the conventional circuit operation explained in the figure.

On the other hand, when inspecting the redundant program circuit, by setting the potential of the pad section 3 to a low level in advance, the M
Since O8F'ET T2 is in the off state, most of the charge extracted from the power supply to the input of inverter 2 is retained. At this time, if the phase section 1 is not completely disconnected, the charges extracted to the input of the inverter 2 via the phase section 1 will increase the input potential without going out to the ground line.

Since this configuration can operate even when the rise time of the power supply voltage is short, it is possible to reproduce the above-mentioned defective operation without taking a long rise time of the power supply voltage during the electrical characteristic test.

FIG. 2 is a redundant program circuit diagram showing a second embodiment of the present invention.

As shown in FIG. 2, this embodiment adds a resistor R2 to the input of the inverter 2 and M
It is connected between the north of OSFET Tl.

The capacitance CI,02 is a capacitance associated with the input of the inverter 2, such as a wiring capacitance or a gate capacitance, and a resistor R2 of about several tens of MΩ that does not affect the power supply current is used.

In such a redundant program circuit, first the phase section 1
When not disconnecting the resistor R2, the resistance value of the resistor R2 is sufficiently large, so that the input voltage of the inverter 20 is not lowered to a low level, and therefore a low level is obtained at the output. On the other hand, when the phase section 1 is disconnected, the inverter 20
The input charge is resistor R2, MOSFET Tl and T
2 to the ground line, the input of the inverter 20 is at a low level and the output is at a high level, which is a stable state. Furthermore,
If the phase section is not completely disconnected, if the value of the high resistance of phase section 1 is Rx and the logic threshold of inverter 2 is vi, then the input voltage of inverter 2 is D.
The limit point of logical displacement in the C-like stable state is expressed by the following equation (1). However, at this time, it is assumed that MOSFET Tl is in the off state and the resistance between the source and drain is infinite, and the resistance between the source and drain of MOSFET T2 is assumed to be RT2.

Vi/VDD=(R1+RT2)/(Rx+
R1+ RT 2) (1) Therefore, under the conditions shown in equation (2) below, the input potential of inverter 20 cannot exceed the logic threshold of inverter 2 regardless of the rise time of the power supply voltage. do not have.

Rx>(V,,(R1+RT2)/Vs)
(R1+ RT 2 )...(2) By the way, in order to detect if the above-mentioned cutting of the phase part 1 is incomplete, first, as in the above-mentioned first embodiment, , apply a low level to the test pad 3 to cut off the MOSFET T2, and
This can be determined by applying the power supply voltage and determining whether the output of the inverter 2 changes to a low level, but the time required from the rise of the power supply voltage until the input of the inverter 2 exceeds the logic threshold is determined by Rx, It is uniquely determined by the time constants of CI and C2, and the maximum value of Rx to be measured is Rx = (
VDD(R1+ RT 2)/V i) (R1+ R
T 2) (3) ◆ Therefore, it is possible to minimize the test time required for the electrical test to detect defects in the phase section 1. In short, compared to the first embodiment described above, this embodiment has a feedback n-channel type MOSFET.
By adding the resistor R2 to the switching circuit of the ET, the test time for inspection can be minimized.

〔Effect of the invention〕

As explained above, the redundant program circuit of the present invention has a feedback MO of an inverter connected to a phase.
By controlling the SFET's ground potential using a switching circuit that turns on and off with a test signal,
This has the effect that a defective operation that occurs when the power supply voltage rise time is long, which occurs when phase disconnection is incomplete, can be reliably reproduced in a short power supply rise time.

[Brief explanation of drawings]

FIG. 1 is a redundant program circuit diagram showing a first embodiment of the present invention, FIG. 2 is a redundant program circuit diagram showing a second embodiment of the present invention, and FIG. 3 is a redundant program circuit diagram showing a conventional example. Figure 4 is a voltage characteristic diagram of each part when the power supply voltage rises steeply in Figure 3, and Figure 5 is a voltage characteristic diagram of each part when the power supply voltage rises gradually in Figure 3. be. 1... Phase section, 2... Inverter, 3... Pad section, TI, T2... n
Channel type MOSFET, R1, R2...high resistance, C1, C2...capacity.

Claims (1)

[Claims] a phase whose one end is connected to a power supply line; an inverter whose other end is connected to the input side of the phase; and a feedback n whose drain is connected to the input side of the inverter and whose output side is connected to the gate. A redundant program circuit comprising a channel type MOSFET and a switching circuit connected between the source of the feedback n-channel type MOSFET and ground and turned on and off by a test signal.