JPH0349160B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a semiconductor integrated circuit device, and in particular to a memory circuit that stores address information, etc. of a defective circuit section in order to replace the defective circuit section with a redundant circuit section. The present invention relates to a semiconductor integrated circuit device having a memory circuit and capable of accurately detecting a write state of the memory circuit.

(Technical background) Generally, in a semiconductor integrated circuit device (hereinafter referred to as an IC device), for example, a semiconductor integrated circuit device,
Extra memory cells in addition to the normally used number of memory cells are provided as redundant bits, and if a defective memory cell is detected in an operation test at the wafer stage, etc., this defective memory cell can be used as a redundant bit. Manufacturing yield can be improved by replacing a bit line with a bit memory cell, or by replacing a bit line containing a defective memory cell with a redundant bit line containing a redundant memory cell. In semiconductor storage devices equipped with such redundant bits, a read-on memory (ROM) is used as a memory circuit to store the address of a defective memory cell.
If the input address signal matches the address of a defective memory cell stored in the ROM, the circuit is switched so that a redundant memory cell is accessed in place of the defective memory cell. Therefore, in such a ROM, it is necessary to perform write and read operations accurately, and it is also necessary to be able to accurately detect the write state.

(Prior Art and Problems) Conventionally, in an IC device having a redundant circuit portion and a memory circuit that stores address information of the redundant circuit portion, the comparison result between the input address and the address information stored in the memory circuit is externally transmitted. There was no function to output to the terminal. Therefore, conventionally, it has been impossible to detect the memory data of the memory circuit, that is, the address information of the defective circuit part, or it has been impossible to detect the memory data, etc. of the memory circuit from the internal circuit of the semiconductor chip using a special probe or the like. There was an inconvenience that it had to be extracted.

(Object of the Invention) In view of the problems in the conventional type described above, an object of the present invention is to provide an IC device having a memory circuit for storing address information of a defective circuit portion, etc. Outputs the comparison result with the information to an external terminal, detects the writing state of the memory circuit that stores address information, etc. of the defective circuit, and determines whether there is a defective circuit in the IC device that has been replaced with a redundant circuit. Another object of the present invention is to obtain an appropriate semiconductor circuit device capable of detecting the address of a defective circuit portion and inspecting the operating state of a storage device.

(Structure of the Invention) In the present invention, in order to use a redundant circuit section in place of the defective circuit section, a memory circuit that stores address information of the defective circuit section, and data obtained by reading the memory circuit and an external comprising a comparison circuit for detecting a match with an input address; and circuit means for outputting a match detection signal obtained by the comparison circuit to the outside via an external signal terminal used in normal operation; The circuit means includes first and second transistors connected between a power supply line and the external signal terminal, the first transistor being controlled based on the output of the comparison circuit, and the second transistor being controlled based on the output of the comparison circuit. A semiconductor integrated circuit device is provided, wherein the transistor is connected to conduct when a voltage outside a signal voltage range during normal operation is applied to the external signal terminal.

(Embodiments of the invention) Hereinafter, embodiments of the invention will be described with reference to the drawings.
FIG. 1 shows a coincidence detection circuit used in a semiconductor recording device as an IC device according to an embodiment of the present invention. The coincidence detection circuit shown in the figure determines whether or not the address signal input to the semiconductor memory device indicates a defective bit, and the number of coincidence detection circuits corresponding to the number of bits of the input address signal is
CMP ₀ , CMP ₁ ,..., CMP _o , depletion type load transistor Q ₁ and transistor Q _a
and an output circuit having Q _b . Transistor Q ₁ is connected between power supply V _cc and control line N ₁ and operates as a pull-up circuit or a load circuit.
Transistors Q _a and Q _b are connected to the power supply V _ss and external terminals
The gate of the transistor Q _a is connected to the control line N ₁ and the gate of the transistor Q _b is connected to the connection point between the transistors Q _a and Q _b .
Note that the external terminal EKT can also be shared with other signal or power supply terminals.

In the address determination circuit shown in FIG. 1, each matching circuit CMP ₀ , CMP ₁ , . . . , CMP _o is provided with non-inverted and inverted address signals A ₀ , ₀ , A ₁ ,
A ₁ , ..., A _o , _o are input. Then, in each matching circuit, the input address signal is compared with the address signal stored in the ROM inside each matching circuit, and if the two match, the output connected to the control line _N1 and the power supply _Vss are connected. High impedance; if not matched, low impedance.
Therefore, all matching circuits CMP ₀ , CMP ₁ ,
..., CMP _o , the potential of the control line N ₁ becomes high level, and at least 1
When a mismatch occurs in the two match circuits, the control line _N1 becomes low level. That is, each matching circuit
The addresses of defective memory cells, etc. are stored in the ROM built in each of CMP ₀ , CMP ₁ ,..., CMP _o , and when this address matches the input address, the potential of the control line _N1 becomes high level. Therefore, automatic switching between a defective memory cell and a redundant memory cell can be performed by performing a circuit operation such that a redundant memory cell is accessed instead of a defective memory cell only when the control line _N1 is at a high level. can.

In the circuit of FIG. 1, each matching circuit CMP ₀ ,
If you can know the addresses stored in the built-in ROM of CMP ₁ ,..., CMP _o , you can not only know the presence or absence of defective bits in the IC device and the address of the defective bit, but also be able to perform various tests on the IC device. It is also convenient for In order to detect the storage information of ROM, external addresses A ₀ , A ₁ ,...,
All you have to do is detect the potential of the external terminal EXT while changing A _o sequentially. When the external address matches the address stored in each ROM, the potential of the control line _N1 becomes high level, approximately _Vcc, as described above. At this time, when the potential of the external terminal EXT is lowered from V _cc , _{the potential of the power supply V ss - transistor}
The current flows to the external terminal in the path of Q _a - transistor Q _b
Flows into EXT. On the other hand, if the address stored in the ROM and the input address do not match,
As described above, the potential of the control line _N1 is at a low level, that is, approximately _Vss . Therefore, in this case, when the potential of the external terminal EXT is lowered from _Vss , a current starts to flow from the potential of the external terminal _{at Vss} - _2Vth . Note that V _th is the threshold voltage of each transistor Q _a and Q _b . Therefore, the external terminal
Detects whether the external input address matches the internal address stored in the ROM based on the potential of the external terminal EXT when current starts flowing to EXT,
In addition, it becomes possible to know the address of the defective circuit portion.

The matching circuits CMP ₀ , CMP ₁ , . . . , CMP _o used in the circuit of FIG. 1 may be those shown in FIG. 2, for example. In the circuit shown in Figure 2, the fuse F ₁ and transistor Q ₂ connected in series between the power supplies V _cc and V _ss constitute a so-called fuse blowing type ROM.
One bit of the address information of the defective memory cell is stored by the ROM. Transistors Q ₃ and Q ₄ constitute an inverter circuit,
Transistors Q ₅ , Q ₆ , Q ₇ , and Q ₈ constitute a comparison circuit. Transistors Q ₅ , Q ₆ and transistors
Q ₇ and Q ₈ are each connected in series between the control line N ₁ and the power line V _ss , the base of transistor Q ₅ is connected to the output node N ₂ of the inverter circuit, and the gate of transistor Q ₇ is of the fuse blowing type. Connected to the output node _N3 of the ROM. Further, for example, a 1-bit non-inverted address signal A _i and an inverted address signal _i are applied to the gates of transistors Q ₆ and Q ₈ , respectively (i=0, 1, 2, . . . , n).

In the circuit shown in FIG. 2, for example, when the fuse _F1 is blown, the output node _N3 of the ROM becomes a low level, and the output node _N2 of the inverter circuit becomes a high level. Therefore, transistor _Q7 is cut off and transistor _Q5 is turned on.
At that time, if the address signal A _i is "0", that is, a low level, the transistor Q ₆ is cut off, and since the transistor Q ₇ is also cut off, the potential of the control line N ₁ becomes high level. If the address signal A _i is "1", that is, at a high level, the transistor Q ₆ is turned on, and the potential of the control line N ₁ is lowered to a low level. On the other hand, if fuse _F1 is not blown, the potential at node _N3 is high and the potential at node _N2 is low, transistor _Q7 is on and transistor _Q5 is off. Become. Therefore, when the address signal A _i is "0", that is, at a low level, the inverted address signal _i becomes a high level, and the potential of the control line _N1 is lowered to a low level by transistors Q ₇ and Q ₈ , and the address signal When A _i is "1", the control line N ₁ becomes high level. That is, in the circuit shown in Fig. 2, the fuse-blown ROM stores address data " ₀ " when fuse F1 is blown, and the fuse F1 is blown.
Data “1” is stored when F ₁ is not fused, and these stored data and input address signal A _i
When the two match, the control line _N1 becomes high level.

(Effects of the Invention) As described above, according to the present invention, address information etc. stored in the ROM inside the IC device can be outputted to the outside with an extremely simple configuration, and a defective circuit replaced with a redundant circuit part can be installed in the IC device. It is possible to obtain an appropriate semiconductor circuit device in which the presence or absence of the defective circuit portion and the address of the defective circuit portion are detected, and the operating state of the storage device can be tested. Furthermore, in the device of the present invention, the output of the comparison result can be observed when a voltage outside the voltage range during normal operation is applied, and the output terminal can be shared with other output terminals. It is.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram showing the configuration of an IC device according to an embodiment of the present invention, and FIG.
FIG. 3 is an electrical circuit diagram showing a detailed configuration of each matching circuit used in the circuit shown in the figure. CMP ₀ , CMP ₁ ,..., CMP _o : Matching circuit, Q ₁ ,
Q ₂ ,..., Q ₈ , Q _a , Q _b : Transistor, EXT: External terminal, F ₁ : Fuse.

Claims (1)

[Claims] 1. A memory circuit that stores address information of the defective circuit section in order to use a redundant circuit section in place of the defective circuit section, and data obtained by reading the memory circuit and an external input address. and a circuit means for outputting a coincidence detection signal obtained by the comparison circuit to the outside via an external signal terminal used in normal operation. , including first and second transistors connected between a power supply line and the external signal terminal, the first transistor being controlled based on the output of the comparison circuit, and the second transistor being controlled based on the output of the comparison circuit. , connected to the external signal terminal so as to become conductive when a voltage outside the signal voltage range during normal operation is applied to the external signal terminal.