JPH036837A - Charge transfer element and manufacture thereof - Google Patents

Abstract

PURPOSE:To double the bit density of conventional device, to reduce a size in charge transfer direction by 50% of conventional one, and to realize high density readily by forming a potential step inside a single electrode for orientation of charge transfer by implanting an impurity. CONSTITUTION:A first impurity (N-type impurity) is implanted ranging from one side below a first layer transfer electrode 4 to all over below a second layer transfer electrode 5 to form a first region 6. A second impurity (P-type impurity) is implanted to one side region below the second layer transfer electrode 5 to form a second region 7. If an implanted amount of each impurity is set so that a potential shift amount +Va and -Ve of each of first and second impurity may coincide in a direction to cancel each other, potential steps for orientation can be made to coincide between first layer and second layer transfer electrode 4, 5. According to this constitution, it is possible to orient a potential depth formed immediately below the transfer electrode 4, 5 to a charge transfer direction and to reduce pitch of a transfer electrode by half of a conventional device.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention can be applied to two-dimensional image sensors and the like.
The present invention relates to a suitable charge transfer device, and particularly to a charge transfer device that can be increased in density and a method for manufacturing the same.

[Prior Art] Charge transfer devices (C) such as charge coupled devices (COD) used as two-dimensional image sensors
As is well known, the four-phase drive method shown in FIG. 12, the three-phase drive method shown in FIG. 13, and the two-phase drive method shown in FIG. 14 are well-known transfer methods for TD). 1・
If the (1/2) phase drive method is used, one phase of the two-phase drive method is set to D.
It is basically the same as the two-phase drive method except that the C potential is used.

Among these, when considering a unit of 1 bit, the 4-phase and 3-phase drive systems are usually configured with one electrode per 1 bit, but the 2-phase drive system requires direction of signal charge transfer within the phase. Usually, one electrode consists of two electrodes.

As shown in Fig. 14, the direction of signal charge transfer is formed by injecting impurity Nb only under one of the transfer electrodes in the same phase to form a potential barrier (■b). Common.

Regarding the electrode formation method, two-phase and four-phase drive systems can have a two-layer structure, but the three-phase system requires a three-layer structure to make each bit equivalent, so if the consecutive characters are In some cases, a four-phase drive system is adopted.

As shown in FIG. 12, the maximum amount of transferred charge per unit area is such that the signal charge accumulation area is 50% or more of the bit length, and the effective potential difference is equal to or greater than the clock amplitude Vc.
In terms of characteristics, the 4-ring drive system is superior because it can only remove as much oil as possible.

On the other hand, in terms of transfer efficiency, the two-phase drive method is superior in that it can greatly increase the fringe field effect that defines charge transfer during high-speed transfer.

That is, in the two-phase drive method, since the direction of signal charge transfer is created as shown in FIG. 14, the fringe electric field effect acts over the entire period of charge transfer. Therefore, there is no need to worry about No. 48 charge being left behind or backflow, and as a result, the transfer efficiency during high-speed driving is superior to other driving methods.

For the above reasons, a four-phase drive system is generally used for low-speed drive, and a two-phase drive system is often used for high-speed drive. Note that all of these have a configuration of four electrodes per one bit.

[Problems to be Solved by the Invention] In order to increase the number of bits in such a COD, the bit length must be made extremely short because it is necessary to suppress an increase in chip size. The case of a two-dimensional image sensor will be explained below as an example.

As is well known, a two-dimensional CCD image sensor includes a plurality of pixels (photodiodes PD) arranged two-dimensionally, a plurality of columns of vertical shift registers that vertically transfer signal charges accumulated in these pixels, and a vertical shift register that vertically transfers signal charges accumulated in these pixels. A horizontal shift register is usually configured in one column and is configured to receive a signal charge, transfer it in the horizontal direction, and convert it into a predetermined electric signal.

Since horizontal shift registers are generally required to be driven at high speed, a two-phase drive system can be adopted as described above, and the electrode pattern is as shown in FIG. 15.

- The area within the dotted chain line is the active region 20 forming the COD transfer channel in the horizontal shift register, and the area outside thereof is the channel stop area. The broken line is the transfer 'ra pole 4 of the first layer,
The solid lines indicate the transfer electrodes 5 in the second layer, and clock signals φH1 and φ■2 are applied from wirings shown by broken lines through contact openings 22 marked with an x, respectively.

Now, consider the number of horizontal pixels.

Horizontal shift register (horizontal transfer section) as the number of pixels increases
For example, when the number of horizontal effective pixels is 510 in a 1/2 inch optical system, the bit length becomes about 12.8 μm.

Therefore, the number of horizontal effective pixels changes from 510 to 77, for example.
If it increases to 0, the bit length is 12.8μm
It becomes short from about 8.5 μm.

As is clear from FIG. 15, in order to form four electrodes within 8.5 μm, the electrode processing itself is difficult, and the formation of the contact opening 22 that applies the potential to the electrodes is also difficult.
Current technology is already close to reaching its limits. In the future, if we are going to increase the number of pixels and therefore the similar bit length, the current technical system will not be able to handle it.

The above discussion is not limited to the case of two-dimensional image sensors;
This also applies to one-dimensional image sensors and delay lines.

Next, consider the case of a vertical shift register.

Two-dimensional CCD image sensors are classified into interline transfer type and frame transfer type depending on the relationship between the light receiving part PD and the vertical shift register. The currently mainstream interline transfer method will be explained below.

FIG. 16 is a schematic diagram of the configuration of this pixel section. Light receiving part PD
vertical columns and vertical shift registers are arranged alternately, and signal charges in the light receiving section PD are read out by the adjacent vertical shift registers. The lead-out portions of the transfer electrodes φv1 to φv4 need to pass between the upper and lower light-receiving parts PD, but if the transfer electrodes φv1 to φv4 of the vertical shift register have a two-layer structure, four electrodes are required per one bit, so two Each photodetector PD corresponds to one bit, and a four-phase drive system is adopted.

The drive method is the same for the two-phase drive method.

For this reason, in one reading, 1
Either the number 48 charge of the second photodetector PD is read out, or each signal charge of two vertically adjacent photodetector PDs is added and read, and the signal charges of all the photodetectors PD are independently read out.
It cannot be read in one go.

As described above, with the structure of the conventional charge transfer element, it is impossible to increase the density.

Therefore, the present invention solves these problems and proposes a charge transfer element and a manufacturing method suitable for its structure.

[Means for Solving the Problem] In order to solve the above-mentioned problem, in the first invention, the first layer transfer electrode and the second layer are connected to each other on the surface of the semiconductor substrate via an insulating film.
In a charge transfer element in which transfer electrodes of the first layer are formed alternately, two
A first impurity of a first conductivity type is implanted into the semiconductor substrate in the region covering the entire region under the transfer electrode of the second layer, and a part of the region under the transfer electrode of the second layer is implanted into the semiconductor substrate. A second impurity is implanted into the semiconductor substrate in the region as a second region, and when the first and second impurities are of different conductivity types, the second region is approximately the same as the first region. This is the area under the second layer electrode that is in contact with the bottom of the first layer electrode at the center, and when the first and second impurities are of the same conductivity type, the second layer electrode is located at the boundary within the first region. The lower first layer was selected to be in contact with the lower part of the first electrode, and by implanting the above impurity, a potential step for directing charge transfer was formed within the single electrode. This is a characteristic feature.

In the second invention, after forming the first electrode layer on the entire surface of the semiconductor substrate via an insulating film, a first film is formed on the first electrode layer to ensure a sufficient etching selectivity with respect to the electrode layer. and a first resist layer are formed in the same pattern, and using the first film and the first resist layer as a mask, a first conductive film is formed on the surface of the semiconductor substrate through the first electrode layer and the insulating film. After implanting the first impurity of the mold with high energy and removing the first resist layer, one end is placed on the first film,
A resist layer @2 is patterned in a region near the other end or the center of the first inter-film line, and the second resist layer and the first
Using the film as a mask, the first electrode layer is etched and IN
After removing the second resist layer, a third resist layer is patterned in a region where one end covers the first layer electrode and the other end is in the middle of the gap between the first layer electrodes. A second impurity is implanted into the semiconductor substrate surface using the resist layer No. 3 and the first layer electrode as a mask, and after removing the third resist layer,
This method is characterized in that the second layer electrode is patterned on the semiconductor substrate in the first layer electrode gap region with an insulating film interposed therebetween.

[Function] By configuring in this way, there is a potential difference between the two layers of transfer electrodes to ensure continuity and directionality between the two layers of transfer electrodes. It is not a matter of shaping it to have it.

This makes it possible to reduce the number of transfer electrodes,
When applied to a two-phase driving force type, it is only necessary to assign two electrodes per one bit, and the bit length can be significantly reduced. If we compare with the same electrode pitch, the information density of the signals that can be handled is 2
It can be doubled.

[Embodiment 1] Next, a case in which an example of the charge transfer device according to the present invention is applied to the above-mentioned CCD will be described in detail with reference to FIG. 1 and subsequent figures.

Note that, in order to simplify the explanation, below, a case will be exemplified in which all the CCDs are buried channel CCDs and the signal charges are electrons.

FIG. 1A is a sectional view along the transfer direction, and FIG. 1B is a diagram showing the potential distribution for FIG. 1A.

In FIG. 1A, in the surface region of the P-type semiconductor substrate 1, CC
An N-type semiconductor layer is formed over the entire D transfer channel to form a buried channel layer 2. On the surface of the semiconductor substrate, first-layer transfer electrodes 4 and second-layer transfer electrodes 5 are alternately deposited in the transfer direction via thin insulating films 3 such as 5i02, and the first-layer transfer electrodes 4 and ? A transfer lock φ1 shown in FIG. 4A is applied to the second electrode 4, and a transfer lock φ2 shown in FIG. 4B is applied to the second layer transfer electrode 5.

The direction of charge transfer is determined by the following configuration.

First, a first impurity (in this example, an N-type impurity) is implanted from one side under the first layer transfer electrode 4 to the entire area under the second layer transfer electrode 5 on the surface of the semiconductor substrate. 6
is formed. Then, a second impurity (in this example, a P-type impurity) is implanted into one region under the second layer transfer electrode 5, and the second region 7 is completely formed.

The potential distribution when configured as above will be explained with reference to FIG. 1B. The first impurity and the second impurity deepen the potential by +Va and -Ve, respectively.

Therefore, the first region 6 forms a potential step Va for charge transfer direction under the first layer transfer electrode 4, and the second region 7 forms a potential step Va for charge transfer direction under the second layer transfer electrode 5. A potential step Ve for orientation is formed. Vc is a potential difference corresponding to the clock amplitude.

Potential shift amount +V due to each of the first and second impurities
If the implantation amount of each impurity is set to such an extent that a and -Ve match in the direction of canceling each other out, it is possible to match the potential steps in orientation between the first and second layer transfer electrodes 4.5. can. By setting the second impurity implantation region in the positional relationship shown in FIG. 1, the depth direction of the potential formed directly under the transfer electrodes 4 and 5 can be directed in the charge transfer direction.

As a result, as shown in FIG. 4, the transfer pulses φ1, φ2
enables two-phase drive under the same voltage conditions.

In the first [mB, the solid line potential is when transfer lock φ1 is low and φ2 is high, and the broken line potential is when transfer lock φ1 is high (and φ2 is low. The transfer direction is from the left in the figure. Become the right.

In this way, by forming potential steps that provide direction for charge transfer under each transfer electrode, the pitch of the transfer electrodes becomes about half that of the conventional one.

Note that this potential relationship does not change even in the final stage of the charge transfer cycle, so a fringe electric field still exists even in the final stage of the charge transfer cycle, and a potential barrier called Va that prevents the reverse flow of charges always exists. ing.

As a result, even if the transfer cycle is shortened, transfer deterioration is less likely to occur, and it is possible to increase the transfer speed even when the signal is on fire.

FIG. 2 shows the configuration of a horizontal shift register when applied to a two-dimensional image sensor.

The transfer electrodes that can be deposited on the active region 20 of the horizontal shift register have a two-phase structure, and the number of electrodes per bit is 4.
halved from one to two.

Therefore, when the bit length is the same as the conventional one, the convergence of the transfer electrodes 4 and 5 becomes about twice that of the conventional one, as shown in the figure.

Furthermore, since the opening area of the contact opening 22 for supplying the transfer lock is approximately doubled, manufacturing becomes easier.

When the radius of the transfer electrode 4.5 and the area of the contact opening 22 are kept the same as in the conventional case, the bit density is doubled.

FIG. 3 shows a configuration example of a vertical shift register similarly applied to the interline transfer method.

Vertical columns of light receiving sections PD and vertical shift registers are arranged alternately, and signal charges of the light receiving sections PD are read out by adjacent two-phase driven vertical shift registers. Transfer electrode φV
The lead-out portions of l and φv2 need to pass between the upper and lower photodetector PDs, but in the present invention, 2 electrodes correspond to 1 bit, so if φVl and φV2 are made of 2 layers 111, it is necessary to pass the lead-out portions between the upper and lower photodetector PDs. It becomes 1 bit. Therefore, it becomes possible to read out the signals of all the light receiving sections PD independently at one time. As a result, the vertical resolution per reading is doubled compared to the conventional example shown in FIG. 16.

FIG. 5 is a process diagram showing an example of the method for manufacturing a CCD according to the present invention, in which a buried channel layer 2 is formed by implanting N-type impurities into the surface region of a P-type semiconductor substrate 1 (a fifth
Figure A).

Next, a thin gate insulating film 3 is formed using 5i02 or the like over the entire surface of the semiconductor substrate 1, and a first layer transfer electrode 4 is formed on the upper surface of the thin gate insulating film 3, and the etching selectivity with respect to the electrode 4 is roughly etched on the upper surface. A film 8 with a sufficient amount of film 8 is deposited (FIG. 5B).

When polysilicon is used as the transfer electrode 4 and is etched by reactive ion etching as described later, the film 8 is 5i02 as described above by way of example.

A resist film 9 is roughly and selectively deposited on the upper surface of the film 8 (FIG. 5B), and the film 8 is selectively etched using this resist film 9, and then patterned. Using this film 8 and resist film 9, semiconductor base FiI
On the surface side of the transfer electrode 4 and the gate insulating film 3,
The first region (
An N-type impurity region) 6 is formed (FIG. 5C).

For example, if the transfer electrode 4 is formed of polysilicon as described above and has a thickness of about 5000 J Angstroms, the implantation energy of the N-type impurity is approximately 500 KeV.
It is enough.

After forming the first region 6, the resist film 9 is removed, and then a resist film 11 with a rough predetermined pattern is deposited (FIG. 5D). As shown in the figure, the resist film 11 is
It is patterned so that one end thereof extends over the membrane 8 and the other end lies approximately in the center of the gap between the membranes 8 . and,
Using the resist film 11 and film 8 as a mask, the transfer electrode 4
is patterned by ion etching (Fig. 5D)
).

Such patterning allows one end of the first region 6 to be in contact with one end of the transfer electrode 4 and the other end thereof to extend to the central region of the adjacent transfer electrode 4 .

Next, the resist film 11 is removed and a new resist film 12 is formed.
is deposited in a predetermined pattern (Fig. 5E)
. This resist film 12 is patterned so that its negative end extends over the transfer electrode 4 and the other end lies in the middle of the opposing gap between the transfer electrodes 4 .

Thereafter, using resist film 12 as a mask, P type impurities are implanted to form second region 7 (FIG. 5F).

When the impurity implantation is completed, the film 8 and the resist film 12 are removed, and then a second layer of transfer electrode 5 is deposited via a thin gate insulating film (Si021) and patterned (Fig. 5G). ).

By depositing and forming the second transfer electrode 5, the manufacturing process of the target CCD is completed.

The method for manufacturing the CCD described above is as follows: First, the first region 6 is implanted with high energy through the first layer electrode 4 using the first film 8 and the first resist layer 9 as a mask. to be formed in

Second, the etching process is performed so that the transfer electrode 4 located under the first film 8 remains.

It has its characteristics.

Only by adopting such a unique manufacturing method can direction of charge transfer be achieved in a CCD with a minimum shape without producing a potential barrier or a potential dip.

This will be easily understood from the explanation below.

That is, if charge transfer can be directed within a single electrode, the CCD density can be doubled.

However, even a slight deviation between the orientation boundary and the electrode boundary creates a potential dip or barrier, leading to transfer deterioration.

As a method to solve this problem, "offset game h
"CCD Method" published by Kindai Kagakusha "Charge Transfer Device J 1"
978. C,5equin, written by M. Tompset> is the best known.

However, this method has the following problems.

(1) In a surface channel CCD (SCCD), as shown in FIG. 6, the larger the gate insulating film thickness (dox), the smaller the potential (φm), or the amount of change
The smaller the gate voltage (VG), the smaller m becomes, and the amount of signal charge cannot be obtained unless the voltage is increased on the low level side of the clock amplitude.

(2) In a buried channel CCD (BCCD), the seventh
As shown in the figure, the larger dox is, the larger φm is.
The accumulation area is on the dox-large side. On the other hand, when dox becomes thick (the signal charge amount per unit gate voltage becomes small), this is disadvantageous with respect to the transferable charge amount.

From the above, it is clear that it is desirable to adopt the minimum shape CCD method and to direct the transfer by implanting impurity ions.

However, with the prior art, it is impossible to inject under the first layer electrode and to automatically align the boundary of the implanted region with the end of the first layer electrode.

This is because the injection below the first layer electrode needs to be performed before forming the first layer electrode, but in order to match the position of the electrode 1 to be formed later, it is necessary to implant the third layer as shown in Figure 8. Even if it were to be used, the first layer electrode on the third layer would have to be removed, which is usually impossible.

On the other hand, in the present invention, high-energy implantation is used so that the injection can be performed under the first layer electrode after the first layer electrode is formed. In this case, a third layer is formed on the first layer electrode, and the third layer and a resist layer having the same pattern are used as masks for implantation.

Next, in order to leave the first layer electrode under the third layer,
The injection under the first layer electrode extends not only under a single electrode but also under the adjacent second layer electrode. This makes it possible to align the implantation region boundary with the end of the first layer electrode.

The first and second impurity implanted regions are formed so that one end thereof automatically coincides with the boundary between the transfer electrodes in the first layer and the second layer, so that it is possible to prevent charge transfer failure from occurring. No potential barrier or dip occurs.

Therefore, processing accuracy is not particularly required from the viewpoint of charge transfer efficiency.

Further, although the other ends of the first and second impurity implantation regions end at the intermediate portion of each transfer electrode, the processing accuracy only slightly affects the maximum charge amount.

The formation position of the region into which the second impurity is implanted (second region) differs depending on the conductivity type of the second impurity that can be implanted into the region.

That is, when the impurities implanted into the first and second regions 6 and 7 are of different conductivity types, the second impurity is implanted approximately at the center of the first region 6 and the second region 7 is It is formed.

Examples of this are the case of FIG. 1 and the case of FIG. 1A is an example in which the impurity implanted into the first region 6 is of the same conductivity type (second conductivity type) as the buried channel layer 2;
FIG. 9 shows an example in which the impurity implanted into the first region 24 is of the same conductivity type as the semiconductor substrate 1 (first impurity). 26 is a second region, which has a conductivity type different from that of the first impurity (N
A second impurity of type ) is implanted.

On the other hand, if the impurities that can be implanted into the first and second regions are of the same conductivity type, the second impurity is implanted at the border within the first region and the second region is formed. It is formed.

10 and 11 are examples thereof, and FIG. 10 is an example of the same conductivity type as the buried channel layer 2 (N type). In this example, the second impurity is implanted into the first region 28 so that the second region 30 is in contact with the right boundary of the first region 28 and a portion thereof.

FIG. 11 shows an example of the same conductivity type (P type) as the semiconductor substrate 1, and in this case, contrary to FIG. 10, the second region 34
The second impurity is completely implanted so that the left side border of the first region 32 and a part thereof are in contact with each other.

The reason why the implantation region of the second impurity is varied depending on the conductivity type of the second impurity is that the deep directionality of the potential formed directly under the transfer electrode 4.5 is directed in the charge transfer direction depending on the conductivity type. This is to make it easier.

By the way, in the examples of FIGS. 10 and 11, the potential shifts due to the first impurity and the second impurity are in the same direction, and the potentials for the same gate voltage do not match between the first layer electrode and the second layer electrode. . In this case, a driving method in which one of the two-phase clocks is a DC voltage is suitable.

In the embodiment shown in FIG. 10A, a transfer lock φ1 as shown in FIG. 4A is applied only to the transfer electrode 4, and a predetermined DC voltage V2 is applied to the other transfer W pole 5. The potential of the DC voltage V2 can be set to a voltage slightly higher than the low level potential of the transfer lock φ1.

In this way, as shown in FIG. 10B, the transfer lock φ1
When the voltage changes to a high level, a potential well as shown by the broken line is formed, so that the signal charge is transferred from left to right without losing the fringe electric field.

This type of signal charge transfer method is called a 1/2 phase drive method.

The example shown in FIG. 11 also uses the (1/2) phase drive method, and, contrary to the example shown in FIG.
1 is applied, and a predetermined DC voltage v2 is applied to the transfer electrode 4.

Note that even if the polarity of the impurity is opposite to that described above, the present invention can be applied by slightly changing the implantation region.

The type of transfer channel is not limited to a buried channel type, but may also be a surface channel type. Applicable charge transfer device tJCC
Not limited to D.

[Effects of the Invention] As explained above, according to the configuration of the present invention, the bit density can be doubled compared to the conventional one, so the dimension in the charge transfer direction can be reduced to half of the conventional one. I can do it.

In other words, when the electrode density is the same, it is possible to double the density of information that can be handled, and it has a feature that high density can be easily realized.

Further, the manufacturing method according to the present invention has a feature that orientation for charge transfer can be provided under a single electrode without creating a potential barrier or a potential dip.

Therefore, the charge transfer device according to the present invention is extremely suitable for application to two-dimensional image sensors and the like.

[Brief explanation of the drawing]

Fig. 1 is a block diagram and its potential distribution diagram showing an example of a charge transfer device according to the present invention, Fig. 2 is a block diagram of a horizontal shift register when applied to a two-dimensional image sensor, and Fig. 3 is a vertical shift register diagram as well. FIG. 4 is a diagram of the configuration of the shift register, FIG. 4 is a waveform diagram of a transfer lock used therein, FIG. 5 is a manufacturing process diagram showing an example of the charge transfer device according to the present invention, and FIGS. Explanatory drawings, FIGS. 9 to 11 are configuration diagrams and potential distribution diagrams similar to FIG. 1 showing other examples of the present invention, and FIGS. 12 to 16 are diagrams for explaining the present invention. 1... 2... 3... 4.5... 6.24.28.32... 7.26, 30.34... - Semiconductor substrate, buried channel layer, gate insulating film, transfer electrode, first Area/Second Area

Claims (2)

[Claims] (1) In a charge transfer element in which a first layer of transfer electrodes and a second layer of transfer electrodes are alternately formed on the surface of a semiconductor substrate with an insulating film interposed therebetween, the area below the first layer of transfer electrodes in the transfer direction 2 from one side area of
A first impurity of a first conductivity type is implanted into the semiconductor substrate in the region covering the entire region under the transfer electrode of the second layer, and a part of the region under the transfer electrode of the second layer is implanted into the semiconductor substrate. A second impurity is implanted into the semiconductor substrate in the region as a second region, and when the first and second impurities are of different conductivity types, the second region is implanted into the semiconductor substrate in the first region. This is a region below the second layer electrode that is in contact with the first layer electrode at approximately the center, and when the first and second impurities are of the same conductivity type, the second layer is located at the boundary within the first region. The region was selected to be in contact with the first layer under the electrode, and by implanting the above impurity, a potential step for directing charge transfer was formed within the single electrode. Characteristic charge transfer device. (2) After forming a first electrode layer on the entire surface of the semiconductor substrate via an insulating film, a first film and a first electrode layer are formed on the first electrode layer to ensure a sufficient etching selectivity with respect to the electrode layer. forming a resist layer with the same pattern, using the first film and the first resist layer as a mask, and performing the above step 1.
A first impurity of a first conductivity type is implanted with high energy into the surface of the semiconductor substrate through the second electrode layer and the insulating film, and after removing the first resist layer, one end of the first impurity is implanted into the surface of the semiconductor substrate. Then, a second resist layer is patterned in a region where the other end is near the center of the first film gap, and the first layer electrode is formed using the second resist layer and the first film as a mask. The layer is etched to form a first layer electrode, and after removing the second resist layer, a third resist layer is etched in a region where one end spans the first layer electrode and the other end is in the middle of the first layer electrode gap.
After patterning the resist layer, a second impurity is implanted into the semiconductor substrate surface using the third resist layer and the first layer electrode as a mask, and after removing the third resist layer,
A method for manufacturing a charge transfer device, characterized in that a second layer electrode is patterned on the semiconductor substrate in the first layer electrode gap region with an insulating film interposed therebetween.