JPH0368217A - Variable frequency oscillator - Google Patents

Abstract

PURPOSE:To shorten the frequency switching time and to reduce the power consumption by providing a voltage holding means including a sample hold circuit where a voltage holding capacitor is connected to the output of a D/A converter. CONSTITUTION:A control voltage VS supplied to a voltage control oscillator 5, an output voltage VF of a loop filter 3, and an output voltage VSH of a sample hold circuit 9 have relations VS=VF+VSH. When the voltage VS corresponding to a desired frequency is applied from a D/A converter 8 through the circuit 9, the voltage VF is kept at 0V independently of the output frequency. Consequently, the transient response for frequency switching is reduced to shorten the frequency switching time. A control circuit 7 stops the power supply to the D/A converter 8 after the circuit 9 holds an output voltage VDA of the D/A converter 8. The change of the voltage VDA at this time is prevented from being transmitted to a PLL, and the power consumption is reduced by the stop of power supply.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a variable frequency oscillator using a phase-locked loop. In particular, in order to shorten the frequency switching time, the control voltage of the voltage controlled oscillator is converted to a digital-to-analog converter (hereinafter referred to as r).
This invention relates to a variable frequency oscillator configured to be supplied directly from a D/A converter.

The present invention is suitable for use in a local oscillator of a wireless device.

The present invention provides voltage holding means at the output of the D/A converter to shorten the operating time of the D/A converter and reduce power consumption.

[Conventional technology]

Traditionally, phase-locked loops (
A PLL frequency synthesizer using a PLL (PLL) is used. Since the PLL frequency synthesizer can set the output frequency with high precision, it is used as a local oscillator in wireless devices. However, since the PLL is a negative feedback loop, the frequency switching time may become long under certain conditions. In order to solve this problem, a configuration is known in which a D/A converter is used to directly supply the control voltage of the voltage controlled oscillator. This will be explained in detail below.

FIG. 9 is a block diagram of a conventional variable frequency oscillator using a PLL frequency synthesizer.

The PLL frequency synthesizer includes a reference oscillator 1, a phase comparator 2, a loop filter 3, a voltage controlled oscillator 5, and a variable frequency divider 6. The output signal of the voltage controlled oscillator 5 is divided into 1/N by a variable frequency divider 6, and a control voltage is set such that the phase difference between the output signal of the variable frequency divider 6 and the output signal of the reference oscillator 1 is zero. is applied to the voltage controlled oscillator 5. Thereby, if a highly stable oscillator such as a temperature compensated crystal oscillator is used as the reference oscillator 1, the output layer wavenumber stability of the voltage controlled oscillator 5 can also be made highly stable. Further, the output frequency can be selected by changing the frequency division ratio N.

In such a PLL frequency synthesizer, frequency switching time may become a problem. In particular, there are cases where it is required to switch frequencies at high speed. PLL is a negative feedback loop, which causes transient phenomena when switching frequencies,
It takes a certain amount of time to reach the target frequency.

This time will hereinafter be referred to as "frequency switching time".

In order to reduce the frequency switching time, a variable frequency oscillator combining a PLL and a D/A converter 8 has been considered, as shown in FIG. This is to apply the control voltage V of the voltage controlled oscillator 5 directly from the D/A converter 8. This allows the frequency to be switched at high speed.

The output voltage of the loop filter 3 on the PLL side is Vp.

The output voltage of the D/A converter 8 is V. A, the control voltage V is set by the adder circuit 4 as follows: Vs = VF fVDA.

Figure 10 shows the output frequency as f. A timing chart when switching from l to f02 is shown.

Here, the frequency division ratios N corresponding to the frequencies fil and rot are respectively Nl5N2, and the corresponding voltages vDA are respectively VOAI s VDA2. When switching frequencies,
The frequency division number N and voltage VDA are simultaneously set as shown in FIG. At this time, the output voltage V of the loop filter 3 does not change (VF-0), so transient phenomena are less likely to occur and the frequency switching time can be shortened.

Note that the voltage controlled oscillator 50 control voltage V during steady state.

Although the relationship between V
changes, and the output frequency remains constant.

In this way, in a variable frequency oscillator where the output frequency of the voltage controlled oscillator is stabilized by the negative feedback loop of the PLL, the frequency can be adjusted quickly by directly setting the control voltage of the voltage controlled oscillator from the D/A converter. can be switched.

[Problem to be solved by the invention]

However, variable frequency oscillators using D/A converters have problems in terms of power consumption and phase noise characteristics.

When a variable frequency oscillator is used in a small portable wireless device, it is desirable that its power consumption be as low as possible. However, in the conventional example shown in Fig. 9, the D/A converter is used only when switching frequencies, so if the power supply to the D/A converter can be stopped during normal operation when frequency switching is not performed, power consumption can be saved. can. However, when the power supply is stopped,
The voltage Vt1A changes stepwise, and the output frequency fluctuates greatly. Therefore, it is impossible to stop the power supply to the D/A converter, and there is a limit to reducing the power consumption of the variable frequency oscillator.

Furthermore, in the conventional example shown in FIG. 9, the output voltage of the D/A converter is directly applied as a control voltage to the voltage controlled oscillator through the adding circuit. Therefore, noise from the D/A converter is added to the PLL. If the closed loop bandwidth of the PLL is made wide enough, the noise from the D/A converter can be suppressed by the PLL. However, when the frequency division ratio is extremely large, such as in a synthesizer for mobile communication, the closed loop bandwidth cannot be made so wide, and the noise of the D/A converter is not suppressed but is added to the voltage controlled oscillator. Therefore, the phase noise characteristics of the variable frequency oscillator deteriorate.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and provide a variable frequency oscillator with short frequency switching time, low power consumption, and low phase noise.

[Means to solve the problem]

The variable frequency oscillator of the present invention includes voltage holding means for holding the output voltage of the D/A converter, and after this means holds the output voltage of the D/A converter, power supply to the D/A converter is stopped. It is characterized by comprising means for stopping.

The voltage holding means preferably includes a sample and hold circuit connected to a voltage holding capacitor.

In addition, a resistor is connected in parallel to the voltage holding capacitor, and after the output voltage of the D/A converter is held during frequency switching, the output voltage is transferred to the sample and hold circuit after a time longer than the time constant CR determined by the capacitor and the resistor has passed. It is also possible to have a configuration in which the power supply is stopped.

Furthermore, as a voltage holding means, a first switch whose one end is connected to the output of the D/A converter, and a first resistor connected between the other end of the first switch and a ground point; A capacitor with one end connected to the connection point between this first resistor and the first switch, a second resistor connected between the other end of this capacitor and the ground point, and a second resistor connected in parallel with this resistor. When switching the frequency with the connected second switch, the D/A
While the converter is outputting voltage, open the first switch, close the second switch, and after holding the output voltage of the D/A converter, turn the first switch on, and then turn on the second switch. It may also include control means for opening.

[For production]

The output voltage of the D/A converter is held by a sample and hold circuit, and then power supply to the D/A converter is stopped. As a result, power supply to the D/A converter can be stopped during steady state without fluctuations in the output frequency.

Additionally, if a resistor is connected in parallel to the voltage holding capacitor of the sample-and-hold circuit, its output voltage will gradually decrease, but the output frequency of the voltage-controlled oscillator will not fluctuate due to the PLL effect. .

Therefore, when the holding voltage of the sample-and-hold circuit becomes substantially zero, the power supply to this circuit can be stopped.

The voltage can also be maintained by providing an output circuit consisting of a capacitor, a resistor, and a switch at the output of the D/A converter and opening and closing the switch at regular timing. In this case as well, the held voltage gradually decreases, but the output frequency of the voltage controlled oscillator is not affected.

〔Example〕

FIG. 1 is a block diagram of a variable frequency oscillator according to a first embodiment of the present invention.

This oscillator includes a voltage controlled oscillator 5, a reference oscillator 1 that supplies a control voltage to the voltage controlled oscillator 5 to stabilize its output frequency, a phase comparator 2, a loop filter 3, a variable frequency divider 6, and a voltage controlled oscillator 5. A control circuit 7 that outputs a voltage corresponding to the frequency after switching when the output frequency of the controlled oscillator 5 is switched via the D/A converter 8, and an adder circuit that adds the output of the D/A converter 8 to the control voltage. 4. Adder circuit 4 is connected between loop filter 3 and voltage controlled oscillator 5.

Here, the feature of this embodiment is that the D/A converter 8
A sample-and-hold circuit 9 holds that voltage at the output of
The control circuit 7 is equipped with a sample/hold circuit 9 that is D/
The present invention includes means for stopping power supply to the D/A converter 8 after maintaining the output voltage of the A converter 8. A voltage holding capacitor lO is connected to the sample and hold circuit 9.

The relationship between the control voltage V supplied to the voltage controlled oscillator 5, the output voltage V of the loop filter 3, and the output voltage V5H of the sample-and-hold circuit 9 is Vs = Vp +
Vs.

becomes. When a voltage V corresponding to the desired frequency is applied from the D/A converter 8 via the sample-and-hold circuit 9,
The voltage VF can be kept constant (OV) regardless of the output frequency. Therefore, the transient response during frequency switching is reduced, and the frequency switching time is shortened.

FIG. 2 shows the timing of each signal when switching the output frequency from .1 to f02.

Output frequency f. , and f02 are respectively Nl and N2, and the output voltage of the D/A converter 8 corresponding to these frequencies is VDAI s VDA2. Before frequency switching, power supply to the D/A converter 8 is stopped. Further, the output voltage V, □ of the sample-and-hold circuit 9 is VDAI. The frequency switching procedure is as follows.

■ First, start supplying power to the D/A converter 8, and
The output voltage of converter 8 is V. Set to A2.

■ Change the sample/hold circuit 9 from hold mode to sample mode. As a result, the output voltage V, □2 of the sample-and-hold circuit 9 becomes VDA2, and the output frequency of the voltage controlled oscillator 5 becomes f. Changed to 2. At the same time, the frequency division ratio is changed from N to N2.

■ Change the sample/hold circuit 9 from sample mode to hold mode.

■ Stop power supply to the D/A converter 8.

In this procedure, the sample-and-hold circuit 9 is placed in the hold mode in step (■), so stepwise changes in the voltage VDA when the power supply to the D/A converter 8 is stopped can be prevented from being transmitted to the PLL. , no frequency fluctuations occur due to changes in VDA. Therefore, the power supply to the D/A converter 8 can be stopped, power consumption can be reduced, and an increase in phase noise of the frequency synthesizer output due to noise from the D/A converter 8 can be prevented.

FIG. 3 shows the block configuration of the variable frequency oscillator according to the second embodiment of the present invention.

This embodiment has a resistor 1 in parallel with the voltage holding capacitor 10.
1 is connected, and the power supply to the sample and hold circuit 9 can be stopped, which is different from the first embodiment.

In a typical sample-and-hold circuit, a capacitor with a small tan δ is used as a voltage holding capacitor in order to improve droop characteristics. However, in the case of this example,
A resistor 11 is connected to increase tan δ.

Figure 4 shows the output frequency as r. The timing of each signal when switching from l to f02 is shown.

In this case, as in FIG. 2, the output frequency f. l and f0
Let the frequency division ratios corresponding to 2 be Nl and N2, respectively. Before frequency switching, the D/A converter 8 and the sample
Power supply to the hold circuit 9 is stopped. Also,
The output voltage V, □ of the sample-and-hold circuit 9 is VSM=0 because its power supply is stopped. The frequency switching procedure is as follows.

(2) First, power supply to the D/A converter 8 and sample/hold circuit 9 is started, and the output voltage of the D/A converter 8 is set to the frequency f. Voltage controlled oscillator 5 corresponding to I and ".2
The change in control voltage is set to ΔVDA. The power supply control for each of the D/A converter 8 and the sample/hold circuit 9 is performed separately as shown in (6) of FIG.

■ Change the sample/hold circuit 9 from hold mode to sample mode. As a result, the output voltage V, □ of the sample-and-hold circuit 9 becomes VDA, and the output frequency of the voltage controlled oscillator 5 is changed to f02. At the same time, the frequency division ratio is changed from N to N2.

■ Change the sample/hold circuit 9 from sample mode to hold mode. Since the resistor 11 is connected to the voltage holding capacitor IO, its output voltage VS)I gradually decreases after changing to the hold mode. However, P
Due to the effect of LL, the output voltage vF of the loop filter 3 becomes V
The output frequency remains constant as it compensates for the decrease in SH.

■ Stop the power supply to the D/A converter 8. At this time, even if there is a change in the output voltage VDA of the D/A converter 8,
Since the sample/hold circuit 9 is in the hold mode, changes in VDA are not transmitted to the PLL. Therefore, no variation in output frequency occurs.

■ Stop the power supply to the sample-and-hold circuit 9 when there is no longer any change in VSO. In this case, V3
Since H is zero [V], even if the power supply to the sample-and-hold circuit 9 is stopped, changes in V and □ will not be transmitted to the PLL, and the output frequency will not fluctuate.

In this procedure, if VSH is changed as in step (2), there is no need to maintain the output voltage of the D/A converter 8 by the sample-and-hold circuit 9 during steady state. However, if the decreasing speed of VSll is fast, the PLL cannot follow it, so the capacitance C of the voltage holding capacitor 10 and the resistor 11
The time constant determined by the resistance value R must be selected within a range that can be followed by the PLL.

If frequency switching is performed in accordance with the above procedure, the same effects as in the first embodiment can be obtained in this embodiment, and furthermore, since the power supply to the sample-and-hold circuit 9 can be stopped, power consumption can be further reduced. It becomes possible to

FIG. 5 is a block diagram showing a part of a variable frequency oscillator according to a third embodiment of the present invention. This embodiment differs from the second embodiment in that a voltage holding capacitor 10 and a resistor 11 are grounded via a reference voltage source 12. Since the other parts are the same as the second embodiment, only the essential parts are shown in FIG.

In the second embodiment, the output voltage of the D/A converter 8 was a change in control voltage ΔVI]^ corresponding to the frequency switching width. Therefore, ΔV[IA may become a negative voltage. In that case, it is necessary to prepare a negative power supply within the device.

On the other hand, in the third embodiment, the reference potential of the sample-and-hold circuit 9 is raised by V[15] by the reference voltage source 12. If the maximum absolute value of ΔVDA in the second embodiment is ΔvmaM, if VH2 is selected so that V HS≧ΔV□8, there is no need to prepare a negative power supply.

In this embodiment, the output voltage of the D/A conversion circuit 9 is
The value in the second embodiment is V! It is the sum of Is.

FIG. 6 shows a block diagram of a variable frequency oscillator according to a fourth embodiment of the present invention.

In this embodiment, as the voltage holding means, the switch Sl,
S2, resistor Rz, R2, and capacitor C include a D/A output circuit 13.

The output of the D/A converter 8 is connected to one end of a capacitor C via a switch Sl. The other end of capacitor C is D/
It is connected to the adder circuit 4 as the output of the A output circuit 13.

A connection point between the switch S1 and the capacitor C is grounded via a resistor R1, and the other end of the capacitor C is grounded via a resistor R2. A switch S2 is connected in parallel with the resistor R2.

Figure 7 shows the output frequency as f. 1 to f. The timing of each signal when switching to 2 is shown.

In this case as well, as in FIGS. 2 and 4, the output frequency f. l and f. Let the division ratios corresponding to 2 be N, , N2, respectively.
shall be. Before frequency switching, power supply to the D/A converter 8 is stopped. Further, in the initial state of the D/A output circuit 13, the switch S1 is opened, the switch S2 is closed, and the voltage across the capacitor C is zero [v]. therefore,
Output voltage V of the D/A output circuit 13. An is zero (V). The frequency switching procedure is as follows.

■ First, start supplying power to the D/A converter 8, and
The output voltage of the A converter 8 is set to the frequency f. I and r. The control voltage change amount ΔVDA corresponding to 2 is set.

■ Open switch S2 and close switch S1.

At this time, the output voltage VIIAO of the D/A output circuit 13 temporarily becomes ΔVDA, then gradually decreases, and finally becomes zero [V]. However, due to the effect of PLL, the output voltage V of the loop filter 3.

compensates for the decrease in VDAO, so the output frequency remains constant.

■ When V DAO becomes zero [V], switch S
2 is closed, switch S1 is opened, and power supply to the D/A converter 8 is stopped. At this time, the potential across the capacitor C is ΔVDA, but it is gradually discharged by the resistor R8 and eventually becomes zero [V], returning to the initial state.

If you turn off the power to the D/A converter 8 as described above,
Changes in VDA are not transmitted to the PLL, and output frequency fluctuations do not occur.

This embodiment provides the same effects as the first and second embodiments, and also simplifies the circuit configuration since no sample-and-hold circuit is required.

The operation timing of switches S1 and 82 is shown in FIG.
f), (It is desirable that the deviation is as shown in (),
They may be opened and closed simultaneously (complementarily). In the circuit shown in FIG. 6, the same control signal is sent directly to the switch 31,
The power is supplied to the switch S2 through the inverter 14, and the two switches 31 and 32 open and close at the same time.

FIG. 8 is a block diagram showing a part of a variable frequency oscillator according to a fifth embodiment of the present invention. In this example, the resistances R,,
This embodiment differs from the fourth embodiment in that R and switch S2 are grounded via a reference voltage source 12. Since the other parts are the same as the fourth embodiment, only the essential parts are shown in FIG.

In the fourth embodiment, the output voltage of the D/A converter 8 was a change in control voltage AVDA corresponding to the frequency switching width. Therefore, ΔVoA may become a negative voltage.

In that case, it is necessary to prepare a negative power supply within the device.

On the other hand, in the fifth embodiment, the reference potential of the sample-and-hold circuit 9 is raised by VIIS by the reference voltage source 12. The maximum absolute value of AVDA in the second embodiment is ΔV. 8, if VIIS is selected so that V B s≧ΔV0, there is no need to prepare a negative power supply.

In this embodiment, the output voltage of the D/A conversion circuit 9 is
This is the value obtained by adding V8S to the value in the fourth embodiment.

〔Effect of the invention〕

As explained above, the variable frequency oscillator of the present invention has D
By setting the control voltage of the voltage controlled oscillator via the /A converter, high-speed frequency switching is possible.
Use the /A converter only when switching frequencies, and set the PL at steady state.
Separate from L. This has the effect of reducing power consumption and making it possible to ignore noise generated from the D/A converter.

The present invention is particularly effective when used as a frequency synthesizer for small mobile radio devices that require low power consumption and low phase noise.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a variable frequency oscillator according to a first embodiment of the present invention. Figure 2 is a timing chart when switching frequencies. FIG. 3 is a block diagram of a variable frequency oscillator according to a second embodiment of the present invention. FIG. 4 is a timing chart when switching frequencies. FIG. 5 is a block diagram showing a part of a variable frequency oscillator according to a third embodiment of the present invention. FIG. 6 is a block diagram of a variable frequency oscillator according to a fourth embodiment of the present invention. FIG. 7 is a timing chart when switching frequencies. FIG. 8 is a block diagram showing a part of a variable frequency oscillator according to a fifth embodiment of the present invention. FIG. 9 is a block diagram of a conventional variable frequency oscillator. FIG. 10 is a timing chart at the time of frequency switching. ■... Reference oscillator, 2... Phase comparator, 3... Loop filter, 4... Adder circuit, 5... Voltage controlled oscillator, 6... Variable frequency divider, 7... Control circuit, 8...
・D/A converter, 9...sample/hold circuit, 1
0... Voltage holding capacitor, 11... Resistor, 12...
...Reference voltage source, 13...D/A output circuit, 14...
・Inverter.

Claims (1)

[Claims] 1. A voltage controlled oscillator; circuit means for supplying a control voltage to the voltage controlled oscillator to stabilize its output frequency; In the variable frequency oscillator, the variable frequency oscillator is equipped with means for outputting a voltage via a digital-to-analog converter, and an addition circuit for adding the output of this means to the control voltage, wherein the outputting means comprising a voltage holding means for holding the voltage at the output of the digital-to-analog converter, and a means for stopping power supply to the digital-to-analog converter after the voltage holding means holds the output voltage of the digital-to-analog converter. A variable frequency oscillator featuring: