JPH036746A - Information processor - Google Patents

Abstract

PURPOSE:To reduce the capacity of a conversion table and to decrease the number of logical gates forming the conversion table by producing a secondary scan address based on the conversion unit identification information given to a primary scan address. CONSTITUTION:A primary scan address set to an address register 1 is sent to a conversion unit identifying device 5. Thus the conversion unit identification information is checked and a conversion unit is decided. An address conversion table 4 is retrieved based on the conversion unit, and a secondary scan address is read out of the table 4. The secondary scan address is set to an output address register 19 and sent to an address group. Thus it is possible to produce a conversion table with only the memory elements which hold the information requiring the conversion of scan addresses. As a result, the capacity of the table 4 is reduced and the number of logical gates forming the table 4 is also decreased.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a scanning method for an information processing device.

In particular, the present invention relates to a scan method featuring scan address conversion.

[Conventional technology]

In the conventional scanning method, as described in Japanese Patent Application Laid-Open No. 59-161744, a conversion table is indexed according to a logical scan address during a scan operation to obtain a plurality of physical scan addresses in bit units.

[Problem to be solved by the invention]

In this type of conversion method for scan addresses fixed in 1-bit units, one pair of conversion tables is required for each bit of each latch, so a huge amount of conversion tables is required for the entire information processing device. This has the disadvantage that the logical scale of the table increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a scan method that reduces the amount of a conversion table used for converting scan addresses during a scan operation, and reduces the number of logic gates constituting the conversion table to one.

[Means to solve the problem]

The present invention includes a conversion unit identification device in the scan address conversion mechanism, and conversion unit identification information on the input side to the scan address conversion mechanism - next scan address, so that during scan operation, the - next scan address is set as the secondary scan address. When converting, the conversion unit identification device examines the conversion unit identification device information added to the primary scan address, determines the conversion unit, and generates a secondary scan address based on the conversion unit.

[Effect]

During a scan operation, when converting a scan address from a -next scan address to a secondary scan address, the conversion unit identification information is checked by a conversion unit identification device to determine the conversion unit. After determining the conversion unit, the conversion table is indexed based on the conversion unit to obtain a secondary scan address. In this way, scan address conversion from the next scan address to the secondary scan address is performed in conversion units based on the conversion unit identification information, so a conversion table can be created for each conversion unit, and the number of conversion tables is can be determined by the type and size of the conversion unit.

〔Example〕

FIG. 1 shows a block diagram of one embodiment of the invention.

In the figure, 1 is an address register in which the -next scan address is set. 2 is a data register in which 1 byte of scan-in data is set during scan-in operation. 3 is an address translation mechanism, which includes an address translation table 4,
It consists of a conversion unit identification device 5, an address selector 6, an address selector 7, a scan-in data selector 8, a scan-out data selector 9, a scan-out data register 10, and a selector control section 20. The address conversion table 4 has a function of inputting the primary scan address of the address register 1 and converting it into a secondary scan address.

FIG. 2 shows the scan address conversion process and the format of the address conversion table 4.

Register 1 has the same contents as address register 1 in FIG.
In this embodiment, the primary scan address consists of 2 bits of conversion unit identification information and 19 bits of the scan address section. The conversion unit identification information consists of the following bit configuration.

Bit O: When set to '1', scan address conversion is performed in the conversion unit indicated by bit 1.

When it is 0', scan address conversion is not performed.

When bit 1 bit O is 1', it is valid, and when this bit is 0', bit-by-bit address conversion is performed. When this bit is 1', address conversion is performed in byte units. −
The upper 16 bits of the scan address part of the next scan address are one word per 8 bits to specify a memory element that holds logically meaningful information, for example, eight pieces of information that make up one byte, as one information unit. In this example, 16 bits or 64 words (K, , 1024) are assigned.
scan addresses can be assigned.

The lower three bits of the scan address section indicate the bit position within the scan address.

The address conversion table 4 is composed of a bit-by-bit conversion part part and a byte-by-byte conversion part part. In this embodiment, the address conversion table consists of 16 pairs (K=1024 ) is prepared, and consists of a pair in the bit unit conversion part 12 and a pair in the byte unit conversion part 4.

Next, the scan address conversion process will be explained. The primary scan address set in the address register 1 is sent to the conversion unit identification device 5 and the conversion unit identification information is checked. As a result of the inspection, bit O of the conversion unit identification information is 0.
', the scan address part of the primary scan address is directly set as the secondary scan address from the conversion unit identification device 5 to the output address register 19 without indexing the address conversion table 4, and the address register group shown in FIG. Sent to 6. The scan control unit 11 sequentially increments the lower 3 bits of the scan address part in the conversion unit identification device 5 by 1 to obtain a value in which the lower 3 bits of the primary scan address are updated without using the 8-bit secondary scan address). At the same time, it is sequentially stored in the address register 6 specified by the lower three bits.

Next, bit O of the conversion unit identification information is 1' and bit 1 is 0.
The conversion process of the primary scan address which is ′ will be described below. The conversion unit identification information is checked by the conversion unit identification device 5, and if the inspection result is as above, the lower 14 bits of the scan address part of the primary scan address are sent from the conversion unit identification device 5 to the address conversion table 4 and used as an index address. As a result of indexing the bit-by-bit conversion part of the address conversion table 4, the secondary scan address is read from the address conversion table 4, and the output address register 19
address register group 6. The scan control unit 11 sequentially adds 1 to the lower three bits of the scan address part in the conversion unit identification device 5, indexes the address conversion table 4, reads out the secondary scan address, and obtains the secondary scan address for 8 bits. At the same time, the process of converting the primary scan address in which bit 0 of the conversion unit identification information is 1' and bit 1 is 1' after the lower three bits are set will be described. The conversion unit identification device 5 checks the conversion unit identification information, and if the check result is the above (byte unit conversion), the conversion unit identification device 5 outputs bit position information to shift the scan address part of the primary scan address to the right by 3 bits. 1' in the most significant 2 bits of the lower 14 bits of that value.
is added and sent to the address conversion table 4, where it is used as an index address. As a result of indexing the byte unit conversion part of the address conversion table 4, the secondary scan address is read from the address conversion table 4, and the bit position information sent by the conversion unit identification device 5 is added to the output address register 19 and set. and sent to the address register group 6. The scan control unit 11 sequentially increments the lower 3 bits of the scan address field in the conversion unit identification device 5 by 1 to obtain an 8-bit secondary scan address (without performing a new index for 4 byte unit conversions, The bit position information sent from the conversion unit identification device 5 is added to the secondary scan address read from the address conversion table 4 and set to 0), and at the same time, it is sequentially stored in the address register 6 specified by the lower three bits.

The secondary scan address is the module part 5-bit LSi
The data is divided into 7 bits in the BYTE part, 4 bits in the BYTE part, and 3 bits in the T part, and used for control. Setting each bit number is
This is not the essence of the invention and can be easily modified. Now, the module part indicates the module number constituting this logic, and in this embodiment, it is composed of 32 modules or less, so it is 5 bits. The LSi section indicates the LSi number within each module. In this embodiment, up to 128 LSis can be defined. BYTE Department, B
The iT section is a section for specifying the bit number of the flip-flop in each LSi, and each is a byte.

represents a bit. Flip-flops of up to 128 bits can be defined in each LSi.

The address register group 6 is composed of eight registers and stores eight secondary scan addresses created for the address conversion tape 4 and the conversion unit identification device 5, respectively. Reference numeral 11 denotes a scan control unit, which transfers data from the address register group 6 and data register 2 to each set of address registers and data using the address selector 7 and scan data selector 8 according to the designation of the selector control unit 20 in the address conversion mechanism 3. The selected addresses are sequentially selected and received in the register 21. The scan control unit 11 decodes the 5 bits of the module part of the secondary scan address using the decoder 23, and sends a permission signal to the module specified by the address of the module part. In addition, addresses other than the module section are shared by the scan address bus 201 for each module.
The data is output to the scan-in data line 202.

The scan-out data is output to the scan-out data line 203 from the memory element that holds the information specified by the module permission signal and the scan address bus 201, and is selected by the scan-out data selector 9 according to the instruction from the select control section 20 and scanned out. The selected bit position of data register 10 is set.

〔Effect of the invention〕

According to the present invention, since it is possible to create a conversion table only for memory elements that hold information that requires scan address conversion,
It is possible to reduce the amount of the conversion table and to greatly reduce the number of logic gates that constitute the conversion table.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a detailed diagram of the address translation table section shown in the figure. 1... Address register, 2... Data register, 3
. . . address conversion mechanism, 4 . . address conversion table, 5 . . . conversion unit identification device, 11 . . . scan control unit.

Claims (1)

[Claims] 1. A unique scan address is assigned to a memory element that retains information in an information processing device, and a predetermined value is assigned to the memory element that retains specific or arbitrary information by a scan operation that is independent of normal logical operation. In a scan method that performs scan-in and scan-out, a conversion mechanism converts a primary scan address assigned to a storage element that holds the above information into a secondary scan address, performs a scan operation using the secondary scan address, and converts the A conversion unit identification device is provided in the device, and when converting a primary scan address into a secondary scan address, the conversion unit is determined based on conversion unit identification information provided in the primary scan address, and a secondary scan address is generated based on the conversion unit. Characteristic information processing device.