JPH036593A - Video display device - Google Patents

Abstract

PURPOSE:To display plural video signals on one display by providing means which compare set display order, one raster control means for displaying picture element data in a window and a setting means for the background on the display. CONSTITUTION:This device is provided with the means 4 - 6 which compare the set display order, the one raster control means 7 which displays in-window picture element data on one display and the setting means 3 for the background on the display 30. Further, bit map raster memories which are as many as windows are provided, and those window memories 4 - 6 are provided with a priority registers and offset registers which indicate the display start positions of the windows on the display are provided so that priority order for respective displays is generated. Consequently, plural moving image windows can be displayed on one display 30.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is useful for handling multiple images by a computer, displaying multiple images of the same signal standard on one display, or displaying images of different signal standards at the same time. The present invention relates to a video display device for displaying images.

BACKGROUND OF THE INVENTION In the past, various video signal standards have been created, and the appropriate one has been selected depending on the situation, depending on the advantages and disadvantages of each. However, until now, the principle that there is only one television broadcasting standard within a country has been adhered to. However, in recent years, television broadcasting using video signal standards that are incompatible with conventional broadcasting standards such as HD TV is being carried out. in this case,
Although it is anticipated that HDTV displays will be able to display traditional broadcast standards, the price of HDTV displays will inevitably be prohibitive.

Conventionally, for displaying multiple moving images on one screen,
Pictures seen on VTRs, television receivers, etc.
There is an in-picture function (hereinafter referred to as PIF).

Although this is intended to be different from the purpose of the present invention,
Since the display effects are very similar, this PIF will be explained below.

FIG. 7 is a block diagram showing the configuration of a display device having 212 functions, and FIG. 8 is a diagram showing an example of a typical PNP display.

In FIG. 8, in PIF, two video signals are generally displayed on one screen at the same time, and these two images are always positioned as one main screen and the other sub screen.

Next, the conventional technique will be explained with reference to FIG. Two systems of NTSC video signals are input to this device.
These become inputs to the main screen system and sub screen system circuits, respectively. Further, by switching between these using a switch 711, the main screen and sub screen can be exchanged. Here, the video signal input to the main screen system will be referred to as the main video signal, and the video signal input to the sub screen system will be referred to as the sub video signal. In Figure 7, 70
1゜706 is a synchronization separation circuit that separates the synchronization signal from the input video signal, 7o5 is a dual port frame memory for storing the video signal, and 702゜707 is a dot clock that is synchronized with the separated synchronization signal. 7o3 is a read address generation circuit that generates a memory read address based on the dot clock generated by the PLL circuit 702, and 708 is a PLL circuit.
A write address generation circuit generates a memory write address based on the dot clock generated by the circuit 707, 704 is a video switching circuit that switches two video signals at the switching timing from the timing generator 712, and 709 is a synchronously separated video signal. 710 is a D/A converter that converts the digital data from the memory 705 into analog conversion; 712 is a D/A converter that converts the sub-picture signal into digital data; This is a timing generator that generates switching signals for video signals.

First, the operation of the main screen system will be explained. The input video signal passes through a synchronization separation circuit 701, and further passes through a video switching circuit 70.
This is one input of 4. The separated synchronization signal is guided to PLL circuit 702, where a dot clock is generated. The generated dot clock is distributed to read address generation circuit 703 and timing generator 712.

The read address generation circuit 703 has a frame memory 705.
It creates an address signal and memory control signal group for reading out the image data stored in the memory 705.
/A converter 710.

At this time, the signal converted into analog by the D/A converter 710 is completely synchronized with the main screen input video signal.
This signal becomes another input to the video switching circuit 704. Therefore, the switching timing signal provided by the timing generator 712 will not disturb the synchronization of the output signal, no matter what timing the switching is performed.

Next, the operation of the sub-screen system will be explained. The input video signal passes through a sync separation circuit 706, is further guided to an A/D converter 709, and is converted into digital data. The synchronization signal separated by the synchronization separation circuit 708 is sent to the PLL circuit 70.
7, a dot clock for data writing is created. The write address generation circuit 708 generates a write address to the frame memory 705 and a group of memory control signals based on this dot clock, and generates the A/D converter 0.
The digital data from 9 is written to the memory.

As mentioned earlier, PIP consists of two screens: a main screen and a subscreen. Therefore, the sub-screen must be considerably smaller than the main screen, that is, it must be displayed in a reduced size. For this purpose, the address generation circuit is configured to appropriately thin out read or write addresses, that is, divide the dot clock to generate addresses. Generally, since it has an advantage in terms of memory capacity, the screen is reduced by thinning out the write addresses.

Problems to be Solved by the Invention As mentioned above, with conventional display devices, it is difficult to handle functions such as overlapping and multi-window display by a computer, and it is difficult to display still images and text information on the same screen. Can not.

Moreover, it is also impossible to display video signals of different standards on one display.

The present invention enables a computer to handle such multiple video signals while displaying a relatively inexpensive high-resolution C display, such as a display for a personal computer, regardless of whether the signal standards are compatible or not.
An object of the present invention is to provide a video display device that can display images on RT.

Means for Solving the Problems In order to solve the above-mentioned problems, the video display device of the present invention has the following features:
a plurality of conversion means for converting an input video signal into pixel data; a plurality of storage means for storing the pixel data in a storage device;
a plurality of writing means for writing the pixel data into the storage device; a plurality of reading means for reading the pixel data stored in the storage device; a plurality of setting means for setting the size of each window; a plurality of specifying means for specifying the display position on the display for each window;
a plurality of order setting means for setting the display order of the window in relation to other windows for each window, and one display order comparison means for displaying according to the set display order; One raster control means for displaying the pixel data in the window on one display, and a background setting means for setting the background to be displayed on the display, It can be displayed on one display as an image within a window.

Function: With this configuration, the display device has a plurality of BITMATSU plaster memories (window memories) corresponding to the number of windows, and also has a priority register so that each of these window memories can be prioritized for display. and an offset register indicating the display start position of the window on the display. Therefore, the host computer can display a plurality of moving image windows on one display regardless of the input video signals, with little regard to how the windows overlap.

EXAMPLES Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a diagram showing one embodiment of the present invention.

In FIG. 1, 1 is a host computer for controlling the display device of the present invention, and 2 is this computer 1.
30 is a CRT display capable of responding to the output of display device 2. Here, the host computer 1 may be any known device as long as it can generate or read the input/output signal group of the display device 2. In addition, the CRT display 30 has a display bag W.
Any display may be used as long as it can input the signal 27 output by t2.

Display bag fl! 2 is a 1024x900 resolution bitmap display with a 4:3 screen aspect ratio, capable of full color (8 bits each of R, G, and B) and presenting up to three independent windows. It is made so that you can. Therefore, the aspect ratio per pixel is 1:1. The display device 2 includes background color data 15, a background register 3 in which lowest level priority data 14 corresponding to the background is set, and a window memory 4 for controlling windows. 5. 6, a raster control circuit 7 that applies a video address signal 18.17 to the window memory and converts the signal 15 output from the window memory into a video signal 27, and input video signals 24, 25.28.
8. A/D conversion circuit that converts the data into digital data. 9.
10, and a CPU control bus tt of the host computer 1.

It is connected to the CPU address bus 12 and the CPU data bus 13, and includes a background register 3 and a window memory 4. 5. 6 are connected in cascade through a video data bus 15 and a priority bus 14, respectively.

FIG. 2 is an example of multi-window display performed by the display device of this embodiment. In the figure, the display address is set to 0 at the lower left corner of the screen, the horizontal direction is set to the X axis, and the vertical direction is set to the Y axis. Window 1 in FIG. 2 is displayed in the window memory 4 in FIG. 1, and similarly, window 2 is displayed in the window memory 5, and window 3 is displayed in the window memory 6. In this display example,
Window 1 is displayed to the fullest extent, that is, it is set to have the highest priority. As mentioned above, the background has the lowest priority, so window 1 has the highest priority, followed by window 2. Window 3. In order of background.

Next, the operation of each part of the display device of this example will be explained.

FIG. 3 is a diagram showing the configuration of the window memory. 3
01 is a priority register for setting the display order of windows, and the value 255 is determined to have the highest priority.

In this example, since there are four types of data to be compared,
Although a width of 2 bits would be sufficient, the width was set to 8 bits in order to match the width of other buses. This is optional depending on the configuration, and the value 0 may be given top priority, but in this case,
It is necessary to invert the output of the priority comparison circuit. 302 is an offset register X indicating the starting position of the window in the X direction, and 303 is an offset register Y indicating the starting position of the window in the Y direction (X, Y are the coordinates of the offset position in FIG. 2). These are selected by a select signal generated by the bus control circuit and can be set by the host computer. 104 is 880
1 of the window displaying one address on the raster memory 304 in the bitmatsu plaster memory of the X512.
corresponds to a point. Furthermore, in this embodiment, the raster memory 30
4 is configured with dual port memory. One input/output port of the dual port memory is connected to the A/D conversion circuit through a window address bus and a window data bus, and the other is read-only, and the read address input from the address conversion circuit 305 allows
The data is confirmed. Is the confirmed data low cuff? It is connected to the priority control circuit 307 through the video data bus.

307 is a priority control circuit for determining priority and selecting priority data. 306 generates an enable signal for the priority control circuit 307 by comparing the offset registers 302 and 303 with the video address bus addressed by the X and Y coordinates. 305
is an address conversion circuit that converts the video data bus addressed by x, y coordinates to generate a read address for reading the raster memory.

FIG. 4 is a diagram showing the configuration of the A/D conversion circuit. 40
1 is a synchronization separation circuit that separates a synchronization signal from a video signal; 4
02 is a PLL circuit that generates a dot clock signal based on the synchronization signal separated by the synchronization separation circuit 401; 403;
404 is a write address generation circuit that generates a write address to the window memory based on the double clock generated by the PLL circuit 402, and an A/D converter 404 that converts a video signal into digital data. Note that for this part, it is necessary to prepare a different circuit for each video signal of a different standard.

FIG. 5 is a diagram showing the configuration of the raster control circuit. 50
1 is a dot clock generation circuit that generates a dot clock for this display device, and 502 is a counter that generates a video X address for this display device.

In this example, since there are 1024 dots in the X direction, 10
Use a digit binary counter. 503 is a counter that generates a video X address. Since there are 900 dots in the X direction, a 10-digit binary counter is used. 50
4 is a synchronizing signal generation circuit for generating a synchronizing signal for controlling the display, and 505 is a D/A converter that converts the video data bus signal into an analog signal according to the dot clock.

FIG. 6 is a diagram showing a priority control circuit, in which 801. E302. E103 and 804 are buffers 1 which can be switched by a gate signal, and are turned on when the gate signal is "0"5. For inputs, 801 is on the video data bus, 60 is on the video data bus.
3 is connected to a video priority path, 602 is connected to a local video data bus, and 604 is connected to a local priority bus. Also, for the output, connect 601 and 802 and use it as the output data of this circuit, and similarly, connect 601 and 802.
The outputs of 3 and 804 are connected to form the output priority of this circuit. 605 is a comparator for comparing two input priority data, and has two input terminals A and H.

Comparator E305 has an output terminal A>B that becomes 'true' if input A is greater than input B. Now, this signal is distributed to the gate terminal of buffer θ01.E!03, and , A>B signals are inverted and distributed to the gate terminals of buffers 802 and 804. In the figure,
606 is N for applying an external enable signal.
AND gate 807 is an inverter. As described above, this priority control circuit can select data with priority.

Now, returning to FIG. 1, the overall operation will be explained.

In FIG. 1, each window memory is not located in the address space of the host computer 1. - Therefore, the host combiator 1 does not need to consider differences in video data, ie, video signal standards. Furthermore, the window position can be displayed at any location on the screen by writing in offset registers X and Y. Furthermore, since the display order of windows cannot be managed by this display device, this only needs to be controlled by the host computer. However, it is only necessary to manage the display order, and there is no need to save data in hidden parts or calculate where to hide.

On the other hand, on the display device side, the raster control circuit 7 generates a video address for display. This address, in other words, hails the point on the screen that is currently displayed. Therefore, based on this address, the window control circuit of each window memory compares the offset registers X and Y with the number of dots (window size) of the image data stored in the window memory, and determines the currently displayed image data. Determine whether the point is inside the window. To determine this, the address for both the X and Y coordinates must be an offset address, that is, larger than the values of the offset registers All you have to do is find a time when the value is smaller than the sum of the values. That is, if x and y are video addresses, it is sufficient if Offset X<x<Offset X+Size X and Offset Y<y<Offset Y+Size Y. At this time, a select signal and an enable signal are sent to the raster memory and the priority control circuit, respectively. However, the offset x, yl and the size X, Y are both positive values, and furthermore, regarding the size, the condition is that the size of the raster memory, that is, in this example, both x and y do not exceed 512. .

Here, when an enable signal is sent to the raster memory, data is loaded onto the local video data bus. Now, considering the window memory 4, this data signal and the priority set are prioritized between the background register data and the priority set (generally, the data in the window memory 4 is (which has a higher priority), a pair of data with a higher priority and a priority is sent to the window memory 5. Furthermore, since the same thing is done for window memories 5 and 6,
Eventually, the output of window memory 6 will represent the maximum data at that video address point.

Therefore, the raster control circuit 7 only needs to D/A convert the data corresponding to the generated address, that is, the output from the window memory 6, to generate a video signal.

As described above, according to the display device of this embodiment, the host computer 1 can perform multi-window video display without paying any attention to window overlap, and can display video signals of different signal standards on one display. can be displayed.

Effects of the Invention As described above, according to the present invention, regardless of the video signal standard, overlapping multi-window display can be performed using a high resolution CRT without imposing a large burden on the host computer side. can.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the video display device of the present invention, FIG. 2 is a screen layout diagram showing a display example of the embodiment of the present invention, and FIG. A block diagram showing the configuration, Figure 4 is the A/D in Figure 1.
FIG. 5 is a block diagram showing the configuration of the conversion circuit, FIG. 5 is a block diagram showing the configuration of the raster control circuit in FIG. 1, FIG. 6 is a block diagram showing the priority control circuit in FIG. 3, and FIG. 7 is a conventional display. A block diagram showing the configuration of the device,
FIG. 8 is a screen layout diagram showing a typical display example of a conventional example. DESCRIPTION OF SYMBOLS 1...Host computer, 2...Graphics display device, 3...Background register, 4, 5. 8... Window memory, 7...
・Raster control circuit, 8,9.10...-A/D conversion circuit, 11...-CPU control bus, 12...
CPU address bus, 13...-CPU data bus, 14... Window priority bus, 15...
・Window data bus, 18...Window address bus X, 17-...Window address bus Y1 18,20.22-...Write address, 1
9.21.23...Video signal data, 24.25,2
θ...Input video signal, 27...Output video signal,
30... Display, 301-... Priority register, 302... Offset register X1 303... Offset register Y1304.
...Bitmatsu plaster memory, 305...Address conversion circuit, 30θ...Window control circuit,
307...Priority control circuit, 401-...
・Synchronization separation circuit, 402・-PLL circuit, 40
3...Address generation circuit, 404-A/D
Converter, 501--Dot clock generation circuit, 602--Counter, 503--Counter,
504...Synchronization signal generation circuit, 505...D/
A converter, 801. 802. 603.
804 - Axis path buffer, 805 - Comparator, 606 - NAND gate, 807 - Inverter.

Claims (2)

[Claims] (1) A display device that can display multiple windows with a constant aspect ratio and arbitrary size on the display, and can display a bitmap image composed of individual pixels within each window. Yes, a plurality of storage means for storing the pixel data in a storage device for each of the plurality of windows, a plurality of conversion means for converting the plurality of input video signals into pixel data, and writing the pixel data into the storage device. a plurality of writing means; a plurality of reading means for reading out the pixel data stored in the storage device; a plurality of setting means for setting the size of each of the windows; and displaying on a display for each of the windows. It has a plurality of specifying means for specifying the position, and a plurality of order setting means for setting the display order of the window in relation to other windows for each window, and displays according to the set display order. one display order comparison means for displaying, one raster control means for displaying the pixel data within the window on one display, and a setting means for setting a background to be displayed on the display. Display device. (2) The video display device according to claim 1, wherein the plurality of video signals are video signals of different standards.