JPH0686187A - Display device - Google Patents

Abstract

PURPOSE:To make it possible to perform a multiscreen display efficiently and with high degree of freedom in accordance with the number of screen to be displayed and the aspect ratios of the screens, etc., by arranging each TV signal for which a screen size is adjusted on a stipulated display location. CONSTITUTION:A CPU 15 switches a selection station channel for an NTSC decoder 25, reads an area designation signal E2 to be outputted from an I/O control circuit 44 and transfers it to an address generation circuit 39 after the CPU transfers the thinning ratio or interpolation ratio data A2 to be outputted from an I/O control circuit 50 to a thinning interpolation circuit 48. Subsequently, the CPU 15 switches the selection station channel for a MUSE decoder 26, reads an area designation signal E3 to be outputted from the I/O control circuit 44 and transfers it to an address generation circuit 41 after the CPU transfers the thinning ratio or interpolation ratio data A3 to be outputted from the I/O control circuit 50 to a thinning interpolation circuit 49. Thus, the size of each screen and display location are stipulated in accordance with the number of screen to be displayed and the aspect ratios of the screens, etc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION This invention is applicable to, for example, NTSC and M.
The present invention relates to a display device for selectively processing a plurality of television signals including various systems such as USE and displaying them on a display such as a CRT (cathode ray tube) or a liquid crystal projector in a multi-screen manner.

[0002]

2. Description of the Related Art As is well known, in order to display a plurality of images on a single display on a multi-screen, it has been conventionally necessary to use a screen shown in FIG.
As shown in (a), (b), (c), and (d), it is considered that one screen is divided into four screens, nine screens, 16 screens, and 12 screens of the same size ( See, for example, JP-A-1-238389).

However, in such a conventional multi-screen display means, one screen is divided into a plurality of screens of a predetermined size equal to each other. Therefore, for example, images of five types of channels are displayed on the same display. In order to display the screen, five of the nine screens shown in FIG. 16 (b) are used for image display, and the remaining four screens are not displayed. There is a problem that it is not possible to perform a multi-screen display.

The aspect ratio of the NTSC system is 4: 3.
The optimal number of divisions for equally dividing a display with
If the image is divided into 12 as shown in FIG. 16D, the aspect ratio of each divided screen becomes 1: 1 and the images on both sides of each screen are lost. There is also an inconvenience. Furthermore, recently, in addition to the conventional NTSC broadcast having an aspect ratio of 4: 3, MUSE system broadcast having an aspect ratio of 16: 9 is also added, and one screen has a plurality of equal sizes. There is a resentment that images with different aspect ratios cannot be displayed on the multi-screen by the conventional multi-screen display means for dividing the screen.

[0005]

As described above, in the conventional multi-screen display means, one screen is divided into a plurality of screens of the same size which are defined in advance. Depending on the number, efficient multi-screen display cannot be performed, the number of screen divisions is limited, and there are problems that images with different aspect ratios cannot be multi-screen displayed.

Therefore, the present invention has been made in view of the above circumstances, and is an extremely good display device capable of performing efficient and highly flexible multi-screen display according to the number of screens to be displayed, the aspect ratio of the screens, and the like. The purpose is to provide.

[0007]

A display device according to the present invention is intended for a multi-screen display of a plurality of television signals on the same display. And a defining means for defining the screen size and the display position of each television signal on the display according to the number and system of the plurality of television signals, and each television signal according to the screen size defined by the defining means. Adjusting means for selectively subjecting the screen size to thinning processing or interpolation processing, and arranging means for arranging each television signal whose screen size has been adjusted by the adjusting means at the display position defined by the defining means. Is provided.

[0008]

According to the above construction, the size and display position of each screen are regulated according to the number and system of television signals to be displayed, and the television signal of each screen is conformed to the regulation. The screen size is reduced or expanded by thinning out or interpolating, and each television signal with this screen size adjusted is placed at the specified display position. It is possible to perform efficient and highly flexible multi-screen display according to the situation.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. In FIG. 1, UHF / VHF
Each broadcast television signal is received by the antenna 11 and then selected by the tuners 12 and 13 to be converted into a baseband signal. These tuners 12,
13 is controlled by a control signal output from a CPU (central processing unit) 15 in the system controller 14 being supplied via a data bus 16 and an I / O (input / output) control circuit 17. It should be noted that these tuners 12 and 13 are used for EDTV as well as normal NTSC signals.
It also has the function of receiving and processing signals.

A BS broadcast television signal is received by an antenna 18 and then selected by a tuner 19 to be converted into a baseband signal. This tuner 1
9 is also controlled by the control signal output from the CPU 15 being supplied via the data bus 16 and the I / O control circuit 17. Note that this tuner 19 is a normal N
In addition to TSC signals and EDTV signals, it also has a function of receiving and processing MUSE signals of high-definition broadcasting.

The baseband signals output from the tuners 12, 13 and 19 are supplied to the switch circuit 20 and the system discriminating circuit 21. The system discriminating circuit 21 discriminates the type of the input baseband signal, that is, the NTSC signal or the MUSE signal. The discriminating result is the system memory 23 via the I / O control circuit 22 and the data bus 16. Written in. Further, the switch circuit 20 is operated so as to distribute the respective baseband signals output from the tuners 12, 13 and 19 to the NTSC decoders 24 and 25 and the MUSE decoder 26 and supply them. The operation of the switch circuit 20 is controlled by supplying a control signal output from the CPU 15 based on the system determination result via the data bus 16 and the I / O control circuit 27.

Here, in this embodiment, the tuner 12,
Tuners 12 and 13 are both receiving NTSC signals.
Is supplied to the NTSC decoder 24, and the tuner 1
3 is supplied to the NTSC decoder 25, the tuner 19 is receiving the MUSE signal, and its output is supplied to the MUSE decoder 26.
It is assumed that the switch circuit 20 is switching-controlled. Then, from the NTSC decoder 24, the color signals R ₁ , G ₁ and B ₁ , the clock CK ₁ and the horizontal synchronizing signal H ₁ are sent.
And the vertical synchronizing signal V ₁ are output. Also,
From the NTSC decoder 25, the color signals R ₂ , G ₂ , B ₂
And a clock CK ₂ , a horizontal synchronizing signal H ₂ and a vertical synchronizing signal V ₂ . Further, from the MUSE decoder 26, the color signals R ₃ , G ₃ , B ₃ and the clock CK.
₃ , the horizontal synchronizing signal H ₃ and the vertical synchronizing signal V ₃ are output respectively.

Of these, the color signals R ₁ , G ₁ and B ₁ are written in the time base conversion memory 28, and the clock CK ₁ , the horizontal synchronizing signal H ₁ and the vertical synchronizing signal V ₁ are written in the write address generating circuit 29. Supplied. In addition, the color signals R ₂ , G
₂ , B ₂ are written in the time base conversion memory 30, and the clock CK ₂ , the horizontal synchronizing signal H ₂ and the vertical synchronizing signal V
₂ is supplied to the write address generation circuit 31. Further, the color signals R ₃ , G ₃ , B ₃ are transferred to the time base conversion memory 3
2, the clock CK ₃ , the horizontal synchronizing signal H ₃ ,
The vertical synchronization signal V ₃ is supplied to the write address generation circuit 33.

The write address generating circuit 29 writes the color signals R ₁ , G ₁ and B ₁ in the time base conversion memory 28 based on the input clock CK ₁ , horizontal synchronizing signal H ₁ and vertical synchronizing signal V _1. To generate a write address, and the generated write address is the buffer 3
4 to the time base conversion memory 28. The write address generation circuit 31 receives the input clock C
A write address for writing the color signals R ₂ , G ₂ , and B ₂ into the time axis conversion memory 30 is generated based on K ₂ , the horizontal synchronizing signal H _2, and the vertical synchronizing signal V ₂ , and the generated writing is performed. The address is supplied to the time axis conversion memory 30 via the buffer 35. The write address generating circuit 33, based on the input clock CK ₃ , horizontal synchronizing signal H ₃ , and vertical synchronizing signal V ₃ , outputs a color signal R ₃ ,
A write address for writing G ₃ and B ₃ into the time base conversion memory 32 is generated, and the generated write address is passed through the buffer 36 to the time base conversion memory 32.
Is supplied to.

The time axis conversion memory 28 is supplied with the read address generated by the read address generation circuit 37 via the buffer 38, so that the color signals R ₁ , G ₁ , B ₁ are read out. . The time axis conversion memory 30 is supplied with the read address generated by the read address generation circuit 39 through the buffer 40, and the color signals R ₂ , G ₂ , and B ₂ are read. Furthermore, the time axis conversion memory 32 is supplied with the read address generated by the read address generation circuit 41 via the buffer 42, so that the color signals R ₃ , G ₃ , and B ₃ are read. Buffer 3
4, 38, 35, 40, 36 and 42 are controlled by read address generating circuits 37, 39 and 41, respectively.

Here, the read address generation circuit 37,
The read addresses are generated by 39 and 41 by the clock CK, the horizontal synchronizing signal H, the vertical synchronizing signal V generated by the master synchronizing generating circuit 43, and the area designating signals E ₁ and E output from the I / O control circuit 44. ₂ and E ₃ . The area designating signals E ₁ , E ₂ , E ₃ are color signals R read from the time axis conversion memories 28, 30, 32.
₁ , G ₁ , B ₁ , R _{2, G 2} , B ₂ and R ₃ , G ₃ , B ₃
Is specified in which storage area of the display memory 45 to be described later, and is output from the CPU 15 and set in the I / O control circuit 44 via the data bus 16. Further, the master sync generation circuit 43 generates a sync signal SYNC for driving a display (not shown), and supplies the sync signal SYNC to the display via the output terminal 46.

In this way, the time base conversion memory 28,
Each color signal R ₁ , G ₁ , read from 30, 32,
_{B 1, R 2, G 2} , B 2 and R _3, G _3, B ₃ is supplied to the thinning interpolation circuit 47, 48 and 49. These thinned-out interpolation circuits 47, 48, 49 are output from the CPU 15 and output via the data bus 16 to the I / O control circuit 50.
Thinning rate or interpolation rate data A ₁ , set to
Based on A ₂ and A ₃ , the input color signals R ₁ , G ₁ and
A thinning process (reduction process) or an interpolation process (enlargement process) is performed on B ₁ , R ₂ , G ₂ , B ₂ and R ₃ , G ₃ , B ₃ , respectively.

The thinning interpolation circuits 47, 48, 49
Each color signal R ₁ , which has been thinned out or interpolated by
G ₁ , B ₁ , R ₂ , G ₂ , B ₂ and R ₃ , G ₃ , B
₃ is supplied to the switch circuit 51 and selectively led to the display memory 45. The selection operation of the switch circuit 51 is performed by the clock CK, the horizontal synchronization signal H, the vertical synchronization signal V generated by the master synchronization generation circuit 43, and the area designation signals E ₁ , E ₂ output from the I / O control circuit 44. ，
It is controlled by the switching control circuit 52 to which E ₃ and E ₃ are supplied.

Further, the display memory 45 is switched based on the address output from the drive address generation circuit 53 to which the clock CK generated by the master synchronization generation circuit 43, the horizontal synchronization signal H, and the vertical synchronization signal V are supplied. Color signals R ₁ , G ₁ , B ₁ , R ₂ , G derived from the circuit 51
After writing ₂ , B ₂ or R ₃ , G ₃ , B ₃ , it is output to the display through the read output terminal 54.

In the system controller 14, a program ROM (read only memory) 55 in which a program to be given to the CPU 15 is stored, and the CPU 1
5, a calculation RAM (random access memory) 56 used in the calculation, a ROM 57 in which area information, thinning information, interpolation information and the like are stored, and operation data from a remote control operation unit 58 operated by a user. CP
An I / O control circuit 59 for taking in U15 is provided.

Here, FIGS. 2A, 2B and 2C are
An example in which multi-screen display is performed on a display having an aspect ratio of 8: 3 is shown. First, as shown in FIG.
FIG. 2B shows the case where the 8-channel NTSC signals NT _{1 to} NT ₈ and the 1-channel MUSE signal MU ₁ are displayed on the same display in multiple screens. FIG. 2B shows the 12-channel NTSC signals NT _{1 to} NT ₁₂ . 3-channel MU
The SE signal MU ₁ ~MU ₃ shows the case of multi-screen display on the same display, FIG. 2 (c), the 6-channel NTSC signal NT ₁ ~NT ₆ and 9 channels of MUSE
The case where the signals MU _{1 to} MU ₉ are displayed on the same display in multiple screens is shown. 2 (a), (b), (c)
As is clear from the above, the screen size of each channel is switched according to the number of displays, so that the unused portion is reduced as much as possible.

Next, with respect to the multi-screen display example shown in FIG. 2B, how the display is realized will be described. First, the aspect ratio of the display is 8: 3 as described above, and this aspect ratio is 8: 3.
Is a display in which two displays each having an aspect ratio of 4: 3 are arranged side by side as shown in FIG. In addition, in FIG. 3B, an NTSC signal having an aspect ratio of 4: 3 has N sizes which can be displayed on the display shown in FIG.
It is shown that there are four types of _{1 to} N ₄ . In the case of N ₁ size, a maximum of 32 screens can be displayed on this display. FIG. 3C shows that the MUSE signal having an aspect ratio of 16: 9 has _four sizes M _{1 to} M ₄ which can be displayed on the display shown in FIG. 3A. In the case of M ₁ size, a maximum of 24 screens can be displayed on this display.

Data for multi-screen display in the form shown in FIG. 2B is stored in the ROM 57 shown in FIG. In this display example, NTSC has 12 screens, MUSE has 3 screens, and channels are selectable for reception. The data indicating which screen size and which position is displayed is stored in the ROM 57 in the form shown in FIG. Figure 5
Is an address table showing where in ROM 57 the data shown in FIG. 4 is stored. The addresses in FIG. 5 are expressed in binary, a _{0 to} a ₄ indicate the number of NTSC screens (3 in this case), and a _{5 to} a ₉ indicate the number of MUSE screens (12 in this case).

[0024] That is, in the multi-screen display mode shown in FIG. 2 (b), NTSC is 12 screen, since MUSE is 3 screen, addresses a ₉ ~a ₀ is "0001101100"
It expressed and, where the data "0100" (hexadecimal) is the control data d ₇ to d ₀ of turned to multi-screen display with the address of ROM57 shown in Fig. 4 is obtained. This control data d
Of _{7 to} d ₀ , d _{2 to} d ₀ indicate horizontal display positions, and as shown in FIG. 3A, they are divided into 8 blocks in NTSC and 6 blocks in MUSE. Also,
d ₄ and d ₃ indicate the display positions in the vertical direction.
As shown in (a), both NTSC and MUSE are divided into 4 blocks. d ₆ and d ₅ indicate the display screen size,
d ₇ indicates the screen of NTSC or the screen of MUSE. Figure 6 shows the relationship between d ₇ to d ₅ and size.

The screen NT ₁ shown in FIG. 2B is NT
It is the N ₂ size of the SC, and is shown as “00100000” in the control data of the ROM 57. Other screens NT ₂ ~
The control data of NT ₁₂ and MU _{1 to} MU ₃ are also stored in the ROM 57 as shown in FIG. 4, and the position and the size of the display on the display are instructed. Based on this size information, the horizontal and vertical thinning rate and interpolation rate data A ₁ , A ₂ , A ₃ for each size are obtained from the conversion table shown in FIG. 7, and the I / O control circuit 50
Are supplied to the thinning-out interpolation circuits 47, 48, and 49, respectively.

Next, FIG. 8 shows the details of the read address generating circuit 37. Since the other read address generation circuits 39 and 41 have the same configuration as the read address generation circuit 37, the description thereof will be omitted. That is, if the data of the screen NT ₁ shown in FIG. 2B is processed by the NTSC decoder 24, the area designation signal E ₁ is input to the conversion ROM 61 in the read address generation circuit 37 via the terminal 60. . This conversion R
From the OM61, based on the size information and the position information,
The start address and end address of the horizontal period of display are output and supplied to the H-work generation circuit 62.

The clock CK supplied to the terminal 63
Is output and the output of the horizontal counter 65, which is reset by the horizontal synchronizing signal H supplied to the terminal 64, is also supplied to the H-work generation circuit 62 as an address. The H-work generation circuit 62 outputs the output of the conversion ROM 61 and the horizontal counter 65.
9A, the signal indicating the display period in the horizontal direction is generated as shown in FIG.

On the other hand, the output of the conversion ROM 61 is also supplied to the V_work generation circuit 66. A vertical counter 68 that counts the horizontal synchronizing signal H supplied to the terminal 64 and is reset by the vertical synchronizing signal V supplied to the terminal 67.
Is also supplied to the V_work generation circuit 66 as an address. The V-wax generating circuit 66 compares the output of the conversion ROM 61 and the output of the vertical counter 68, and then, FIG.
As shown in, a signal indicating a display period in the vertical direction is generated.

The output of the H-work generation circuit 62 and V
The output of the work generation circuit 66 is the display H counter 6 respectively.
9 and the display V counter 70, the address signal is generated only during the H period and V period of the display, and is supplied to the address conversion ROMs 71 and 72. This address conversion RO
M71 and 72 are supplied with horizontal and vertical thinning interpolation control signals H1C and V1C output from the thinning interpolation circuit 47 through terminals 73 and 74, respectively.
The input address signal is converted into an H address and a V address according to the screen size, and is output to the time axis conversion memory 28 via the terminals 75 and 76 as a horizontal read address and a vertical read address.

The output of the H-working generation circuit 62 and the output of the V-working generation circuit 66 are added by an adding circuit 77,
The added output becomes the control signal of the buffer 38 via the terminal 78, and the output obtained by inverting the output of the addition circuit 77 at the knot circuit 79 becomes the control signal of the buffer 34 via the terminal 80.

In this way, the color signals R ₁ , G ₁ , B ₁ read from the time base conversion memory 28 are input to the thinning interpolation circuit 47. In the thinning interpolation circuit 47, as shown in FIG.
The screen size is N for the NTSC signal NT _{1 in} (b).
Since a ₂ performs as thinning interpolation ratio shown in FIG. 7, the thinning process of 0.6 in the horizontal direction, 1.0 in the vertical direction
Execute thinning processing (output as it is). Similarly, in the thinning interpolation circuit 47, the NTSC signal NT of FIG.
_{Since the} screen size is N ₁ for _{2 to} NT ₁₂ , 0.3 decimation processing is performed in the horizontal direction and 0.5 decimation processing is performed in the vertical direction according to the decimation interpolation rate shown in FIG. Run.

Further, in the thinning-out interpolation circuit 49 in which the color signals R ₃ , G ₃ and B ₃ output from the MUSE decoder 26 are input via the time base conversion memory 32, FIG.
Since For the MUSE signal MU ₁ ~MU ₃ screen size is M _2, as thinning interpolation ratio shown in FIG. 7, performs the thinning processing in the horizontal direction to 0.5, in the vertical direction 0.
5 thinning processing is executed.

Next, FIG. 10 shows the details of the thinning-out interpolation circuit 47. The other thinning-out interpolation circuits 48, 49
Since it has the same configuration as that of the thinning-out interpolation circuit 47, its description is omitted. That is, the color signals R ₁ , which are output from the NTSC decoder 24 and written to and read from the time axis conversion memory 28 via the terminal 81.
G ₁ and B ₁ are taken into the latch circuits 82, 83, 84 and 85, respectively. These latch circuits 82, 83, 8
4, 85 are synchronized with the latch pulses LP ₁ , LP ₂ , LP ₃ , LP ₄ output from the control signal generation circuit 86,
Each performs a latch operation.

The control signal generating circuit 86 is based on the clock CK, the horizontal synchronizing signal H and the vertical synchronizing signal V supplied through the terminal 87 and the thinning interpolation control signals H1C and V1C output from the conversion ROM 88. , Latch pulses LP ₁ , LP ₂ , LP ₃ , LP ₄ are generated,
The control data S to be supplied to the coefficient memory 89 is generated. Then, the conversion ROM 88 generates thinning-out interpolation control signals H1C and V1C based on the thinning-out rate or the interpolation rate data A ₁ supplied through the terminal 90.

Here, the thinned-out interpolation control signals H1C and V1C output from the conversion ROM 88 are the terminals 91 and 9.
It is supplied to the read address generating circuit 37 via 2 and is also supplied to the coefficient memory 89. The coefficient memory 89 outputs predetermined coefficient data in pixel units based on the control data S and the thinning-out interpolation control signals H1C and V1C. The coefficient data output from the coefficient memory 89 and the latch circuits 82, 83, 8
And the outputs of 4, 85 are the multiplication circuits 93, 94, 9 respectively.
5, 96 are multiplied, and the respective multiplication results are added by the addition circuit 97 and output to the switch circuit 51 via the terminal 98.

[0036] FIG. 11 (a) shows the state of a thinning process carried out in the horizontal direction of the screen size N _1, FIG. (B) shows the state of a thinning process carried out in the vertical direction of the screen size N _1. Further, FIG. 11C shows a state of horizontal thinning-out processing for the screen size N ₂ . The vertical direction of the screen size N ₂ is not shown because the thinning process and the interpolation process are not performed. Further, with respect to the screen size M ₂ , the thinning rate is 0.5 in both the horizontal and vertical directions.
It can be easily known from (b).

FIGS. 12 (a), 12 (b) and 12 (c) are shown in FIG.
The sequence of the decoding process executed by each of the NTSC decoders 24 and 25 and the MUSE decoder 26 when the other screen display shown in (b) is performed is shown. That is, N
The TSC decoder 24 uses the NTSC signals NT ₁ , NT ₂ ,
The programs of NT ₃ , NT ₄ , NT ₅ , and NT ₆ are decoded in order, and each screen can be viewed with a frame drop. Also, the NTSC decoder 25 uses the NTSC signal N
The programs of T ₇ , NT ₈ , NT ₉ , NT ₁₀ , NT ₁₁ , and NT ₁₂ are sequentially decoded, and the MUSE decoder 26 is
The programs of the USE signals MU ₁ , MU ₂ , and MU ₃ are sequentially decoded.

Next, FIG. 13 shows the decoding processing timing when the screen size is N ₂ . Data for four pixels is read from the time axis conversion memory 28 during one pixel period of display. _{N 2 m 1, N 2 m} 3, N 2 m 4 is output from the latch circuit 82 based on a latch pulse LP _1, the latch circuit 83 based on a latch pulse LP ₂
Outputs N ₂ m ₂ , N ₂ m ₄ , and N ₂ m ₅ . The outputs of the latch circuits 82 and 83 are supplied to the multiplying circuits 93 and 94, respectively, and the coefficient data output from the coefficient memory 89 is subjected to the following arithmetic operation, and the addition circuit 97 performs thinning processing on N ₂ m ₁ ′. , N ₂ m ₂ ′ and N ₂ m ₃ ′ are output.

N ₂ m ₁ ′ = (N ₂ m ₁ × 0.5) + (N ₂ m ₂ × 0.5) N ₂ m ₂ ′ = (N ₂ m ₃ × 0.7) + (N ₂ m ₄ × 0.3) N ₂ m ₃ ′ = (N ₂ m ₄ × 0.3) + (N ₂ m ₅ × 0.7) N ₂ m ₄ ′ = (N ₂ m ₆ × 0.5) _{+ (N 2 m 7 × 0.5} )::::

FIG. 14 shows the decoding processing timing when the screen size is N ₁ . Basically, the processing is performed in the same way as the case of the screen size N ₂ , except that the thinning processing is performed in both the horizontal and vertical directions. The operation of the outputs of the latch circuits 82, 83, 84, 85 and the coefficient data output from the coefficient memory 89 is as follows.

N ₁ l ₁ ′ N ₁ m ₁ ′ = (N ₁ l ₁ N ₁ m ₁ × 0.25) + (N ₁ l ₁ N ₁ m ₂ × 0.25) + (N ₁ l ₂ N _{1 m 1 × 0.25) + (} N 1 l 2 N 1 m 2 × 0.25) N 1 l 1'N 1 m 2 '= (N 1 l 1 N 1 m 4 × 0.42) + ( N ₁ l ₁ N ₁ m ₅ × 0.08) + (N ₁ l ₂ N ₁ m ₄ × 0.42) + (N ₁ l ₂ N ₁ m ₅ × 0.08) N ₁ l _{1 ′} N _{1 m 3 '= (N 1 l} 1 N 1 m 8 × 0.08) + (N 1 l 1 N 1 m 9 × 0.42) + (N 1 l 2 N 1 m 8 × 0.08) + ( N ₁ l ₂ N ₁ m ₉ × 0.42) ::

The series of operations described above are all performed in the above C.
It is performed under the control of the PU 15. FIG. 15 collectively shows the operation of such a CPU 15. First, in step S1, the CPU 15 causes each tuner 12,
13, 19 are operated in a time-division manner (search), the system discrimination circuit 21 is made to discriminate the broadcasting system for each selected channel, and the discrimination result is stored in the system memory 23 via the I / O control circuit 22. Let Then, in step S2, the CPU 15 determines the number of NTSC programs to be displayed on the multi-screen and the MU.
Based on the number of SE programs and the address a ₉ shown in FIG.
˜a ₀ , the address of the ROM 57 storing the display format data d _{7 to} d ₀ shown in FIG. 4 is detected, and step S3
In the display after reading the format data d ₇ to d ₀ from the screen size information and the display position information, in step S4, the thinning rate of the read horizontal from the list shown in FIG. 7 than the screen size information and the vertical direction or the interpolation rate Read the data.

Next, the CPU 15 at step S5, the NTSC decoder 2 which selectively corresponds to the baseband signals of the channels selected by the tuners 12, 13, and 19.
4 and 25 and the distribution process given to the MUSE decoder 26 is performed. First, the CPU 15 at step S6,
Switching channel selection for NTSC decoder 24,
In step S7, the thinning rate or interpolation rate data A ₁ output from the I / O control circuit 50 is transferred to the thinning interpolation circuit 47, and then in step S8, the area designation signal output from the I / O control circuit 44. E ₁ is transferred to the read address generation circuit 37, and the process returns to step S5.

Thereafter, the CPU 15 returns to N in step S9.
The channel selected for the TSC decoder 25 is switched, and the thinning rate or the interpolation rate data A ₂ output from the I / O control circuit 50 is transferred to the thinning interpolation circuit 48 in step S10, and then in step S11, I / O O control circuit 44
The area designating signal E ₂ output from is transferred to the read address generating circuit 39, and the process returns to step S5. After that, the CPU 15 proceeds to step S12, where the MUS
The channel selected for the E decoder 26 is switched, and the thinning rate or interpolation rate data A ₃ output from the I / O control circuit 50 is transferred to the thinning interpolation circuit 49 in step S13. The area designation signal E ₃ output from the O control circuit 44 is transferred to the read address generation circuit 41, and the process returns to step S5.

Therefore, according to the configuration of the above embodiment, the size and display position of each screen are defined according to the number of screens to be displayed, the aspect ratio of the screens, etc. Since the screen size is reduced or expanded by thinning or interpolating the baseband signal, it is possible to perform efficient and highly flexible multi-screen display according to the number of screens to be displayed and the aspect ratio of the screen. it can. The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention.

[0046]

As described above in detail, according to the present invention,
It is possible to provide an extremely good display device capable of performing efficient and highly flexible multi-screen display according to the number of screens to be displayed, the aspect ratio of the screen, and the like.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing an embodiment of a display device according to the present invention.

FIG. 2 is a diagram showing an example of multi-screen display in the embodiment.

FIG. 3 is a diagram for explaining each screen size in the embodiment.

FIG. 4 is a diagram showing a storage state of display format data in the embodiment.

FIG. 5 is a diagram showing an address table for searching the same display format data.

FIG. 6 is a diagram showing a relationship between the same display format data and a screen size.

FIG. 7 is a diagram showing a relationship between the screen size, a thinning rate, and an interpolation rate.

FIG. 8 is a block configuration diagram showing details of a read address generation circuit of the same embodiment.

FIG. 9 is a timing chart for explaining the operation of the read address generation circuit.

FIG. 10 is a block configuration diagram showing details of a thinning-out interpolation circuit of the embodiment.

FIG. 11 is a diagram for explaining a thinning-out process in the embodiment.

FIG. 12 is a view for explaining the order of decoding processing in the embodiment.

FIG. 13 is a timing chart for explaining a thinning-out processing operation in the embodiment.

FIG. 14 is a timing chart for explaining another thinning-out processing operation in the embodiment.

FIG. 15 is a flowchart collectively showing the overall operation in the embodiment.

FIG. 16 is a diagram for explaining conventional multi-screen display.

[Explanation of symbols]

11 ... Antenna, 12, 13 ... Tuner, 14 ... System controller, 15 ... CPU, 16 ... Data bus, 1
7 ... I / O control circuit, 18 ... Antenna, 19 ... Tuner, 20 ... Switch circuit, 21 ... System discriminating circuit, 22 ...
I / O control circuit, 23 ... System memory, 24, 25 ... NT
SC decoder, 26 ... MUSE decoder, 27 ... I / O
Control circuit, 28 ... Time axis conversion memory, 29 ... Write address generation circuit, 30 ... Time axis conversion memory, 31 ... Write address generation circuit, 32 ... Time axis conversion memory, 33
... write address generation circuit, 34 to 36 ... buffer,
37 ... Read address generating circuit, 38 ... Buffer, 3
9 ... Read address generating circuit, 40 ... Buffer, 41
... Read address generation circuit, 42 ... Buffer, 43 ...
Master synchronization generation circuit, 44 ... I / O control circuit, 45 ...
Display memory, 46 ... Output terminal, 47-49 ... Thinning interpolation circuit, 50 ... I / O control circuit, 51 ... Switch circuit, 5
2 ... Switching control circuit, 53 ... Drive address generation circuit, 54
... Output terminal, 55 ... Program ROM, 56 ... Calculation RA
M, 57 ... ROM, 58 ... Remote control operation section, 59 ... I / O control circuit, 60 ... Terminal, 61 ... Conversion R
OM, 62 ... H generation circuit, 63, 64 ... Terminal, 65
... horizontal counter, 66 ... V-working generation circuit, 67 ... terminal,
68 ... Vertical counter, 69 ... Display H counter, 70 ... Display V counter, 71, 72 ... Address conversion ROM, 73
-76 ... Terminal, 77 ... Addition circuit, 78 ... Terminal, 79 ... Knot circuit, 80, 81 ... Terminal, 82-85 ... Latch circuit, 86 ... Control signal generating circuit, 87 ... Terminal, 88 ... Conversion ROM, 89 ... Coefficient memory, 90 to 92 ... Terminal, 93 to
96 ... Multiplier circuit, 97 ... Adder circuit, 98 ... Terminal.

Claims (1)

[Claims] 1. A display device for displaying a plurality of television signals on a single display in a multi-screen manner, the screen size and the display position of each television signal on the display according to the number and system of the plurality of television signals. The adjusting means for adjusting the screen size by selectively thinning or interpolating each television signal according to the screen size specified by the specifying means, and the screen size by the adjusting means. And a disposing unit that disposes each adjusted television signal at the display position defined by the defining unit.