JPH0365903B2 - - Google Patents
Info
- Publication number
- JPH0365903B2 JPH0365903B2 JP22741884A JP22741884A JPH0365903B2 JP H0365903 B2 JPH0365903 B2 JP H0365903B2 JP 22741884 A JP22741884 A JP 22741884A JP 22741884 A JP22741884 A JP 22741884A JP H0365903 B2 JPH0365903 B2 JP H0365903B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- semiconductor
- conduction
- conductivity type
- programmable element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 84
- 239000012535 impurity Substances 0.000 claims description 15
- 238000010438 heat treatment Methods 0.000 claims description 12
- 238000010894 electron beam technology Methods 0.000 claims description 3
- 238000010884 ion-beam technique Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 238000005265 energy consumption Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000004093 laser heating Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000003685 thermal hair damage Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は例えば半導体PROM（プログラマブ
ル・リード・オンリ・メモリ）装置あるいはリダ
ンダンシイ回路等に使用されるプログラマブル素
子に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a programmable element used, for example, in a semiconductor PROM (programmable read-only memory) device or a redundancy circuit.
近年、プログラマブル素子、いわゆるPROM
素子を含む半導体LSI（大規模集積回路）の需要
が増大している。上記PROM素子はPROM・
LSIとしてだけではなく、メモリLSIや論理LSI
のリダンダンシイ回路すなわち不良救済回路の一
部として使用されるに至つている。
In recent years, programmable elements, so-called PROM
Demand for semiconductor LSIs (large-scale integrated circuits) including devices is increasing. The above PROM element is PROM・
Not only LSI, but also memory LSI and logic LSI
It has come to be used as part of redundancy circuits, that is, defect relief circuits.
従来のPROM素子、特に通常導通状態でプロ
グラム後に非導通状態になるようなPROM素子
の代表的なものは、フユーズ溶断方式のものであ
り、その溶断方式としては、例えば電流によるも
のや、レーザによるものが使用されている。 Conventional PROM elements, especially PROM elements that are normally conductive and become non-conductive after programming, are typical of fuse blowout methods, such as electric current or laser blowout. things are used.
フユーズ溶断方式のPROM素子の等価回路を
第５図ａに、構造の例を第５図ｂに示す。上記電
流溶断方式の場合は、端子１，２の間に数十ｍ
Ａ、数ｍsecの電流パルスをフユーズ部３に流す。
この様に大きな電流駆動には大きな面積のトラン
ジスタを要する為、高集積MOS・LSIに適用す
るには困難があつた。一方、レーザ溶断方式の
PROM素子では１プログラム当り0.6μJ程度のエ
ネルギーが必要なことが知られている。 An equivalent circuit of a fuse blowing PROM element is shown in FIG. 5a, and an example of its structure is shown in FIG. 5b. In the case of the above current fusing method, there is a distance of several tens of meters between terminals 1 and 2.
A. A current pulse of several milliseconds is passed through the fuse section 3.
Since driving such a large current requires a transistor with a large area, it has been difficult to apply it to highly integrated MOS/LSI. On the other hand, the laser fusing method
It is known that PROM elements require approximately 0.6 μJ of energy per program.
ところで一般にフユーズ溶断方式のPROM素
子は、単にフユーズを溶融するエネルギー以外
に、フユーズを構成している物質を追い流した
り、吹き飛ばしたり、あるいは蒸発させたりして
切断するためのエネルギーを要する為、プログラ
ム時に大きなエネルギーを消費する。また、フユ
ーズ素子は溶断時、保護膜で被ふくしておけない
こと、フユーズを構成している物質が素子全体に
飛散すること、あるいは多大なエネルギーのため
フユーズ素子周囲に熱ダメージを与え易い等、信
頼性を低下させる様な要因を多く含んでいる。 By the way, in general, fuse-cutting PROM elements require energy not only to simply melt the fuse, but also to blow away, blow away, or evaporate the materials that make up the fuse, so it is difficult to program the fuse. sometimes consumes a large amount of energy. In addition, when the fuse element blows, it cannot be covered with a protective film, the substances that make up the fuse may scatter over the entire element, or the large amount of energy can easily cause thermal damage to the area around the fuse element. It includes many factors that reduce reliability.
その他に、従来のPROM素子は、プログラム
によつて単にon（オン）がoff（オフ）になるか、
あるいはoffがonになるかするもの以外は知られ
ていない。例えばリダンダンシイ回路等で必要な
一方がonからoffになると同時に、他方がoffから
onになるような素子が必要な場合は、２つの異
種の素子を用意しこれらを同時にプログラムする
必要があつた。この方法では２つの素子を用意す
るため、面積的にも不利であり、２ケ所のプログ
ラムを行なうため、エネルギー面、信頼性面でも
不利であり、新しい多機能のプログラマブル素子
が望まれている。 In addition, conventional PROM elements can be simply turned on or off by a program, or
Or nothing is known other than turning off to on. For example, in a redundancy circuit, one side changes from on to off, while the other changes from off to off.
If an element that turned on was required, it was necessary to prepare two different types of elements and program them simultaneously. Since this method requires two elements, it is disadvantageous in terms of area, and since programming is performed in two places, it is disadvantageous in terms of energy and reliability.Therefore, a new multifunctional programmable element is desired.
本発明は上記欠点を解消するためになされたも
ので、その目的は、プログラム時のエネルギー消
費を低減でき、信頼性にすぐれ、設計余裕度が高
く、且つ１ケ所のプログラムで一方の電流経路が
onからoff、他方の電流経路がoffからonへという
ような多機能な切換えが可能なプログラマブル素
子を提供することにある。
The present invention was made in order to eliminate the above-mentioned drawbacks, and its purpose is to reduce energy consumption during programming, have excellent reliability, have a high degree of design margin, and to program one current path at one location.
The object of the present invention is to provide a programmable element capable of multifunctional switching such as switching from on to off and the other current path from off to on.
すなわち、本発明のプログラマブル素子は、第
１導電型の第１半導体層を挾んで互いに離間させ
て、第２導電型で上記第１半導体層より高濃度の
不純物を拡散し第２、第３の半導体層を設け、こ
れら第２、第３半導体層に熱処理を加えることに
より、第２、第３半導体層からこれら半導体層間
の第１半導体層へ不純物をしみ出させて第２、第
３半導体層の導電性を増加させるとともに、上記
第２、第３半導体層を結ぶ線に対して交差する方
向の第１半導体層の導電性を減少させるようにし
ており、上記熱処理を加えるか否かに応じてプロ
グラムを行なうようにしている。また、第１導電
型の第１半導体層の長手方向に対して交差する方
向に一端が接するように、第２導電型で上記第１
半導体層より高濃度の不純物が拡散された第２の
半導体層を設けるとともに、上記第１半導体層と
第２半導体層との接合部近傍における第１半導体
層の一端側に第１導電型の高濃度不純物領域を設
け、上記第１、第２半導体層の接合部近傍に熱処
理を加えることにより、上記第２半導体層から第
１半導体層へ不純物をしみ出させ、上記高濃度不
純物領域から上記第１、第２半導体層の接合部へ
不純物をしみ出させてPN接合を形成することに
より、第１半導体層の一端と他端間を非導通と
し、上記第１半導体層の一端と第２半導体層間を
導通させるようにしており、上記熱処理を加える
か否かに応じてプログラムを行なうようにしてい
る。これらの構造では、プログラムする際、不純
物が拡散する程度のエネルギーを加えれば良く、
従来と異なつて物質を切断する必要はない。従つ
て、低消費エネルギーでプログラム出来、プログ
ラマブル素子を保護膜でおおつた状態でもプログ
ラムが可能であるため、高信頼性を有する回路が
実現できる。また、一方向の電流経路がoffから
onへ、他方向の電流経路はonからoffへ一度にプ
ログラムが可能である。
That is, in the programmable element of the present invention, the first semiconductor layer of the first conductivity type is sandwiched and separated from each other, and the impurity of the second conductivity type and the second semiconductor layer is diffused at a higher concentration than the first semiconductor layer. By providing a semiconductor layer and applying heat treatment to these second and third semiconductor layers, impurities are exuded from the second and third semiconductor layers to the first semiconductor layer between these semiconductor layers, and the second and third semiconductor layers are formed. At the same time as increasing the conductivity of the first semiconductor layer, the conductivity of the first semiconductor layer in the direction crossing the line connecting the second and third semiconductor layers is decreased, depending on whether or not the heat treatment is applied. I try to run the program using Further, the first semiconductor layer of the second conductivity type is arranged such that one end of the first semiconductor layer of the first conductivity type is in contact with a direction crossing the longitudinal direction of the first semiconductor layer.
A second semiconductor layer in which impurities are diffused at a higher concentration than the semiconductor layer is provided, and a first conductivity type high-conductivity layer is provided on one end side of the first semiconductor layer in the vicinity of the junction between the first semiconductor layer and the second semiconductor layer. By providing a high concentration impurity region and applying heat treatment near the junction between the first and second semiconductor layers, impurities seep out from the second semiconductor layer to the first semiconductor layer, and from the high concentration impurity region to the first semiconductor layer. 1. By exuding impurities into the junction of the second semiconductor layer to form a PN junction, one end of the first semiconductor layer and the other end are made non-conductive, and one end of the first semiconductor layer and the second semiconductor layer are made non-conductive. Conductivity is established between the layers, and programming is performed depending on whether or not the above-mentioned heat treatment is applied. When programming these structures, it is sufficient to apply enough energy to diffuse the impurities.
Unlike conventional methods, there is no need to cut the material. Therefore, programming can be performed with low energy consumption, and programming is possible even when the programmable element is covered with a protective film, so that a highly reliable circuit can be realized. Also, the one-way current path changes from off to
on, and the current path in the other direction can be programmed from on to off at once.
以下、本発明の一実施例について図面を参照し
て説明する。第１図ａはプログラム前の状態、第
１図ｂはプログラム後の状態をそれぞれ示してい
る。ここでは前記第１導電型としてＰ型、第２導
電型としてＮ型の例を示すが、反対の構成も可能
である。ａ図におけるＰ型の半導体層６１には、
この半導体層６１と交差する方向に、半導体層６
１を挟むようにしてN+型の第２、第３半導体層
６２1，６２2が形成される。ここで、上記半導体
層６２1，６２2の不純物濃度は、半導体層６１の
不純物濃度よりも高く設定される。上記各半導体
層６１，６２1および６２2としては、技術的には
単結晶シリコン、多結晶シリコン、非晶質シリコ
ン等で形成することが容易と思われるが、他の半
導体でも良い。また、寄生的な電流路をなくすた
め、上記各半導体層６１，６２1および６２2は絶
縁膜上に形成する事が望ましい。
An embodiment of the present invention will be described below with reference to the drawings. FIG. 1a shows the state before programming, and FIG. 1b shows the state after programming. Here, an example is shown in which the first conductivity type is P type and the second conductivity type is N type, but the opposite configuration is also possible. In the P-type semiconductor layer 61 in figure a,
The semiconductor layer 6
N + type second and third semiconductor layers 62 1 and 62 2 are formed so as to sandwich the semiconductor layer 1 . Here, the impurity concentration of the semiconductor layers 62 1 and 62 2 is set higher than that of the semiconductor layer 61. Although it seems technically easy to form each of the semiconductor layers 61, 62 1 and 62 2 using single crystal silicon, polycrystalline silicon, amorphous silicon, etc., other semiconductors may also be used. Further, in order to eliminate parasitic current paths, it is desirable that each of the semiconductor layers 61, 62 1 and 62 2 be formed on an insulating film.
次に、プログラム時に上記半導体層６１と半導
体層６２1，６２2との交差位置付近に、レーザ又
は電子線又はイオンビーム等を上方から選択的に
照射して熱処理を施すと、半導体層６２1，６２2
からその間の半導体層６１にN+型の不純物がし
み出して半導体層６２1と６２2と結合され、第１
図ｂのような構造体に変化する。さて、プログラ
ム前には、Ｂ−B′間は導電性が高く（導通状
態）、Ｃ−C′間はｎ−ｐ−ｎ接合のため極めて導
電性が低い（非導通状態）のに対し、プログラム
後は、Ｂ−B′間がｐ−ｎ−ｐ接合のため極めて
導電性が低くなり、Ｃ−C′間は導電性が高くな
る。従つて、一方の電流経路がonからoffへ、他
方の電流経路はoffからonへ一度にプログラムで
きたことになる。 Next, during programming, heat treatment is performed by selectively irradiating a laser, an electron beam, an ion beam, etc. from above to the vicinity of the intersection between the semiconductor layer 61 and the semiconductor layers 62 1 and 62 2 . ,62 2
The N + type impurity seeps into the semiconductor layer 61 between them and is combined with the semiconductor layers 62 1 and 62 2 to form the first
The structure changes to the one shown in Figure b. Now, before programming, the conductivity between B and B' is high (conducting state), and the conductivity between C and C' is extremely low (non-conducting state) because it is an n-p-n junction. After programming, the conductivity between B and B' becomes extremely low due to the pnp junction, and the conductivity between C and C' becomes high. Therefore, one current path can be programmed from on to off, and the other current path can be programmed from off to on at once.
第２図には、上記第１図に示した本発明による
複合機能を有するプログラマブル素子を最適に応
用し得るリダンダンシイ回路例を示している。リ
ダンダンシイ回路８０の電源線８１は、通常は接
地電位に接続され、リダンダンシイ回路８０を動
作させる時には高電圧（VDD）に接続されるよう
なスイツチＳに接続されている。このスイツチＳ
に対して、本発明のプログラマブル素子を応用す
るパターンレイアウト例を第３図および第４図に
示す。第３図において、N+型半導体層の１部９
３とＰ型半導体層の１部９４は金属線９０によつ
て電気的に短絡されている。この構成は、Ｐ、Ｎ
両層の交差部の加熱により、前記第２図のスイツ
チＳが切り換わるようになつている。 FIG. 2 shows an example of a redundancy circuit in which the programmable element having multiple functions according to the present invention shown in FIG. 1 can be optimally applied. A power supply line 81 of the redundancy circuit 80 is normally connected to a ground potential, and is connected to a switch S that is connected to a high voltage (V DD ) when the redundancy circuit 80 is operated. This switch S
3 and 4 show examples of pattern layouts to which the programmable element of the present invention is applied. In FIG. 3, a part 9 of the N + type semiconductor layer
3 and a portion 94 of the P-type semiconductor layer are electrically short-circuited by a metal wire 90. This configuration is P,N
The switch S shown in FIG. 2 is switched by heating the intersection of both layers.
第４図ａでは、プログラム前Ｐ型半導体層１０
２を介してP+型層１００はN+型層１０１と離れ
ているが、プログラム時、N+半導体領域１０１
からしみ出したN+型不純物により、この領域１
０１が拡大し、第４図ｂの如くP+N+接合１０３
を形成するに至る。このP+N+接合１０３は逆接
合耐圧が小さいため、端子１０４は電源VDDと電
気的に接続される。 In FIG. 4a, the P-type semiconductor layer 10 before programming
Although the P + type layer 100 is separated from the N + type layer 101 through the
Due to the N + type impurity seeping out from the
01 is enlarged and P + N + junction 103 as shown in Figure 4b
leading to the formation of Since this P + N + junction 103 has a low reverse junction breakdown voltage, the terminal 104 is electrically connected to the power supply V DD .
以上説明したように、本発明に係るプログラマ
ブル素子は、電流自己加熱型、レーザ加熱型のど
ちらでも従来の数分の１以下のエネルギーでプロ
グラムが出来る。また従来、フユーズを構成する
物質が変形もしくは消滅するため、保護膜でその
上をおおつておけなかつたが本発明に係るプログ
ラマブル素子では、プログラムに大量の物質の移
動を伴なわないため、保護膜を破壊せずにプログ
ラム出来、信頼性の高い素子の実現が可能であ
る。また本発明では現在知られていない複合機能
を持つた素子を構成でき、リダンダンシイ回路に
適用した際、少ない手数で誤まりの少ないプログ
ラムが可能となる。
As explained above, the programmable element according to the present invention can be programmed with less than a fraction of the energy of conventional devices, whether of the current self-heating type or the laser heating type. Furthermore, in the past, the material constituting the fuse could not be covered with a protective film because it deformed or disappeared, but in the programmable element according to the present invention, since programming does not involve the movement of a large amount of material, the protective film It is possible to program the device without destroying it, making it possible to realize a highly reliable device. Furthermore, the present invention allows an element to be constructed with a complex function that is currently unknown, and when applied to a redundancy circuit, it becomes possible to program with fewer steps and fewer errors.
第１図は本発明の一実施例に係わるプログラマ
ブル素子を説明するための構成図、第２図は上記
第１図のプログラマブル素子を応用し得るリダン
ダンシイ回路例を示す図、第３図および第４図は
それぞれ上記第２図の回路におけるスイツチのパ
ターンレイアウト例を示す図、第５図は従来のプ
ログラマブル素子を説明するための図である。
６１……第１の半導体層、６２1，６２2……第
２、第３の半導体層。
FIG. 1 is a block diagram for explaining a programmable element according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of a redundancy circuit to which the programmable element shown in FIG. 1 can be applied, and FIGS. 4 is a diagram showing an example of the pattern layout of the switch in the circuit of FIG. 2, and FIG. 5 is a diagram for explaining a conventional programmable element. 61...First semiconductor layer, 62 1 , 62 2 ... Second and third semiconductor layers.
Claims (1)
を挾んで互いに離間して形成される第２導電型で
上記半導体層より高濃度の不純物が拡散された第
２、第３の半導体層とを具備し、上記第２、第３
半導体層に熱処理を加えることによりこれら第
２、第３半導体層間の導電性を増加させ、上記第
２、第３半導体層を結ぶ線に対して交差する方向
の上記第１半導体層の導電性を減少させるように
して成り、上記熱処理を加えるか否かに応じて上
記第１半導体層の非導通あるいは導通、および上
記第２、第３半導体層間の導通あるいは非導通を
同時にプログラムする如く構成したことを特徴と
するプログラマブル素子。 ２ 前記各半導体層を、絶縁膜上の多結晶半導体
もしくは非晶質半導体で形成することを特徴とす
る特許請求の範囲第１項記載のプログラマブル素
子。 ３ 前記熱処理を、レーザもしくは電子線もしく
はイオンビームで行なうことを特徴とする特許請
求の範囲第１項記載のプログラマブル素子。 ４ 第１導電型の第１半導体層と、この第１半導
体層の長手方向に対して交差する方向に一端が接
するように設けられ、第２導電型で上記第１半導
体層より高濃度の不純物が拡散された第２の半導
体層と、上記第１半導体層と上記第２半導体層と
の接合部近傍における第１半導体層の一端側に設
けられる第１導電型の高濃度不純物領域とを具備
し、上記第１、第２半導体層の接合部近傍に熱処
理を加えて上記高濃度不純物領域と上記第２半導
体層における第１導電型と第２導電型の各接合面
を移動させることにより、上記第１半導体層の一
端と他端間を非導通とし、上記第１半導体層の一
端と上記第２半導体層間を導通させるようにして
成り、上記熱処理を加えるか否かに応じて上記第
１半導体層の一端と他端間の導通あるいは非導
通、および上記第１半導体層の一端と上記第２半
導体層間との非導通あるいは導通を同時にプログ
ラムする如く構成したことを特徴とするプログラ
マブル素子。 ５ 前記各半導体層を、絶縁膜上の多結晶半導体
もしくは非晶質半導体で形成することを特徴とす
る特許請求の範囲第４項記載のプログラマブル素
子。 ６ 前記熱処理を、レーザもしくは電子線もしく
はイオンビームで行なうことを特徴とする特許請
求の範囲第４項記載のプログラマブル素子。[Scope of Claims] 1. A first semiconductor layer of a first conductivity type, and a second semiconductor layer of a second conductivity type formed spaced apart from each other with this semiconductor layer sandwiched therebetween, and a second semiconductor layer having a higher concentration of impurity diffused than the semiconductor layer. , a third semiconductor layer, and the second and third semiconductor layers.
By applying heat treatment to the semiconductor layer, the conductivity between the second and third semiconductor layers is increased, and the conductivity of the first semiconductor layer in the direction crossing the line connecting the second and third semiconductor layers is increased. and is configured to simultaneously program non-conduction or conduction of the first semiconductor layer and conduction or non-conduction between the second and third semiconductor layers depending on whether or not the heat treatment is applied. A programmable element featuring: 2. The programmable element according to claim 1, wherein each of the semiconductor layers is formed of a polycrystalline semiconductor or an amorphous semiconductor on an insulating film. 3. The programmable element according to claim 1, wherein the heat treatment is performed using a laser, an electron beam, or an ion beam. 4 A first semiconductor layer of a first conductivity type, and an impurity of a second conductivity type with a higher concentration than the first semiconductor layer, which is provided so that one end is in contact with the first semiconductor layer in a direction crossing the longitudinal direction of the first semiconductor layer. a second semiconductor layer in which is diffused, and a first conductivity type high concentration impurity region provided on one end side of the first semiconductor layer in the vicinity of a junction between the first semiconductor layer and the second semiconductor layer. and by applying heat treatment to the vicinity of the junction of the first and second semiconductor layers to move the junction surfaces of the first conductivity type and the second conductivity type in the high concentration impurity region and the second semiconductor layer, The one end of the first semiconductor layer and the other end of the first semiconductor layer are made non-conductive, and the one end of the first semiconductor layer and the second semiconductor layer are made electrically conductive. A programmable element characterized in that it is configured to simultaneously program conduction or non-conduction between one end of the semiconductor layer and the other end, and non-conduction or conduction between the one end of the first semiconductor layer and the second semiconductor layer. 5. The programmable element according to claim 4, wherein each of the semiconductor layers is formed of a polycrystalline semiconductor or an amorphous semiconductor on an insulating film. 6. The programmable element according to claim 4, wherein the heat treatment is performed using a laser, an electron beam, or an ion beam.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59227418A JPS60121762A (en) | 1984-10-29 | 1984-10-29 | Programmable element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59227418A JPS60121762A (en) | 1984-10-29 | 1984-10-29 | Programmable element |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56186408A Division JPS5887860A (en) | 1981-11-20 | 1981-11-20 | Semiconductor prom device and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60121762A JPS60121762A (en) | 1985-06-29 |
| JPH0365903B2 true JPH0365903B2 (en) | 1991-10-15 |
Family
ID=16860528
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59227418A Granted JPS60121762A (en) | 1984-10-29 | 1984-10-29 | Programmable element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60121762A (en) |
-
1984
- 1984-10-29 JP JP59227418A patent/JPS60121762A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60121762A (en) | 1985-06-29 |
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