JPS5877098A - Programmable read-only memory element - Google Patents

Programmable read-only memory element

Info

Publication number
JPS5877098A
JPS5877098A JP56172541A JP17254181A JPS5877098A JP S5877098 A JPS5877098 A JP S5877098A JP 56172541 A JP56172541 A JP 56172541A JP 17254181 A JP17254181 A JP 17254181A JP S5877098 A JPS5877098 A JP S5877098A
Authority
JP
Japan
Prior art keywords
wiring layer
layer
substance
wiring
melting point
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56172541A
Other languages
Japanese (ja)
Inventor
Yukimasa Uchida
内田 幸正
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56172541A priority Critical patent/JPS5877098A/en
Priority to US06/428,614 priority patent/US4814853A/en
Priority to DE8282305624T priority patent/DE3278653D1/en
Priority to EP82305624A priority patent/EP0078165B1/en
Publication of JPS5877098A publication Critical patent/JPS5877098A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01HELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H85/00Protective devices in which the current flows through a part of fusible material and this current is interrupted by displacement of the fusible material when this current becomes excessive
    • H01H85/02Details
    • H01H85/04Fuses, i.e. expendable parts of the protective device, e.g. cartridges
    • H01H85/041Fuses, i.e. expendable parts of the protective device, e.g. cartridges characterised by the type
    • H01H85/046Fuses formed as printed circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Read Only Memory (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To realize a fine and high-density PROM with improved designing tolerance, by providing a wiring layer of the 1st material which generates heat with electric conduction and the 2nd and 3rd wiring layers which are set opposite to the 1st wiring layer via an insulated film and made eutectic with the heat generated from the 1st wiring layer. CONSTITUTION:The 1st wiring layer 30 having conductivity is formed on an insulated film 20 on a semiconductor substrate 10. The 2nd wiring layer 50 of Al is provided on the layer 30 via an insulated layer 40, and a disconnecting part 70 which disconnects the layer 50 on a counter part 60 with a prescribed space. Then the 3rd wiring layer 80 of amorphous silicon is formed across the part 70 of the layer 50. When a program current is supplied to the layer 30 in a program function mode, the layer 30 functions as a heating element. Thus the layers 50 and 80 are made eutectic at the part 60 to form an eutectic region 100 with an extremely low level of resistance value. As a result, a fine and high- density PROM element is obtained.

Description

【発明の詳細な説明】 く技術分野〉 本発明は、プロゲラ!プル・リード・オンリ・メモリ素
子(以下、FROMg子という、)K係り、!!IIK
シト→方式のFROM素子に関するものである。
[Detailed Description of the Invention] Technical Field> The present invention is directed to Progera! Pull read only memory element (hereinafter referred to as FROMg element) K,! ! IIK
The present invention relates to a FROM element based on the ``Site→'' method.

〈従来技術〉 近年、FROM素子を含む牛導体LSIの進歩とともに
その需要が増大しつつある。FROM素子の場合、単に
:FROM−L8Iとしてだけでなく、メモリLSIや
論理L81のいわゆるリダンダンシイ(R@duuda
na7:冗長度)回路、すナワ1 ち不良救済回路に利用されつつある。
<Prior Art> In recent years, with the progress of conductor LSIs including FROM elements, the demand for them has been increasing. In the case of a FROM element, it is not only used as a FROM-L8I, but also as a so-called redundancy (R@duuda) of a memory LSI or logic L81.
na7: redundancy) circuit, sunawa1 is being used for defect relief circuits.

従来のFROM素子の代表的なものとしては、。Typical conventional FROM elements include:

■ ダイオードのPNfi14rK過大電流を流すこと
KよりPN接合間をシ曹−トさせて書込みを行う接合シ
田−ト方式のもの、 ■ フェーズ素子に電流を流して溶断することKより書
込みを行う電流フェーズ方式のもの、■ 73−−ズ素
子をレーザ光線により切断して書−込みを行うレーダフ
ユーズ方式の4へかある。
■ PNfi14rK of the diode The current that performs writing by passing an excessive current through the PN junction. ■ The current that performs writing by flowing a current through the phase element and blowing it out. There are two types: a phase type, and a radar fuse type in which writing is performed by cutting the 73--Z element with a laser beam.

このうち、■の結合シ冒−ト方式PROM素子お工び2
の電流7ユ一ズ方式FROM素子は、共にプログラムす
るのに非常に大きな電流を必要とする。
Of these, the combination sheet method PROM element fabrication 2 of
The current 7-unit FROM elements require very large currents to program together.

例えば、必要とするプレグツム電流の具体的数値を示す
と、■の接合シト→方式では約100100(、■1醜
フェーズ方式では数10(mA)が必要である。このよ
うな大きな電流を駆動するためには、通常、高増幅度の
バイポーラトランジスタが必要となる。
For example, the specific numerical value of the required pregtum current is approximately 100,100 for the junction site → method (2), and several tens (mA) for the 1-ugly phase method. This typically requires bipolar transistors with high amplification.

また、Mo2・L8 IKかかるPIIOM素子を適用
するには、非常に大きなチャネル幅の電流駆動用M08
トランジスタが必要と表9、したがって大きな面積が占
有されてしまうこととなる口このようなことから、上記
1および20方式のFROM素子では高集積化が困−で
あった。
In addition, in order to apply a PIIOM element that requires Mo2 L8 IK, it is necessary to use M08 for current drive with a very large channel width.
Since a transistor is required and therefore a large area is occupied, it has been difficult to achieve high integration in the FROM elements of the above-mentioned 1 and 20 systems.

一方、3のレーダフユーズ方式のFROMg子の場合、
レーザ光線を用いて所定のプ闘グラム位置を切断すると
とに工りプログラムするわけであるが、レーず光線な轟
てる位置は非常に接近しており、したがって高精度の1
動位置検出装置が必要となるなど高価なプ■グラ電ング
装置が必要となる。
On the other hand, in the case of the radar fuse method FROM g-child of No. 3,
The program is programmed by cutting a predetermined program position using a laser beam.
An expensive programming device such as a dynamic position detection device is required.

かかる状況下にあって、FROM素子としては最も代表
的な2の電流フェーズ方式のFROM素子は、上述の如
き欠点を有するもののプ胃グラム処理は最も簡便であり
、そのメリットはFROM素子活用Vc幽って十分評価
に値する。そこで、電流フェーズ方式につき検討する。
Under such circumstances, the current phase type FROM element (2), which is the most typical FROM element, has the above-mentioned drawbacks, but it is the simplest for program processing, and its merits are that the Vc limit using the FROM element is That's worthy of praise. Therefore, we will consider the current phase method.

第1図は従来″の電流7工−ズ方式の7工−ズ素子部を
示した図であり、(a)はその等価回路、伽)は平面的
に与だ構造図である。(&)の等価回路において、端子
1.2間に電流を流すとフェーズ素子Fが溶断し、この
溶断によってプ田グラ電ングがされたこととなる0(b
)の構造図において、フェーズ素子1は、例えば多結晶
シリコン層で形成される。
FIG. 1 is a diagram showing a 7-phase element part of the conventional 7-phase current system, where (a) is its equivalent circuit, and (a) is a structural diagram given in plan. (& ), when a current is passed between terminals 1 and 2, the phase element F melts, and this melting causes the 0(b
), the phase element 1 is formed of, for example, a polycrystalline silicon layer.

7ユiズ素子rの端部5.6は、アルンエウム(以下、
ムjと略記する。)配線7.8とフンタクトをとるため
忙、フユーズ素子IPK対し相対的に広げて設けられて
いる・端部5,6にはボンタクト大3.4が設けられ、
この穴においてAノ配線7.8と接続されている。
The end portion 5.6 of the 7-is element r has an arunium (hereinafter,
It is abbreviated as muj. ) The wiring 7.8 and the wire 7.8 are connected to each other, and are spread out relative to the fuse element IPK.The ends 5 and 6 are provided with a large bond contact 3.4,
It is connected to the A wiring 7.8 in this hole.

このような従来のFROM素子は上述した欠点(高集積
化り困難性)K加え、さらに詳しくは通電による溶断と
いう点に基づきフユーズ素子rの設計性、加工性、信頼
性にも問題がある0っtす、かかる問題は、第1K7:
L−ズ素子の溶断メカニズムが十分に%消されていない
こと、第2にフユーズ素子をその融点以上に加熱する必
要があることからフェーズ嵩子周l!に熱ダメージを与
えること、などから引起こされるものである。さらに1
7エーズ素子はsm時にパッジベージ冒ン(PaBlv
atlon)膜(保護膜)で覆っておくことができない
た玩、信頼性に乏しく表るという欠点もあるO 〈発明の目的〉 そこで、本発明は、上述した如き欠点を解消するととも
に、高密度性に優れ、プログラムに要する電流を小さく
することができ、信頼性に優れ、かつ、設計余裕度の高
いFROM素子!提供すること!を目的とする0 〈発明の構成の概要〉 上記目的を達成するために、本発明によるFROM素子
は、第1の物質工り愈る導電性の第1の配線層と第2の
物質よりなる纂2の配線層とを絶縁膜を介して対向して
配置(例えば、重ね合わせ)し、その対向部における第
2の配線層に断線部を設け、その断線部の両端部間にま
たがった状態で第2の配線層に接して第3の物質よりな
る第3の配線層な配役してなる0 前記第2の物質と第3の物質は、その共融化温度が第1
の物質の融点より十分低くなるように選び、第1の配線
層に通電することによって第1の配線層を発熱体として
作用せしめ、その発熱に工り、前記対向部分において第
2の物質と纂3のm−質問の共融に工9共晶化を進め、
もってw&3配騨層の断線部両端間の電気抵抗を低下さ
せることに。
In addition to the above-mentioned drawback (difficulty in achieving high integration), such conventional FROM elements also have problems in the design, workability, and reliability of the fuse element r due to the fact that it is blown out by current flow. This problem is the first K7:
The fusing mechanism of the fuse element has not been sufficiently eliminated, and secondly, the fuse element must be heated above its melting point, so the phase height of the fuse element is low! It is caused by heat damage to the 1 more
The 7Aze element is used to attack Pudgebage (PaBlv) at the time of sm.
Therefore, the present invention solves the above-mentioned drawbacks, and also has the disadvantage that it is not reliable because it cannot be covered with an atlon film (protective film). A FROM element that has excellent performance, can reduce the current required for programming, has excellent reliability, and has a high design margin! To provide! <Summary of the structure of the invention> In order to achieve the above object, a FROM element according to the present invention comprises a conductive first wiring layer made of a first material and a second material. A state in which the second wiring layer and the second wiring layer are placed facing each other with an insulating film interposed therebetween (for example, overlapping each other), a disconnection part is provided in the second wiring layer in the opposing part, and the disconnection part is straddled between both ends of the second wiring layer. A third wiring layer made of a third substance is formed in contact with the second wiring layer.
The first wiring layer is selected to have a melting point sufficiently lower than the melting point of the substance, and by supplying electricity to the first wiring layer, the first wiring layer is made to act as a heating element, and the heat generation is manipulated, and the material is connected to the second substance in the opposing portion. Proceed with the eutecticization of the m-question of 3,
This lowers the electrical resistance between both ends of the broken wire in the w&3 anchor layer.

よりプログ2ムできるよう構成される。It is configured to be more programmable.

このような構成に工れば、フユーズ素子は第2と第3の
配線層で形成され、プログラム動作(すなわち通電)K
工り溶断するのではなく導電度が変化する0かかるフユ
ーズ素子とプログ2fング電流が通電される発熱体(第
1の配線層)とは絶縁膜によって絶縁分離されている0
発熱体となる第1の配線層の発する熱は、第2と第3の
配線層間(フェーズ素子)を局所的に共融するに十分で
あれば工(、シたがってプログラムに要する電流を着し
く小さくすることができるofだ、発熱が小さくてすむ
ことから周囲への熱的ダメージを減少することができ、
高密度化が可能となり、加えて電流が小さいからプログ
ラム電流を駆動するトランジスタも小さくできるという
点でも高密度化の促進に寄与する0 また、共融化過程が物理的現象としても比較的静的に進
行すること、バッジページ冒ン用の絶ll膜によりPI
IOM素子を覆ったままの状態でプロゲラ建ングが可能
であること、などの点から設計余裕度の高い、信頼性に
優れたFROM素子を提供することができる0 〈発明の実施例〉 以下、本発明を図示す穣施例に基づき説明する。
With such a structure, the fuse element is formed by the second and third wiring layers, and the programming operation (i.e., energization) K
The fuse element, whose conductivity changes instead of melting, and the heating element (first wiring layer) to which the programming current is applied are insulated and separated by an insulating film.
The heat generated by the first wiring layer, which serves as a heating element, is sufficient to locally eutectic the gap between the second and third wiring layers (phase elements) (therefore, the current required for programming can be controlled). It can be made smaller and generates less heat, which reduces thermal damage to the surrounding area.
In addition, since the current is small, the transistor that drives the program current can also be made smaller, which contributes to the promotion of higher density.0 In addition, the eutectic process is a relatively static physical phenomenon. In order to proceed, the PI will not be allowed to use the badge page.
It is possible to set up a programmer while covering the IOM element, so that it is possible to provide a FROM element with high design margin and excellent reliability. The present invention will be explained based on illustrated embodiments.

〔構成〕 第2図は本発明によるFROM素子の実施例
の要部を示す平面図、第3図はその■−■断面図、第4
図はVI−Vl断面図である。
[Structure] FIG. 2 is a plan view showing the main parts of an embodiment of the FROM element according to the present invention, FIG. 3 is a sectional view taken along
The figure is a VI-Vl sectional view.

半導体基板10上には、例えば鹸化シリーン膜または窒
化シリコン膜等からなる絶縁膜題が成長さ゛れている(
第3図、第4図)。
An insulating film made of, for example, a saponified silicone film or a silicon nitride film is grown on the semiconductor substrate 10 (
Figures 3 and 4).

絶縁膜I上には厚さ約5000AIn導電性を有する第
1配線層(資)が帯状にパターン化されている。第1配
線層30に用いられる物質としては、低抵抗のn+形ま
たはP+形の多結晶シリコンが用いられるが、その他の
物質として高融点金属(MO,Pt。
On the insulating film I, a first wiring layer (material) having a thickness of about 5000 Aln and having conductivity is patterned into a band shape. The material used for the first wiring layer 30 is low-resistance n+ type or p+ type polycrystalline silicon, and other materials include high melting point metals (MO, Pt, etc.).

W、Ta等)又は高融点金属のシリサイド(硅化物)、
あるいは?形またはP1形の単結晶シリコン等を用いる
ことができる。
W, Ta, etc.) or high melting point metal silicide (silicide),
or? or P1 type single crystal silicon, etc. can be used.

第1配線層(資)上には、例えば厚さ数百Aの酸化シリ
ジン膜または窒化シリコン膜等よりなる絶縁膜菊が成長
されている(第3図、第4図)。
An insulating film made of, for example, a silidine oxide film or a silicon nitride film with a thickness of several hundred amps is grown on the first wiring layer (FIGS. 3 and 4).

この絶縁膜菊な介して第1配線層(資)上には厚さ約8
000ムの第2配線層(資)が第1配線層Iと交叉状態
にて蒸着により設けられている@したがって第1配線層
薗と第2配線層Iとは絶縁膜ωを介して対向配置されて
いる関係にある。この対向部ω上において第2配線層薗
は所定の間隙(約1μm)をもって断線されている(断
線部70)。第2配線層50に用いられる物質としては
アル1=ウム金属(以下AIと略記する。)が用いられ
る。
A thickness of about 8 cm is applied on the first wiring layer (material) through this insulating film.
A second wiring layer (material) of 000 μm is provided by vapor deposition in a state where it intersects with the first wiring layer I. Therefore, the first wiring layer and the second wiring layer I are arranged facing each other with an insulating film ω interposed therebetween. are in a relationship where On this opposing portion ω, the second wiring layer is disconnected with a predetermined gap (approximately 1 μm) (disconnection portion 70). As the material used for the second wiring layer 50, aluminum metal (hereinafter abbreviated as AI) is used.

第2配線層(資)の剛線部70の両端部間にまたがり、
第2配線層50VCI[Iシて第3配線層(資)が配さ
れている(第4図)。この第3配線層(資)は断線部面
内に入り込み、したがって絶縁膜菊な介して第1配線層
30にも対向して積層されている。第3配線層(資)K
用いられる物質としては、厚さ約8000人情抵抗のア
モルファスシリコンが用いられる0積層の際注意すべき
ことは、半導体基板10の温度!第2配線層団と第3配
線層鉛の共融共晶化温度体!と81の場合580℃)以
下に保持した状態で行なわなければならないことである
Straddling between both ends of the rigid wire portion 70 of the second wiring layer (material),
A third wiring layer (material) is arranged on the second wiring layer 50VCI (FIG. 4). This third wiring layer (material) enters into the plane of the disconnection, and is therefore also stacked facing the first wiring layer 30 with the insulating film interposed therebetween. 3rd wiring layer (capital) K
The material used is amorphous silicon with a thickness of approximately 8,000 mm. When stacking layers, one thing to be careful of is the temperature of the semiconductor substrate 10! A eutectic temperature body of the second wiring layer group and the third wiring layer lead! and 81, the temperature must be maintained below 580°C).

このようkして積層された第1eg2.第3の配線層3
0.50.80上にはパッジベージ習ン用の保饅膜美が
成長されて全体に覆われている0保護膜匍は例えば厚さ
1声mのリンガラスにより形成される0 〔ツーダラム動作〕 次に、以上の構成からなるFRO
M素子のプログツム動作について説明する0プpグライ
ングは第1配線層’XJK数mA程度の電流を流すこと
Kより行われる。すなわち、第1配線層加は発熱体(ヒ
ータ)として作用する。
The 1st eg2. Third wiring layer 3
0.50.80 A protective film for pudgebage training is grown on the entire surface, and the protective film is formed of, for example, phosphor glass with a thickness of 1 meter. Next, FRO consisting of the above configuration
The program operation of the M element will be described. Programming is performed by passing a current of about several milliamperes through the first wiring layer. That is, the first wiring layer acts as a heating element (heater).

発生した熱は対向部60において絶縁膜荀を介して第2
配線層50および第3配線層(至)を加熱する。ご仁で
、注意すべきは第1配線層I自体の融点(例えば、14
20”C)K達しないよう電流をコントーールすること
である。
The generated heat is transferred to the second part through the insulating film in the opposing part 60.
The wiring layer 50 and the third wiring layer (to) are heated. Please note that the melting point of the first wiring layer I itself (for example, 14
The current must be controlled so that it does not reach 20"C)K.

このような第1配線層30による加熱により、絶縁膜4
0が介在しているとして4対向部60における第2配線
層聞と第3配線層(資)とを共融共晶化温度(580℃
)以上Vctで高めることが可能である0第5図に示す
1うに、上述したプログラム動作を行うことにより、対
向部ω上の第2配線層父と第3配線層(資)は共融し、
共融領域側が形成される口この共融領域向の形成にエリ
、プログラム前はほぼ断線状態にあった第2配線層関の
電気抵抗は10”Ωから約(資)Ω以下に低下し、導通
状態となる0つまり、プログラム前とプログラム後の抵
抗比は約10’〜1デとなり、フユーズ素子としての第
2配線層団は実効的に非導通の開放状態から導通の短絡
状態にプログラムされる訳である。
Due to the heating by the first wiring layer 30, the insulating film 4
0 intervening between the second wiring layer and the third wiring layer (material) in the four opposing parts 60 at a eutectic temperature (580°C
) or more can be increased by Vct 0 As shown in FIG. ,
Due to the formation of the opening toward the eutectic region where the eutectic region side is formed, the electrical resistance of the second wiring layer, which was almost disconnected before the program, decreased from 10"Ω to about (material) Ω or less, In other words, the resistance ratio before programming and after programming is approximately 10 to 1, and the second wiring layer group as a fuse element is effectively programmed from a non-conductive open state to a conductive short-circuit state. This is the reason.

次に、以上のFROM素子の等価回路を第6図(a)伽
)に示す。葎)はプログラム前の開破状態におけるPR
ON素子を示し、伽)はプログラム後の短絡状態におけ
るFROM素子を示している。Hは第1配線層30に骸
娼する発熱体、Fは第2と第3の配線層間と80に和尚
するフェーズ素子を示している0 以上の説明では単一のFROM素子について説明したが
、このFROM素子を複数用いることによりメモリセル
アレイを構成できる。第7図K。
Next, an equivalent circuit of the above FROM element is shown in FIG. 6(a).葎) is PR in the open state before programming.
An ON element is shown, and 弽) shows a FROM element in a short-circuited state after programming. H indicates a heating element disposed in the first wiring layer 30, and F indicates a phase element disposed between the second and third wiring layers 80. In the above explanation, a single FROM element was explained. A memory cell array can be constructed by using a plurality of these FROM elements. Figure 7K.

FROM素子を行列配列したメモリセルアレイの例を示
す0プ四グラムするには]R+eR*・・・、R1とC
I e c、 e・・・、Cj′)組み合せを選択し、
RとCの間に電圧な印加す今ことにより任意の7エーズ
素子Fljを短轡して行う。各フェーズ素子P1jの端
子(tjl)、(1j2)はそれぞれ他のLS1回路部
に接続され、メモリ素子として利用に供せられる0 〈発明の効果〉 以上の通り、本発明によればフェーズ素子(第2、第3
の配線層)とプロゲラtング電流を流す発熱体(第1の
配線層)とは絶縁膜(介して絶縁分離された状態で対向
配置されている。そのため、フユーズ素子はこれを利用
するL 8’I回路に接続したままの状態でフユーズ素
子自身に通電することなくプqグラムすることができる
。この点において、従来の電流フユーズ方式のようにフ
ェーズ素子に直接通電してプ田グラムを行うものとは−
なり、PRO・M素子の自由度が増大することとなる0
5 また、プロゲラ建ング電流としては発熱体に対し、フェ
ーズ素子を構成する第2、第3の配線層間に共融状態を
引起こすに必要な熱を発生するに足るだけ流せばよく、
この値は一般に数mA以下でよい。そして、この値は従
来の電流フェーズ方式の場合の約1/10の値である。
To make a 0p quadrogram showing an example of a memory cell array in which FROM elements are arranged in rows and columns] R+eR*..., R1 and C
I e c, e..., Cj') Select the combination,
By applying a voltage between R and C, any 7A element Flj is shortened. The terminals (tjl) and (1j2) of each phase element P1j are respectively connected to other LS1 circuit sections and used as memory elements. <Effects of the Invention> As described above, according to the present invention, the phase element ( 2nd, 3rd
The wiring layer) and the heating element (first wiring layer) through which the progelatin current flows are placed facing each other while being insulated and separated via the insulating film.Therefore, the fuse element utilizes this L 8 ' Programming can be performed while connected to the I circuit without energizing the fuse element itself. In this respect, unlike the conventional current fuse method, programming can be performed by directly energizing the phase element. What is a thing?
0, which increases the degree of freedom of the PRO/M element.
5 In addition, it is sufficient that the progelatin current is applied to the heating element in an amount sufficient to generate the heat necessary to cause a eutectic state between the second and third wiring layers constituting the phase element.
This value may generally be several mA or less. This value is approximately 1/10 of the value in the case of the conventional current phase method.

さらに、発熱体自身Kil求される温度も低いものであ
り、発生熱による周囲への熱的ダメージも従来の電流7
!L−ズ方式のものに比べて著しく減少することができ
、そのためKFROM素子やFROM素子を駆動する電
流ドライブ素子の微細化、高密度化に適している。
Furthermore, the temperature required for the heating element itself is low, and the thermal damage to the surroundings due to the generated heat is lower than that of the conventional current 7.
! This can be significantly reduced compared to the L-Z type, and is therefore suitable for miniaturization and high density of KFROM elements and current drive elements that drive FROM elements.

加えて、第2の配線層と菖3の配線層間の共融化過程は
電流フェーズ方式の溶断過程に比べて物理的メカニズム
上静的に進行するので、設計性も高い。
In addition, the eutectic process between the second wiring layer and the wiring layer of the iris 3 progresses statically due to the physical mechanism compared to the fusing process of the current phase method, so it is highly designable.

さらKtだ、本発明のFROM素子はパッジベージ曹ン
用の保護膜すなわち絶縁膜に覆われた状態でプログラム
することが可能であり、この点についても従来の電流7
エーズ素子に比べて高信頼性が得られるものである。
Furthermore, the FROM element of the present invention can be programmed while covered with a protective film for padding, that is, an insulating film, and in this respect, the conventional current 7.
High reliability can be obtained compared to the AIDS element.

【図面の簡単な説明】[Brief explanation of the drawing]

第11aは従来電流溶断形7:L−ズ素子を示す亀ので
、(→はその等価回路図、伽)はその平面図、第2図は
本発明によるPROM素子の要部構造を示す平面図、第
3図は第2図におけるI−璽断藺図、第4図は第2図に
おけるIf−IV断面図、第5図は本発gAK:よるP
ROM素子のプロゲラ人後の状態を示す断W図、第6図
は本発明によるPROM素子の等価回路図で、(1)は
プルグラム前の状態な示す回路図、伽)はプロゲラ人後
の状態を示す回路図、第7図は本発明によるPROM素
子を用いた行列メモリ1ルアレイの例を示す等価回路図
である。 (資)・・・第1配線層、40・・・絶縁膜、(資)1
第2配線層、(イ)・・・対向部、鶏・・・断線部、(
資)・・・第3配線層、出願人代理人   猪  股゛
    溝築1図 第2図 ■」 第3図 第4図 第5図 第6図 第7図
11a shows a conventional current-fused type 7:L-Z element, so (→ is its equivalent circuit diagram, 彽) is its plan view, and FIG. 2 is a plan view showing the main structure of the PROM element according to the present invention. , Fig. 3 is the I-cut diagram in Fig. 2, Fig. 4 is the If-IV sectional view in Fig. 2, and Fig. 5 is the I-IV cross-sectional diagram in Fig. 2.
Figure 6 is an equivalent circuit diagram of the PROM element according to the present invention, and (1) is a circuit diagram showing the state before programming, and (3) is the state after programming. FIG. 7 is an equivalent circuit diagram showing an example of a matrix memory array using PROM elements according to the present invention. (Capital)...First wiring layer, 40...Insulating film, (Capital) 1
2nd wiring layer, (A)... Opposing part, Chicken... Disconnected part, (
Figure 3, Figure 4, Figure 5, Figure 6, Figure 7

Claims (1)

【特許請求の範囲】 1、導電性の第1の物質よりなり、通電により発熱する
第1の配線層と、 絶縁膜を介して前記第1の配線層に対向して配置され、
その対向部又は七の近傍において断線されている纂2の
物質よりなる第2の配線層と、前記第2の配線層上に接
しその断線部の両端部間<またがって配された第3の物
質よりなる第3の配線層と、を備え 前記第2と第3の物質とは第1の配線層が発した熱によ
って共融化する物質であり、かつその共融化温度は第1
の物質の融点より十分低いものであることを特徴とする
プログラマブル・リード・オンリ・メモリ素子0 2、特許請求の範囲第1項記載の素子において。 前記第1の物質線像抵抗の多結晶シリコンであることを
特徴とする1μグラマプル・リード・オンリ・メモリ素
子0 3.41許請求の範囲第1項記載の素子において、前記
第1の物質は高融点金属又は高融点金属のシリナイドで
あることを特徴とするプログラマブル・リード・オンリ
拳メ峰り素子。 4、特許請求の範囲第1項記載の素子忙おいて、前記第
1の物質はN形又はP形の単結晶シリコンであることを
特徴とするプログラマブル・リード・オンリ・メモリ素
子O 5,特許請求の範囲第1項、第2項または第3項記載の
素子において、前記第2の物質をアル建ニウム金属とし
、菖3の物質を高抵抗クリコンとした組み合せであると
とv特徴とするプログラマブル・リード・オンリ・メモ
リ素子。 649許請求の範囲第1項、第2項、第3項またはJI
g4項記載の素子において、前記第2の物質をアル電ニ
ウム金属とし、第3の物質をN形のシリコンとした組み
合せであることを特徴とするプqグツマプにΦリードー
オンリ・メモリ素子。 7.41許請求の範囲第1項、第2項、第3項J4項、
第5項または第6項記載の素子において、前記第1の配
線層と第2の配線層とは互に交叉する状態で対向して配
置されていることを特徴とするプロゲラiプル・リード
オンリ・メモリ・素子。
[Scope of Claims] 1. A first wiring layer made of a conductive first substance and generating heat when energized; disposed opposite to the first wiring layer with an insulating film interposed therebetween;
A second wiring layer made of the substance of Strain 2, which is disconnected at the opposing part or near the part 7, and a third wiring layer, which is in contact with the second wiring layer and is disposed astride between both ends of the disconnected part. a third wiring layer made of a substance, the second and third substances are substances that become eutectic due to the heat generated by the first wiring layer, and the eutectic temperature is equal to the first
A programmable read-only memory element 02, characterized in that the melting point of the substance is sufficiently lower than the melting point of the substance described in claim 1. 3.41 The device according to claim 1, wherein the first material is polycrystalline silicon having a beam image resistance. A programmable lead-only fist-shaped element characterized by being made of a high-melting point metal or a silinide of a high-melting point metal. 4. A programmable read-only memory device according to claim 1, wherein the first material is N-type or P-type single crystal silicon. The device according to claim 1, 2, or 3, characterized in that the second material is a combination of aluminum metal and the material of the irises 3 is high-resistance cricon. Programmable read-only memory element. 649 Claims 1, 2, 3 or JI
g4. A read-only memory element according to item g4, characterized in that the second material is a combination of aluminum metal and the third material is N-type silicon. 7.41 Claims 1, 2, 3, J4,
In the device according to item 5 or 6, the first wiring layer and the second wiring layer are arranged to face each other in a state where they intersect with each other. Memory/Element.
JP56172541A 1981-10-28 1981-10-28 Programmable read-only memory element Pending JPS5877098A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP56172541A JPS5877098A (en) 1981-10-28 1981-10-28 Programmable read-only memory element
US06/428,614 US4814853A (en) 1981-10-28 1982-09-30 Semiconductor device with programmable fuse
DE8282305624T DE3278653D1 (en) 1981-10-28 1982-10-22 A semiconductor device having a control wiring layer
EP82305624A EP0078165B1 (en) 1981-10-28 1982-10-22 A semiconductor device having a control wiring layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56172541A JPS5877098A (en) 1981-10-28 1981-10-28 Programmable read-only memory element

Publications (1)

Publication Number Publication Date
JPS5877098A true JPS5877098A (en) 1983-05-10

Family

ID=15943796

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56172541A Pending JPS5877098A (en) 1981-10-28 1981-10-28 Programmable read-only memory element

Country Status (1)

Country Link
JP (1) JPS5877098A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6285442A (en) * 1985-10-09 1987-04-18 Mitsubishi Electric Corp Redundancy circuit for semiconductor device
US5366928A (en) * 1988-01-29 1994-11-22 U.S. Philips Corporation Method of manufacturing a semiconductor device, in which a metal conductor track is provided on a surface of a semiconductor body

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6285442A (en) * 1985-10-09 1987-04-18 Mitsubishi Electric Corp Redundancy circuit for semiconductor device
US5366928A (en) * 1988-01-29 1994-11-22 U.S. Philips Corporation Method of manufacturing a semiconductor device, in which a metal conductor track is provided on a surface of a semiconductor body

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