JPH0365722A - Floating-point arithmetic unit - Google Patents

Abstract

PURPOSE:To simplify a circuit, and besides, to reduce power consumption, and to detect underflow and overflow at high speed by executing the arithmetic operation of an exponent part by using one adder or one subtracter. CONSTITUTION:The exponent part of a computed result is obtained by converting once the exponent part into the complement of '2' by logical- inverting 101 the exponent part, and converting again the computed result between the complements of '2' into the complement of '2'. Since the addition of deviation quantity at the time of the subtracting or the dividing the deviation quantity in the case of floating-point multiplication is computed by being included in the correction of the complement of '2', it can be executed by using one adder 103 or one subtracter in spite of the arithmetic operation of three numbers. Besides, the logical inversion 101, 102, 104 of the exponent part required for the conversion into the complement of '2' needs only to change some logic at the time of generating carry, propagating the carry and generating final sum of the usual adder, and it can be realized without adding any extra hardware. Thus, since the arithmetic operation of the exponent part can be executed by using one adder or one subtracter, hardware quantity can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to floating point arithmetic devices, particularly IEEE 754
The present invention relates to a floating-point arithmetic device that performs standard-compliant floating-point multiplication and floating-point division operations.

(Prior Art) First, floating point number operations according to the IEEE754 standard will be explained. The floating point number according to the IEEE754 standard is (-1)"・2g-"-(1,F) ・-・・・(
In equation (1), S is a sign bit, E is exponent part data, B is a deviation amount for shifting E in the positive direction, and F is mantissa part data.

If the number of digits of the exponent is n, then B = 2" + 2" 1+...21+ 1 = 2"
-1-1 format. For single-precision floating point numbers, n=8 and B=127. F is 23 digits long.

In the case of double-precision floating point numbers, n=11 and B=1
023, F is 52 digits long. Operand number X, operand number Y
of.

X=(1)”21IX-”(1,Fx) −・=(
2)X=(-↓)'Y 2"-"-(1,FY)
...-(3), the calculation of the exponent part in the case of multiplication is (Ex-B)+(EY-B)=(Ex+EY-B)
-B・・・・・・(4), and the calculation of the exponent part in the case of division is (EX-B)-(EY-B)=(EX-E
Perform as Y+B)-B...-(5). That is,
The exponent part of the product is obtained by adding the exponent part of the multiplicand and the exponent part of the multiplier and subtracting the deviation fB from the result, and the exponent part of the quotient is obtained by subtracting the exponent part of the multiplier from the exponent part of the multiplicand, and It is obtained by adding the deviation amount B to the result.

FIG. 7 shows the configuration of an exponent part calculator of a conventional floating point arithmetic unit. In Figure 7, 701 is the n-digit exponent part E of the multiplicand and the n-digit exponent part E of the multiplier.
, 711, and 702 is the I-th adder 7.
a second adder that adds the output of 01 and the two's complement 712 of the deviation amount B, and outputs the calculation result (E, +EY-B) 713;
703 is a detector that compares the output of the second adder 702 with a predetermined value to detect underflow or overflow of the multiplication result; 714 is an underflow signal output from the detector 714; and 715 is an overflow signal. In addition, in the case of division, the exponent part arithmetic unit is configured such that the I adder 701 in FIG. 7 is changed to a subtracter, and the second adder 702 adds the output of the subtracter and the deviation amount B. This is achieved by

(Problem to be Solved by the Invention) However, in the above conventional exponent calculator, ■EEE7
In a floating-point arithmetic unit that performs floating-point multiplication or floating-point division in accordance with the X.54 standard, two adders are required to calculate the exponent part, resulting in an increase in the scale and complexity of the overall circuitry of the device. was there. Furthermore, as the circuit size increases, power consumption increases and the time required for calculation increases. Furthermore, since underflow and overflow were detected by performing addition in the second adder and then comparing the calculation result with a predetermined constant, it took a long time to obtain all the calculation results. , there was a problem in executing floating point operations at high speed.

The present invention solves the above-mentioned conventional problems, and by performing calculations on the exponent part with a single adder or subtracter, the circuit is simple and consumes less power, and underflows and overflows can be detected quickly. The object of the present invention is to provide a floating point arithmetic unit that performs the following functions.

(Means for Solving the Problem) In order to achieve the above object, the present invention provides a first means for inputting one of an operand or an exponent part of an n-digit length of an operand, inverting the logic, and outputting the result. , and a second means for inputting the other exponent part and logically inverting the n-2nd to 0th digits and outputting the resultant, and in the case of floating point multiplication, the output of the first means and the second means are provided. In addition, in the case of floating point division, from the exponent part of the dividend logically inverted by the first means or the second means, the second means or the second means or the output is added. a subtracter for subtracting the exponent part of the divisor whose logic has been inverted by means of step 1;

The apparatus further includes third means for inverting the output of the adder or subtracter, and the output of the third means is used as the exponent part of the calculation result.

(Function) Therefore, according to the present invention, the exponent part of the operation result is obtained by first converting the exponent part into a two's complement number by inverting the logic, and then converting the operation result between the two's complement numbers again into a two's complement number. ing. The subtraction of the deviation amount in the case of floating point multiplication or the addition of the deviation amount in the case of floating point division is calculated by including it in the two's complement correction, so despite the operation of three numbers, Can be implemented with one adder or subtracter. In addition, the logic inversion of the exponent part required for two's complement conversion requires only slight changes to the logic during carry generation, carry propagation, and final sum generation of the ordinary adder, and requires no additional hardware. It can be achieved without any problem.

(Embodiment) FIG. 1 shows the configuration of a multiplier exponent part arithmetic unit of a floating point arithmetic unit in a first embodiment of the present invention.

The embodiment shown in FIG. 1 deals with single-precision floating point numbers according to the IEEE754 standard, and the exponent part has a data width of 8 digits. In Figure 1, 101 is the exponent part 11 of the multiplicand.
A first logic inversion circuit that generates a logic inversion of 0, 102 a second logic inversion circuit that generates a logic inversion of the lower seven digits (6th digit to Oth digit) of the exponent part 111 of the multiplier, and 103 a 1
．． An adder that adds the output of the second logic inversion circuit 101, 102 and the most significant digit (seventh digit) 114 of the exponent part 111 of the multiplier; 104 is a third logic inversion that logic inverts the output of the adder 103; It is a circuit, and the calculation result (Ex+EY-1
27; B=2I'-1-1=127) Outputs 112. 105 is the most significant digit (7th digit) of the exponent part of the multiplicand
113 and the most significant digit (7th digit) 114 of the exponent part of the multiplier are both "O" and there is a carry 117 from the 6th digit of the adder 103, an underflow occurs, and the exponent part of the multiplicand 2 multiplier The most significant digits 113 and 114 are both "l"
106 is a multiplicand.

The most significant digits 113 and 114 of the exponent part of the multiplier are both “1”
” and all the outputs of the third logic inversion circuit 104 are “work”, the second detector detects an overflow. 116.117 is a carry output from the 6th digit of the adder 103. Initial carry to 0th digit C+411
6118, which is a carry when there is no 5 and when there is a 5, is an underflow signal, 119 is a first overflow signal,
120 is a second overflow signal.

Next, the operation of the first embodiment will be explained.

As shown in equation (4) above for the IEEE754 standard, the exponent part calculator of the multiplier calculates E2=Ex+EY-B=Ex+Ev-2n-1+1 --- (6). However, in the case of the embodiment shown in FIG. 1, n=8.

This equation (6) is converted into the two's complement relational expression -A=A+1 ・
...Using (7), transform as follows. Note that in equation (7), A is a number in which each digit is expressed in two numbers, and A is a number obtained by inverting the logic of each digit of A.

E, =Ex+EY-21'-"+1 =Ex+1+EY+1-211-1-1=-(Ex+E
Y+2'-')-1 = Ex 1EY+2'1-1 ・・・-(
8) Equation (8) shows that the exponent part operation of floating-point multiplication can be performed by adding the logical inversion of the exponent part of the multiplicand, the logical inversion of the exponent part of the multiplier, and 2n-1, and inverting the addition result. It shows. The addition of 2111-1 can be realized by not inverting the logic of the most significant digit of either the multiplicand or the multiplier. Detection of underflow and overflow in the first embodiment will be explained. (1) In the numerical expression shown in Eq.

Underflow is defined as (E-B)≦-B (9), and overflow is defined as (E-B)≧B+1 (10). In the case of multiplication of single-precision floating point numbers, Figure 2 shows the value of E + Ey + 2'' for the value of Ex + EY.
−”−Ez=Ex+Ey 1,2°−1 It shows each value It. From Figure 2 and equations (9) and (io), it is generally possible to multiply floating point numbers with an exponent part of n digits width. The following term is derived as the underflow condition.

■ The nth -1st digit of Ex and EY are both "O" and -
If all digits of 100, 10E, +2" are 1"".

■ Both the n-1st digit of Ex and E7 are “OF+” and E
From the n-2nd digit to the m-th digit of x and EY (n-2≧m≧0: m
is an integer) in each consecutive digit
If there is.

The above equation (2) is derived from the fact that Ex+EY=127 in FIG. 2 results in an underflow. Also, ■ is Ex+E,
≦126 (01111110: binary representation) This is derived from the fact that there must be no carry with the 7th digit being ``17F.'' Also, for floating point numbers with an exponent part that is n digits wide, The following term is derived as a condition for overflow in multiplication.

■ The n-1st digits of Ex and E are both “l” and E
t = Ex + E Y + 2'' - When all the digits of 1 are 1''.

■ The n-1st digits of Ex and E are both “l” and Ex
and the n-2nd digit to the n+1st digit of EY (n-2≧Flood≧0:
Q is an integer) when there is a 1 in at least one of the consecutive digits.

The above equation (2) is derived from the fact that Ex+EY=382 in FIG. 2 is an overflow. Also, ■ is Ex+EV=38
3 becomes an overflow, and Ex 1 EY ≧ 384
(110000000: binary representation).

This is derived from the fact that a carry is required so that the seventh digit of Ex+EY becomes #I II. Here, E, 10E, +2”-”
Pay attention to the carry increase.

Ex=X,,X,,---X1X.

EY=Yゎ-, Yゎ-2... If we set Y-Y0, the carry C of the first digit (i≦n-2) is expressed by the following logical formula.

C+ =
x) Cr −z=X+ “Yt”(Xt”Yt)Xt
-1” Yt -x+(x++y+) (edited:・Kun;)edited;・line:+・・・・・・+(Xt+Y+)(mouth・[)・
・・・・・・(revised+Y2) (x,+Y,)X,・
Yo"(XT"y,)(mouth・[;)・・・・・・・・・(
"10th edition) (revised + Yi) (proof 10th edition) C-1 In the above formula (11), formula (11) is when there is an initial carry C-0 and a carry C from the first digit. is the first to fifth digit (i≧j
) at least one of the two numbers with consecutive digits up to “Q I
It shows that t. Furthermore, from equation (8), C-□
The value of E8 according to the setting is E2=Ex+EY+2″″′
1+1=Ex+Ev-211-1...(12)
It follows that That is, in FIG. 2, by setting the initial carry C-1, a carry occurs from the 6th digit when Ex+E≦127. Therefore, when the digit width of the exponent part is n, if both the n-1st digits of two numbers are "0", there is an initial carry, and there is a carry from the n-2nd digit, the above underflow occurs. This corresponds to condition (2), and by determining this, underflow can be detected. In the embodiment of FIG.
A carry 117 from the digit corresponds to the above carry, and an underflow is detected by an underflow signal 118. On the other hand, by reversing the logic of the carry of the first digit, the result becomes as shown in the following logical formula.

= Xi ・Yl+ (Xl+Yt)Ct-1"XI"
Yt"(XI"Yt)XI-1-Y,-0"(XI"
Yt) (XI-1"Yt-8)c+-=x+ ・Yt
”(Xt”Yt)XI −t ・Yt −1+(X++
Yt) (XI-t”Yt-z)XI-z S Y, -,
4+-++++” (XI”Yt) (XI-1”Yt-2
) ” ””” ” (Xz”Yt) (Xz”Yt)X
oY.

+(X1+Y1)(XI-8"Yt-u) ・ --
・ (X2”%) (Xt”Yx) (Xo+Yo)C-x
”Formula (13) has no initial carry C-1 (τ;=1)
And if there is no carry from the 1st digit, the 1st to 5th digit
This indicates that at least one of the two consecutive digits up to the digit (i≧j) is “1”. Therefore, when the digit width of the exponent part is n, if both the n-1st rows of the two numbers are "1" and there is no initial carry and there is no carry from the n-2nd digit, the above overflow occurs. This corresponds to condition (2), and by determining this, overflow can be detected.

In the embodiment of FIG. 1, carry 11 from the 6th digit of the adder
6 corresponds to the above carry and the above overflow condition■
is caused by the first overflow signal 119, and the above overflow condition (2) is caused by the second overflow signal 119.
20.

FIG. 3 shows the first to third logic inversion circuits IOT, which are the main components of the exponent calculator shown in FIG. 1, 102°10
4 shows the logic circuits of the adder 103 and the first detector 105. In this circuit, carry generation and propagation are performed by a carry look-ahead circuit. In FIG. 3, 301 is a generation circuit for a carry generation signal (G,) and a carry propagation signal (P,), 302 is a carry propagation circuit, 303 is a final phase determination circuit, and 310 and 311 are the 6th digit. This is a logical inversion signal of a carry from 0 to 0, and is a signal when there is no initial carry to the 0th digit and when there is an initial carry. In a normal adder, a carry generation signal P and a carry propagation signal Gl are defined as follows.

G, =X, -Y, ......(14)p, =x
,■Y, ......(15) Generate and propagate a carry using these two signals, and carry C from one digit below.
By using 1-1, the following formula is obtained as the final phase S.

5i=Pl■C1-□ ・・・・・・(16) On the other hand, in this embodiment, the numbers obtained by inverting the logic of each digit are added, and the logic inversion of the addition result is taken as the final sum, so one digit is increased. Signal 011 carry propagation signal P6, final phase S, is expressed by the following logical formula.

G, =X, ・y, =x, +y, ...... (17
)P, =X+$Y+=XteY+ −−−−−−(
i8) S, = p, ■C, -8 ...... (19) (
17), (18), and (19), 1
The exponent arithmetic unit of this embodiment changes the carry generation logic of the ordinary adder from AND (logical product) to N0R (logical inversion of logical sum), and changes the ordinary final phase determination logic to X0R (exclusive logical sum). ) to XN0R (logical inversion of exclusive OR). Therefore, the logic inverting circuit for the exponent part input and the logic inverting circuit for the adder output can be configured without adding any extra inverter circuit or the like. In addition, 2. of the final sum. , 2. , 2° determines its value using the logical inversion signal of the carry from the lower digit, so XNOR
It uses an XOR circuit instead of a circuit. In addition, since only the 7th digit of the exponent part of the multiplier is not logically inverted, the carry propagation logic circuit for the 7th digit is an XNOR circuit without using an XOR circuit.
using a circuit. Further, in this embodiment, the most significant digit of the exponent part of the multiplier is not logically inverted, but the same function can be achieved even if the most significant digit of the exponent part of the multiplicand is not logically inverted.

Next, the case of division will be explained.

FIG. 4 shows the configuration of the exponent part arithmetic unit of the divider of the floating point arithmetic unit in the second embodiment of the present invention.

In this case as well, single-precision floating point numbers according to the IEEE754 standard are handled, and the exponent part has a data width of 8 digits. In FIG. 4, 401 is a first logic inversion circuit that generates a logic inversion of the exponent part 410 of the dividend, and 402 is a logic inversion circuit that generates the logic inversion of the lower seven digits (6th to 0th digits) of the exponent part 411 of the divisor. A subtracter 403 subtracts the output of the logic inversion circuit 402 and the number 414 of the most significant digit of the exponent part of the divisor from the output of the logic inversion circuit 401;
4 is a third logic inversion circuit that inverts the logic of the output of the subtracter 403, and the calculation result (Ex Ey + 127
; B = 2"-'1 = 127) Outputs 412. 405 is the most significant digit (7th digit) of the exponent part of the dividend 41
If 3 is at Orp and the most significant digit (7th digit) 414 of the exponent part of the divisor is "'l"' and there is no borrow 416 from the 6th digit of the subtraction circuit 403, an underflow occurs, and the dividend The most significant digit 413 of the exponent part is u 1 u, the most significant digit 414 of the exponent part of the divisor is "0", and the subtraction circuit 4
The first detector 406 detects an overflow when there is a borrow 417 from the 6th digit of 03. A second detector 418 is a first underflow signal that detects an underflow when the signal is "1" and all outputs of the third logic inversion circuit 404 are II OFj.

419 is an overflow signal, and 420 is a second underflow signal.

Next, the operation of the second embodiment will be explained.

As shown in equation (5), in the exponent part calculator of the divider in Fig. 4, EZ=Ex-EY+B=Ex-EY+2"-'-1-・
... Find (20). However, in the case of Figure 4, n=8
It is.

This equation (20) is transformed as follows using the two's complement relational equation (7).

Ez=Ex EY+2"-11: Ex+1-(Ey+1)+2"-1 =-(Shoulder analysis-2"-")-1 = Ex-E, -2"-'-1-...(21) (20
) formula shows that the exponent part operation of floating-point division can be performed by subtracting the logical inversion of the exponent part of the divisor and 2n-1 from the logical inversion of the exponent part of the dividend, and inverting the logic of the subtraction result.2 Subtraction of m-1 can be realized by not logically inverting the most significant digit of either the dividend or the divisor. Next, detection of underflow and overflow in the embodiment shown in FIG. 4 will be explained. Figure 5 shows E for the value of Ex-EY in the case of division of single-precision floating point numbers.
It's something like x. From Figure 5 and equations (9) and (10),
Generally, the following term is derived as an underflow condition in division of a floating point number having an exponent part with an n-digit width.

■ The n-1st digit of EX is 0” and all the n-1st digits of EY are l.
(In case of 0”.

■ The n-1st digit of Ex is # OII and the n-th digit of EY
The 1st digit is “1” and the n-2nd to mth digits (n-2≧m
The value of Ex in each digit up to ≧O: m is an integer is “OI
When the value of T or EV is "1 jj.

(2) is derived from the fact that EX EY=127 becomes an underflow in FIG. Also, ■ is Ex-E
Underflow occurs when Y≦−128.

This is derived from the fact that in order to obtain Ex Ev≦-129 (101111111: binary representation), it is necessary to borrow a digit by setting the 7th digit to 0.Also, for a floating point number with an exponent part that is n digits wide, The following term is derived as a condition for overflow in division.

■ The n-1st digit of Ex is "l" and the n-L digit of EY is it Ou, and all digits of 100, -E, -2'-' (n-th digit
1st digit to 0th digit) are all 0".

■ The n-1st digit of E9 is “1” and the n-1st digit of EY is 0
” and from the n-2nd digit to the α+1st digit (n-2≧danger≧0:
If the value of Ex is 11 in each consecutive digit up to (Q is an integer)
1 If the value of Tl or E7 is 110 IP, the last digit of Ex is "1", and the third digit of E7 is O'''.

(2) is derived from the fact that Ex-EY=182 in FIG. 5 is an overflow. ■ is Ex-EY≧129 (100
00001: (binary representation), Ex-E
This is derived from the fact that the 7th digit of 7 is '1' and at least one digit from the 6th digit to the 0th digit must be '1'.

Here, similarly to equations (11) and (13), find the borrow from the first digit (i≦n-2) of 1;-hundred;-2''-1.

Bi=X+・Row+([10 rows)B, -0 =X,・Y,+(X++Y'T)B+-0=X1Y++
(Xt”YI)Xt-0'Y+-x+(xt+D (x
+ −x”Yi −t)Xt −z ・Y, −, 4+−
+++++"(Xt"'-1)(XI-t"Yt-t)
” ””” ' (Xz”Yz) (X-”Yx)Xo・
Y.

+(Xl+Yi) (XI-1+Y=1) ---...--
--(Xt"Ya) (Xt"Yz) (Xo"Yo)B-
Formula t(22) has an initial digit borrow B-1 and a digit borrow from the 1st digit, then the 1st to 5th digits (i≧, j
) indicates that xk is l(0)l or Yk is 1'' (i≧ and ≧j).

Furthermore, from equation (21), E,! due to the setting of B-1. It is derived that the value of Et=Ex Ey 2″-11 =Ex-EY+2″-1−·−−−(23). That is, Ill in FIG.

By setting , a carry occurs when Ex-EY≧128. Therefore, when the digit width of the exponent part is n,
If the n-1st digit of the exponent part of the dividend is 1 (I I+, and the n-1st digit of the exponent part of the divisor is 1107+, and there is an initial digit borrowing and a digit borrowing from the n-2nd digit) This corresponds to the above overflow conditions ■ and ■, and overflow can be detected by determining this. In the example of FIG. 4, the borrow 417 from the 6th digit of the subtractor corresponds to the borrow. The overflow is detected by the overflow signal 419. On the other hand, the logical inversion of 1 in the borrow of the first digit is expressed by the following logical formula.

2 drunkenness, Y, + (red + Y,) mouth, Y, -□” (X++Y+
)(x+-x"YI-t)Xt4"Yr-x"
""'+(x, +y+)(x+-z+yt-t) ・
...... (X2+Y2) (nu5yt)nu;Y
.

+(x++yt)(nu]=2:+Yi-1)...
...(nu l;"yJ (nuni + y1) (Y in xa,)
100=:1 Formula (24) has no initial borrowing E3t-z.
(TT'T= 1) and there is no digit borrowing from the first digit, then in each consecutive digit from the first digit to the fifth digit (i≧j), Xk is “O11” or Yk is ItllI(i≧ to≧j
). Therefore, if the digit width of the exponent part is n, the n-1st digit of the exponent part of the dividend is 110
In G1, if the n-1st digit of the exponent part of the divisor is 'l'', there is no initial digit borrowing, and there is no digit borrowing from the n-2nd digit, it corresponds to the underflow condition (■) above. Underflow can be detected by finding the digit 416 in the embodiment shown in FIG. The underflow condition (2) is detected by the second underflow signal 418 and the second underflow signal 420.

FIG. 6 shows first to third logic inversion circuits 401 and 402, which are the main components of the exponent arithmetic unit in the embodiment shown in FIG.
．． 404. This is a logic circuit of a subtracter 403 and a first detector 405. This circuit also uses a carry look-ahead circuit to generate and propagate a borrow as in FIG. In FIG. 6, 601 is a generation circuit for a borrow generation signal (G1) and a borrow propagation signal (P, ), 602 is a borrow propagation signal, 603 is a final sum determination circuit, and 610.611 is from the 6th digit. These are the logical inversion signals of digit borrowing, and these are the signals when there is no initial digit borrowing to the 0th digit and when there is, respectively.

In this case, the borrow generation signal Giy, the borrow propagation signal P1.
The final sum Sl is obtained in the same way as equations (17), (18), and (19), and is as follows.

G, =XhiY I=X + childcare (25
)p, =x, ■Y, =X, ■Y, ・・・－・・・(
26) s, = p, ■B, -1... (27)
Therefore, as in the case of FIG. 3, this case can be realized by only slightly changing the logic of one ordinary subtracter's borrow generation, single-digit borrow propagation, and final sum determination.

In the above embodiment, the most significant digit of the exponent part of the divisor is not logically inverted, but the same function can be achieved even if the most significant digit of the exponent part of the dividend is not logically inverted.

(Effects of the Invention) As is clear from the above embodiments, in floating-point multiplication or division, the present invention performs an operation between the exponent part of the operand, the exponent part of the operand, and a predetermined constant using two's complement. By using the relationship, the calculation is performed by only adding or subtracting two exponent parts, so it has the following effects.

(1) The amount of hardware can be reduced because the calculation of the exponent part can be executed with one adder or subtracter.

(2) By using carry or borrow used in internal calculations, underflows and overflows can be detected at high speed.

(3) The amount of hardware required to detect underflow or overflow can be reduced.

(4) As the amount of hardware decreases, power consumption also decreases, making it possible to speed up floating-point operations.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the exponent part calculation unit of the floating point arithmetic unit multiplier in the first embodiment of the present invention, FIG. 2 is an explanatory diagram of the exponent part calculation of the floating point multiplication shown in FIG. 1, and FIG. 3 is a circuit diagram of the exponent part calculator of the multiplier in the first embodiment, FIG. 4 is a block diagram of the exponent part calculator of the floating point arithmetic unit divider in the second embodiment of the present invention, and FIG. Fig. 4 is an explanatory diagram of the exponent part operation of floating-point division, Fig. 6 is a circuit diagram of the exponent unit of the divider in the second embodiment, and Fig. 7 is used in the multiplier of the conventional floating-point arithmetic device. FIG. 101, 401...first logic inversion circuit, 102
゜402...Second logic inversion circuit, 130...Adder, 104.404...Third logic inversion circuit, 105
, 405... I-th detector, 106.406... Second detector, 110... Exponent part of multiplicand, 11
1...Exponent part of multiplier, 112°412, 713...
・Arithmetic result, 113...most significant digit of exponent part of multiplicand,
114...The most significant digit of the exponent part of the multiplier, 115...
Initial carry, 116, 117... Carry from the 6th digit of the adder, 118.714... Underflow signal,
119...first overflow signal, 120°・
Second overflow signal, 301... Carry generation signal and carry propagation signal generation circuit, 302... Carry propagation circuit, 303° 603... Final phase determination circuit, 310
．． 311... Logical inversion signal for carry, 403... Subtractor, 410... Exponent part of dividend, 411... Exponent part of divisor, 413... Most significant digit of exponent part of dividend, 414 ...The most significant digit of the exponent part of the divisor, 415.
... Initial digit borrow, 416°417... Digit borrow from the 6th digit of the subtractor. 418...first underflow signal, 419°71
5... Overflow signal, 420... Second underflow signal, 601... Generation circuit for a borrow generation signal and borrow propagation signal, 602... Borrow propagation circuit, 6
10.611...Logic inversion signal of borrowed digit, 701...
- First adder, 702... Second adder, 703...
Detector, 710... n-digit exponent part of multiplicand, 711.
...N-digit exponent part of the multiplier, 712...2's complement of deviation amount B. Figure 1 116.117゛ 6th attack Goka et al. (I beak top 1 item) Bud - Touge wholesale mackerel Figure 7 714 Bottom> Riper flowy No. 6

Claims (4)

[Claims] (1) From the n-1st digit to the 0th digit (the most significant digit is the n-1st digit,
In the multiplication of floating point numbers having an n-digit exponent part up to n ≥ 2, n is an integer), the first function inputs the exponent part of either the multiplicand or the multiplier, logically inverts each digit, and outputs it.
means for inputting the exponent part of the other number, logically inverting each digit from the n-2nd digit to the 0th digit and outputting the same; and a third means for logically inverting the output of the adder, and the output of the third means is used as an exponent part of the multiplication result. A floating point arithmetic unit with special features. (2) When the n-1st digit of the exponent part of the multiplicand and the n-1st digit of the exponent part of the multiplier are both "0" and the initial carry is input to the adder, the n-2nd digit If there is a carry, it is considered an underflow, and the nth of the exponent part of the multiplicand is
-1 digit and the n-1 th digit of the exponent part of the multiplier are both "1"
” and the outputs of the third means are all “1”,
Or, if the n-1st digit of the exponent part of the multiplicand and the n-1st digit of the exponent part of the multiplier are both "1" and there is no carry from the n-2nd digit of the adder, an overflow occurs. The floating point arithmetic device according to claim 1, characterized in that: (3) From the n-1st digit to the 0th digit (the most significant digit is the n-1st digit,
In the division of a floating point number that has an n-digit long exponent part (up to n ≥ 2, n is an integer), the first function inputs the exponent part of the multiplicand or the exponent part of the divisor, logically inverts each digit, and outputs it.
and a second means for inputting the exponent part of the divisor or the exponent part of the dividend and logically inverting the n-2nd to 0th digits and outputting the result.
and subtracting the exponent part of the divisor whose logic has been inverted by the second means or the first means from the exponent part of the dividend which has been logically inverted by the first means or the second means. A floating point arithmetic device comprising a subtracter and third means for logically inverting the output of the subtracter, the output of the third means being an exponent part of the division result. (4) When the n-1st digit of the exponent part of the multiplicand is "0", the n-1st digit of the exponent part of the divisor is "1", and all outputs of the third means are "0", or The n-1st digit of the exponent part of the dividend is "0" and the n-th digit of the exponent part of the divisor is "0".
An underflow occurs when one digit is "1" and there is no borrowing from the n-2nd digit of the subtracter, and the exponent part of the divisor has an exponent part where the n-1st digit of the exponent part of the dividend is "1". nth of
Floating according to claim 3, characterized in that if the first digit is "0" and there is a digit borrow from the n-2nd digit when the initial digit borrow is input to the subtracter, an overflow occurs. Decimal point arithmetic unit.