JPH0364967A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a DRAM of laminated type memory cell structure which is high in reliability and can be highly integrated by a method wherein a field oxide film is formed, then an oxide film is formed thereon once, the oxide film is selectively removed only from a region where a gate electrode is formed, and a gate oxide film is formed again. CONSTITUTION:An element isolation insulating film 202 is formed on the surface of a P-type silicon substrate 201 through a selective oxidation method, and then a silicon oxide layer 203s is formed through a thermal oxidation method. Then, a silicon nitride layer and silicon oxide layer are successively removed, and the silicon oxide layer 203s is formed. Thereafter, a resist pattern R provided with an opening W only at a gate electrode forming region is formed. The silicon oxide layer 203s on the surface of the substrate 201 exposed through the resist pattern R is removed by etching. Then, the resist pattern R is removed, and a silicon oxide film 203 is formed as gate oxide film.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, particularly in a LOCO
This invention relates to an element isolation method using the 8 method.

(Prior Art) In recent years, with advances in semiconductor technology, particularly advances in microfabrication technology, semiconductor devices are rapidly becoming more highly integrated and have larger capacities.

With this increase in integration, even in so-called MO8 type DRAM, the area of the capacitor that stores information (charge) is decreasing, resulting in the memory contents being read out incorrectly or being destroyed by alpha rays, etc. Problems include soft errors.

One way to solve these problems and achieve higher integration and larger capacity is to stack MOS capacitors on the memory cell area, and connect one electrode of the capacitor with a MOS capacitor formed on the semiconductor substrate. A memory cell structure called a stacked memory cell has been proposed in which the capacitance of a MOS capacitor is substantially increased by making the capacitance of a MOS capacitor conductive with one electrode of a switching transistor.

As shown in FIG. 8, this stacked memory cell consists of an element isolation insulating film 10 formed in a p-type silicon substrate 101.
In one memory cell region separated by 2, a source and drain region 103 made of an n-type diffusion layer and a gate insulating film 104 are provided between the source and drain regions 103.
The gate electrode 105 of the MOSFET and the gate electrode (word line ) on the insulating film 106 (-silicon oxide film 106 by CVD method)
a and BPSG film 106b) and a bit line 109 made of polycrystalline silicon film 107 and silicide 11108, and an insulating film 110 (C
A first capacitor electrode 1 formed via a silicon oxide film 110a and a BPSG film 110b by VD method
12 and a capacitor insulating film 114 sandwiched between a second capacitor electrode 113 and a capacitor.

This stacked memory cell is formed as follows.

That is, first, field oxidation is performed for device isolation, and then the silicon surface under the silicon nitride film is oxidized to remove damage sustained during field oxidation, and the oxide film is removed. A method of forming an oxide film is used.

This is called a white ribbon countermeasure, and during field oxidation, a nitride film or oxynitride film is formed on the silicon surface by the action of NH3 generated from the silicon nitride film that serves as a mask. This is done to prevent growth of the gate oxide film in this portion, which may cause deterioration of the breakdown voltage of the gate oxide film and deterioration of other characteristics.

After forming the gate oxide film 104 in this manner, a gate electrode 105 is formed, and ions are implanted into the p-type silicon substrate 101 using the gate electrode as a mask.
A source and drain region 103 made of an n-type diffusion layer is formed, and a MOSFE as a switching transistor is formed.
Form a T.

Next, a silicon oxide film 1 is formed around the gate electrode 105.
After coating with 06s and 106t, a silicon oxide film 10 is further formed by CVD as an insulating film 106 over the entire surface of the substrate.
6a and BPSGM 106b are formed and planarized by heat treatment. After that, a bit line contact for contacting the drain region 103 is formed, and a bit line 109 made of a polycrystalline silicon film 107 and a silicide film 108 is formed. do.

After that, the entire surface of the substrate is insulated [110] and a silicon oxide film 110a and a BPSG film 110b are formed by the CVD method.
After forming, planarization is performed by heat treatment to form a storage node contact 111, and a first capacitor electrode 11 made of a heavily doped polycrystalline silicon layer is formed.
2 patterns are formed.

Then, by sequentially depositing and buttering a capacitor insulating film 113 made of a silicon oxide film and a polycrystalline silicon layer on this first capacitor electrode 112,
Second capacitor electrode 114 and first capacitor electrode 1
12 with a capacitor insulating film 113 sandwiched between them.
A capacitor is formed and a memory cell consisting of a MOSFET and a MOS capacitor is obtained.

In such a configuration, the storage node electrode can be extended to above the element isolation region, and the step of the storage node electrode can be used, so the capacitance of the capacitor can be increased several to several tens of times that of the brainer structure. can.

Therefore, even if the memory cell area is reduced, the amount of stored charge can be prevented from decreasing.

Furthermore, the diffusion layer in the storage node part is only the diffusion layer 103 under the storage node electrode (first capacitor electrode 111), and the area of the diffusion layer that collects the charge generated by α rays is extremely small. It has a strong structure.

However, when such a process is used, the following problems arise when the memory cells are further miniaturized.

That is, as shown in FIG. 9(a), after field oxidation, NH generated from the silicon nitride film that serves as a mask
In order to remove the nitride film or oxynitride film formed on the silicon surface by the action of step 3, oxidation is performed once to form an oxide film 104S, as shown in FIG. 9(b).
A method is used to remove this oxide film 104S.

However, this method has a problem in that the width of field oxide film 102 is reduced.

As a result, as shown in FIG. 9(C), when the diffusion layer 103 is formed by ion implantation, the lateral extension of the diffusion layer is determined by the width of this field oxide film, so the lateral extension is smaller than the designed value. It becomes an elongated shape.

Then, as shown in FIG. 9(d), the direct contact process is performed after the interlayer insulating film formation process, but if lithography misalignment occurs during the formation of the direct contact hole, the diffusion layer The lateral elongation and the lateral elongation of impurities due to the ion implantation process for establishing direct contact are close to each other, making it difficult to suppress leakage between direct contacts.

This has been a major problem that hinders the miniaturization of devices.

Note that in this figure, other regions including the gate electrode are omitted.

(Problems to be Solved by the Invention) As described above, not only DRAMs with a stacked memory cell structure, but also as elements become finer due to higher integration, oxidation after field oxide film formation based on white ribbon countermeasures is becoming more important. A problem has been the occurrence of leakage between direct contacts due to the increase in the width of the diffusion layer due to the reduction in the width of the field oxide film due to the process of forming and removing the film.

The present invention has been made in view of the above-mentioned circumstances, and is a DRA with a stacked memory cell structure that can be highly integrated and has a high reliability.
The purpose is to provide semiconductor devices including M.

[Structure of the invention]

(Means for Solving the Problem) Therefore, in the present invention, after forming a field oxide film, after forming an oxide film on the surface, selectively remove the oxide film only in the region where the gate electrode is to be formed, and then re-form the oxide film. A gate oxide film is formed.

(Function) According to the above method, after the oxide film is formed, this oxide film is removed only in the area under the gate electrode where the white ribbon needs to be removed, and then a gate insulating film is formed again. Therefore, as in the case of the conventional method where all the oxide film on the surface was removed to prevent white ribbon,
Since the width of the field insulating film is not reduced but is maintained as it is, the generation of leakage current due to the lateral extension of the diffusion layer is suppressed.

Therefore, the distance between the direct contacts does not need to be designed in accordance with the worst case of misalignment, so the design dimensions can be reduced, and the element can be miniaturized.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIGS. 1(a) and 1(b) are a plan view and an ABC sectional view of a DRAM having a stacked memory cell structure formed by the method of the embodiment of the present invention.

This DRAM includes a memory cell region formed in a p-type silicon substrate 201 and separated by an element isolation insulating film 202, and a gate electrode 204 formed on the substrate surface with a gate insulating film 203 interposed therebetween. A MOSFET including a source and drain region 205 and a capacitor formed by sandwiching a capacitor insulating film 214 between storage node electrodes 21 and 3 and a plate electrode 215 are formed. Here 207°20
8 is a silicide film and a polycrystalline silicon film constituting the bit line, and 209 is an impurity layer formed by ion implantation during direct contact.

The feature of this DRAM is that after the field insulating film is formed, and before the oxide film is formed and removed to prevent white ribbons,
The area other than the gate electrode formation area is coated with resist, only the oxide film in the gate electrode formation area is removed, and the gate oxide film is re-formed, reducing the width of the field insulating film. This is because there is no lateral extension of the direct contact diffusion layer.

This storage node electrode 213 is also connected to the source/drain 205 of the MOSFET via a storage node contact formed in the interlayer insulating film 211, and the gate electrode 204 is connected continuously in one direction of the memory array. are arranged to form word lines. Here, 206t and 206s are insulating films.

Next, a method for manufacturing this DRAM will be explained with reference to the drawings.

FIGS. 2 to 7 are diagrams showing the manufacturing process of this DRAM. In each figure, (b) is an ABC sectional view of (a).

First, as shown in FIG. 2, an element isolation insulating film 202 is formed by selective oxidation on the surface of a p-type silicon substrate 201 with a specific resistance of about 5 Ω·cIl, and then a film thickness of 'U' is formed by thermal oxidation. An onw silicon oxide layer 203S is formed.

Here, the element isolation region 202 is formed on the silicon substrate 202.
For example, a silicon oxide layer and a silicon nitride layer (both not shown) are formed by thermal oxidation to a film thickness of Ions on 1, and this laminated film is buttered leaving the element region, and thermal oxidation is performed using this as a mask. Form from step 1. After this,
The silicon nitride layer and the silicon oxide layer are sequentially removed to form the silicon oxide layer 203S. Note that this laminated film may be replaced with a single layer film made of a silicon nitride film.

Thereafter, as shown in FIG. 3, a resist pattern R having an opening W only in the gate electrode formation region is formed.

Then, as shown in Figure 4, ammonium fluoride (N
The silicon oxide layer 203S on the substrate surface exposed from the resist pattern R is etched away by a wet etching process using H4F'.

Thereafter, as shown in FIG. 5, after removing the resist pattern R, a gate oxide film with a thickness of 20 mm is formed by CVD.
A silicon oxide film 203 of nm thickness is formed.

Subsequently, as shown in FIG. 6, after forming a gate electrode 204 made of a polycrystalline silicon film, As or P ions are ion-implanted using this gate electrode as a mask to form a source/drain made of an n-type diffusion layer 205. A region is formed to form a MOSFET as a switching transistor. The depth of this diffusion layer is, for example, about 150r+s+.

The rest is to form a capacitor using the usual method. First, the earthen wall of the gate electrode 204 is covered with an insulating film 206.
Cover with t. Then, by CVD method, the film thickness was 100 nm.
An interlayer insulating film made of a silicon oxide layer with a thickness of approximately 200 m is deposited on the entire surface, and the entire surface is etched by a reactive ion etching method to form a sidewall insulating film 206S on the side surface of the gate electrode 204.
It is left in a self-consistent manner as follows.

After this, as shown in FIG. 7, an interlayer insulating film 211a is deposited, and a bit line contact BC is first formed to form a bit line consisting of a silicide film 207 and a polycrystalline silicon film 208, and also for direct contact. An impurity layer 209 is formed.

Further, an interlayer insulating film 211b is deposited, and first a storage node contact SC is formed to form a storage node electrode 213, and an impurity layer 209 for direct contact is formed. Then, a capacitor insulating film 214 and a plate electrode are sequentially formed.

In this way, a DRAM with a stacked capacitor structure is completed, but since the width of the field insulating film is maintained at the designed value, even if misalignment of the direct contacts occurs, leakage current will occur between the direct contacts. Since there is no risk of this happening, it is possible to miniaturize the design dimensions.

In the above embodiments, a method for manufacturing a DRAM was explained, but the method is not limited to a DRAM, but can also be applied to semiconductors including a process for forming a MOSFET in which a diffusion layer is formed using a field oxide film for element isolation as one end of a mask. Needless to say, the present invention can be applied to methods for manufacturing other devices as long as they are devices.

〔Effect of the invention〕

As described above, according to the method for manufacturing a semiconductor device of the present invention, an oxide film is formed on the entire surface after the field oxide film is formed, and when this is removed, only the oxide film in the gate electrode formation region is removed. As a result, there is no reduction in field oxide film width that occurs in conventional processes that include white ribbon countermeasures, and there is no risk of leakage due to elongation of the diffusion layer even when direct contact is used. It becomes possible to form a highly reliable semiconductor device.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are a plan view and an A-B-C cross-sectional view of a DRAM with a stacked memory cell structure according to an embodiment of the present invention, and FIGS. 2 to 7 are A diagram showing the manufacturing process of DRAM, FIG. 8 is a diagram showing a conventional DRAM, and FIGS. 9(a) to 9(d) are diagrams showing the DRAM of the conventional example.
It is a figure showing a part of manufacturing process of M. 101... P-type silicon substrate, 102... Element isolation insulating film, 103... Source/drain region, 104
... Gate insulating film, 105 ... Gate electrode, 106
... Insulating film, 107 ... Polycrystalline silicon film, 108
... Silicide film, 109... Bit line, 110.
...Interlayer insulating film, 111...Storage node contact, 112...First capacitor electrode, 113...
- Capacitor insulating film, 114... Second capacitor electrode, 201... P-type silicon substrate, 202... Element isolation insulating film, 203S... Silicon oxide film, 203
...Gate insulating film, 4...Gate electrode, 205...
・N-type diffusion layer, 206... Insulating film, 207... Polycrystalline silicon film, 208... Silicide film (bit line)
, 209...High concentration layer, 211... Interlayer insulating film, 2
13...Storage node electrode, 214...Capacitor insulating film, 215...Plate electrode, BC...Bit line contact, SC...Storage node contact. Figure 9

Claims (2)

[Claims] (1) A method for manufacturing a semiconductor device including a MOSFET in an element isolation region, which includes a field oxide film formation step in which a field oxide film is formed on the substrate surface by selective oxidation, and then an oxidation step in which the substrate surface is oxidized to form an oxide film. a film forming step; an oxide film removing step of selectively removing the oxide film in the gate electrode forming region; a gate insulating film forming step of forming a gate insulating film in the region where the oxide film has been selectively removed; The method includes a gate electrode forming step of forming a gate electrode on a gate insulating film, and a source/drain forming step of forming a source/drain region by self-aligning impurity introduction into the gate electrode and field insulating film. A method for manufacturing a semiconductor device, characterized in that: (2) The method for manufacturing a semiconductor device according to claim 1, wherein the oxide film removing step is an etching step in which regions other than the gate electrode formation region are coated with a resist and etched.