JPH0364073A - Compound semiconductor device and manufacture thereof - Google Patents

Compound semiconductor device and manufacture thereof

Info

Publication number
JPH0364073A
JPH0364073A JP19919989A JP19919989A JPH0364073A JP H0364073 A JPH0364073 A JP H0364073A JP 19919989 A JP19919989 A JP 19919989A JP 19919989 A JP19919989 A JP 19919989A JP H0364073 A JPH0364073 A JP H0364073A
Authority
JP
Japan
Prior art keywords
compound semiconductor
insulating film
semiconductor substrate
substrate
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19919989A
Other languages
Japanese (ja)
Inventor
Osamu Oda
修 小田
Haruto Shimakura
島倉 春人
Takashi Kaisou
甲斐 荘敬司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Eneos Corp
Original Assignee
Nippon Mining Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Mining Co Ltd filed Critical Nippon Mining Co Ltd
Priority to JP19919989A priority Critical patent/JPH0364073A/en
Publication of JPH0364073A publication Critical patent/JPH0364073A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE:To make composition of an insulating film homogeneous and to obtain a MOSFET having excellent characteristics by vacuum-sealing other element of the same group as an element of a compound semiconductor substrate in an ampule, heating it, and forming a mixed crystal layer between the substrate and the insulating film. CONSTITUTION:An Fe-doped semi-insulating InP single crystal is grown by an LEC method, cut in a direction perpendicular to a pulling-up axis, and Si<+> ions are implanted to a cut wafer. An SiNx film is deposited on the surface of an ion implanted substrate by a sputtering method. Thereafter, it is annealed to be activated, the film is removed by etching with a fluoric acid. The thus treated wafer 2 is introduced together with rod phosphorus in a quartz ampule 1, evacuated in vacuum, oxygen gas is then introduced, heat treated to form a uniform insulating oxide film on the wafer. Thus, electrons can be moved in a mixed crystal layer formed between the insulating film and the substrate at a high speed.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は化合物半導体を基体とするMO3型電界効果ト
ランジスタ(以下MOSFETと記す)の製造方法に関
し、特にInP単結晶およびその三元、四元混晶の基板
上にMOSFETを形成する場合に利用して最も効果の
ある技術に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing an MO3 type field effect transistor (hereinafter referred to as MOSFET) based on a compound semiconductor, and in particular to a method for manufacturing an InP single crystal and its ternary and quaternary The present invention relates to the most effective technique when forming a MOSFET on a mixed crystal substrate.

[従来の技術] GaAs、I nPなどの化合物半導体は電子の移動度
がSiよりも高く、また耐放射線性、耐熱性などに優れ
、Siに代わる高周波、高速の電子デバイスとしてその
将来性が見込まれ、数多くの研究がなされてきたが、界
面準位密度の小さな安定な酸化膜が得られないためMO
SFETはまだ実用化されるに至っていない、そこで、
GaAsにおいては、ショットキー電極を用いたMES
FETが実用化され、ディスクリートの高周波FETや
、小規模のディジタルICが実用化されている。しかし
、G a A s M E S F E Tはショット
キー障壁電位が小さいために、論理振幅が大きくとれず
、大規模のディジタルICを高歩留りで製造することが
できないという欠点を有している。
[Conventional technology] Compound semiconductors such as GaAs and InP have higher electron mobility than Si, and also have excellent radiation resistance and heat resistance, and are expected to have future potential as high-frequency, high-speed electronic devices that can replace Si. However, a stable oxide film with a small interface state density could not be obtained, so MO
SFETs have not yet been put into practical use, so
In GaAs, MES using Schottky electrodes
FETs have been put into practical use, as have discrete high-frequency FETs and small-scale digital ICs. However, since the Schottky barrier potential of GaAs MESFET is small, the logic amplitude cannot be large, and it has the disadvantage that large-scale digital ICs cannot be manufactured with high yield. .

一方−GaAsに比べて更に論理振幅が小さいMESF
ETuかできないInPについては、熱酸化法、陽極酸
化法、プラズマ酸化法などによりMOSFETを作る努
力がされてきたが、いずれも酸化膜の組成が不均一とな
り、絶縁性が悪く、良好なMOSFETが実現できず実
用化されるには至っていない、このようなMOSFET
に代わる方法として、S I Oz t S I N 
X p A Q 20 s 。
On the other hand, MESF has a smaller logic amplitude than GaAs.
Efforts have been made to make MOSFETs using InP, which can only be produced by ETu, using thermal oxidation, anodic oxidation, plasma oxidation, etc., but all of these methods result in non-uniform oxide film composition, poor insulation, and the ability to produce good MOSFETs. This type of MOSFET has not yet been realized and put into practical use.
As an alternative to S I Oz t S I N
X p A Q 20 s.

PNのような絶縁膜をCVD法、プラズマCVD法、光
励起CVD法、スパッタ法、蒸着法、スピンオン法など
により低温堆積させるMISFETの研究が数多くなさ
れてきた。
Many studies have been conducted on MISFETs in which insulating films such as PN are deposited at low temperatures by CVD, plasma CVD, photo-excited CVD, sputtering, vapor deposition, spin-on methods, and the like.

[発明が解決しようとする課題] しかしながら、上記方法により製造されたMISFET
はいずれもドレイン電流がドリフトするという電子デバ
イスとしては致命的な欠点を有しており、実用化される
には至っていない。
[Problem to be solved by the invention] However, the MISFET manufactured by the above method
All of these have a fatal drawback as an electronic device in that the drain current drifts, and so they have not been put into practical use.

ところでさきに述べたように、化合物半導体においては
MOSFETが実用化されていないが、その原因は酸化
膜の組成が不均一となることである。例えばInPの場
合、酸素中で熱酸化させると当初はInPO4が20λ
はど成長するが、その後は、InPO,膜の外側にIn
2O,膜が、またInPとTnPO4の界面にはPが析
出することが知られている。このような現象は陽極酸化
や。
By the way, as mentioned earlier, MOSFETs have not been put to practical use in compound semiconductors, and the reason for this is that the composition of the oxide film becomes non-uniform. For example, in the case of InP, when thermally oxidized in oxygen, InPO4 initially becomes 20λ
After that, InPO grows, and InPO grows on the outside of the film.
It is known that P precipitates at the interface between InP and TnPO4. This phenomenon is caused by anodic oxidation.

プラズマ酸化などのいずれの方法であっても起こり、均
一で良質な酸化膜が得られない原因となっている。
This occurs regardless of the method used, such as plasma oxidation, and is the cause of not being able to obtain a uniform, high-quality oxide film.

このように、熱酸化によっては良質な絶縁膜ができにく
いために、先に述べたような種々の低温堆積法が研究さ
れているわけであるが、堆積法では化合物半導体基板の
表面上に別の系の物質を堆積させるために、絶縁膜と化
合物半導体基板の界面で格子不整合が起こる他、表面の
欠陥、汚れなどにより、界面には多くの界面準位が形成
されやすく、これによってドレイン電流がドリフトを起
こすという問題点がある。
As described above, it is difficult to form a high-quality insulating film by thermal oxidation, so various low-temperature deposition methods as mentioned above are being researched. In addition to the lattice mismatch that occurs at the interface between the insulating film and the compound semiconductor substrate due to the deposition of a system of There is a problem that current drift occurs.

そこで、本発明者らは、先に、良質な熱酸化膜ができ、
ドレイン電流のドリフトがないMOSFETの形成法に
ついて開発し提案した(特願平1−61603号、特願
平1−61604号、特願平1−61605号)。
Therefore, the present inventors first created a high-quality thermal oxide film, and
We have developed and proposed a method for forming a MOSFET without drain current drift (Japanese Patent Application Nos. 1-61603, 1-61604, and 1-61605).

しかし、これらのMOSFETでは例えば基板がInP
の場合にあっては、InP中の電子の飽和速度によって
物理的にMOSFETの高速動作性が決まっていた。勿
論、SiのMOSFETよりははるかに高速動作が可能
ではあるものの、AQ G a A s / G a 
A s系のような2次元電子チャネルを用いたHEMT
のような高速動作は望めない。
However, in these MOSFETs, the substrate is, for example, InP.
In this case, the high-speed operability of the MOSFET was physically determined by the saturation speed of electrons in InP. Of course, it is possible to operate much faster than Si MOSFET, but AQ G a A s / G a
HEMT using two-dimensional electron channels such as As system
You cannot expect high-speed operation like that.

ただし、A Q G a A s / G a A s
系のHEMTは、Al2GaAs/GaAs層をG a
 A s基板上に形成させる際に、MBE法やMOCV
D法などの気相エピタキシャル法を用いて形成させねば
ならず、また、基本的にはMESFET構造を用いるた
め、論理ICを作る場合には、論理振幅が大きくとれな
いとともに、高価な設備を用いてエピタキシャル層を成
長するためコスト高になるという欠点を有している。
However, A Q Ga As / Ga As
The HEMT system uses an Al2GaAs/GaAs layer with Ga
When forming on As substrate, MBE method or MOCV method is used.
It must be formed using a vapor phase epitaxial method such as the D method, and since it basically uses a MESFET structure, when making a logic IC, it is difficult to obtain a large logic amplitude and requires expensive equipment. However, since the epitaxial layer is grown over a period of time, the cost is high.

本発明の目的は、化合物半導体のMOSFET構造にお
いて、従来に比べてより高速動作が可能な新しい電子デ
バイスとその製造方法を提供することにある。
An object of the present invention is to provide a new electronic device and a method for manufacturing the same in a compound semiconductor MOSFET structure that can operate at higher speed than conventional electronic devices.

[問題点を解決するための手段] MOSFETにおいては、ゲート電極へ電位をかけるこ
とによって化合物半導体基板とMID膜の界面において
、化合物半導体基板側の界面にキャリアの反転層を形成
し、もって少数キャリヤを界面近傍で移動させることに
よって動作する。従って、MOSFETにあっては、界
面近傍の化合物半導体材料の性質が極めて重要である。
[Means for solving the problem] In a MOSFET, a carrier inversion layer is formed at the interface between the compound semiconductor substrate and the MID film on the compound semiconductor substrate side by applying a potential to the gate electrode, thereby inverting the minority carriers. It operates by moving near the interface. Therefore, in MOSFETs, the properties of the compound semiconductor material near the interface are extremely important.

例えば、絶縁膜を形成させる際、界面近傍の化合物半導
体基板内で蒸気圧の高い構成元素が一部減少し、欠陥な
どが発生すると、MOSFETの特性に著しい影響を与
える。実際、従来考案されてきた様々なMOSFETや
MISFETが実用化できなかった主要因は二のような
欠陥の発生と、それに伴うドレイン電流のドリフトに基
づくものであった。
For example, when forming an insulating film, if some constituent elements with high vapor pressure are reduced in the compound semiconductor substrate near the interface and defects occur, this will significantly affect the characteristics of the MOSFET. In fact, the main reason why the various MOSFETs and MISFETs that have been conventionally devised could not be put into practical use was due to the occurrence of defects as described in 2 and the accompanying drift of drain current.

本発明者らは、この本質的な問題を解決するために、前
述したように石英アンプル中において熱酸化させる際に
、構成元素のうち蒸気圧の高い元素が基板から抜けない
ようにかつ、常に熱平衡状態で絶縁膜を形成するという
非常に重要な技術を既に開発し提案した。
In order to solve this essential problem, the present inventors have attempted to prevent elements with high vapor pressure among the constituent elements from leaving the substrate during thermal oxidation in a quartz ampoule as described above, and to always We have already developed and proposed a very important technology to form an insulating film in a thermal equilibrium state.

本発明は上記先願発明を更に発展させたものである。す
なわち、上述のように絶縁膜を形成する際、化合物半導
体を構成する元素の同族原子が絶縁膜形成時に石英アン
プル中に気相状態で存在するようにして、絶縁膜形成時
に化合物半導体基板側にこれら元素が混入して、化合物
半導体基板と絶縁膜との間(境界)に2次元的に極めて
薄い混晶もしくはそれに類似した層を形成させるように
したものである。
The present invention is a further development of the invention of the prior application. That is, when forming an insulating film as described above, the homologous atoms of the elements constituting the compound semiconductor are present in a vapor phase in the quartz ampoule when forming the insulating film, and are These elements are mixed to form a two-dimensionally extremely thin mixed crystal layer or a layer similar thereto between the compound semiconductor substrate and the insulating film (at the boundary).

絶縁膜の形成の際に同族元素をアンプル中に存在させる
には1次の2通りの方法が考えられる。
Two primary methods can be considered for making the homologous element exist in the ampoule during the formation of the insulating film.

(1)蒸気圧の高い元素 ■−■族化合物半導体にあってはP 、 A s 、 
S bなど、II−Vl族化合物半導体にあってはS、
Se。
(1) In the ■-■ group compound semiconductor of elements with high vapor pressure, P, As,
In II-Vl group compound semiconductors such as Sb, S,
Se.

Cdなどの元素については、第1図(a)のように石英
アンプル1中にアンプルの加熱時に所定圧となる量を決
定しウェーハ2とともに封入しておくか、あるいは第1
図(b)のようにアンプル1に蒸気圧制御部1aを設け
、これを多段炉(ヒータ)3で温度を!I1節して蒸気
圧を制御するか、いずれかの方法あるいは両者を組合せ
た方法を用いることができる。
Regarding elements such as Cd, as shown in FIG.
As shown in Figure (b), the ampoule 1 is equipped with a vapor pressure control section 1a, and the temperature is controlled using a multi-stage furnace (heater) 3. Either method or a combination of both methods can be used.

(2)蒸気圧の低い元素 ■−V族化合物半導体にあってはAα、In。(2) Elements with low vapor pressure ■-Aα, In for group V compound semiconductors.

Gaなどの元素については、石英アンプル中にそのまま
入れただけでは充分な蒸気圧が得られない。
For elements such as Ga, sufficient vapor pressure cannot be obtained just by placing them in a quartz ampoule.

また石英アンプル1にこれら元素の蒸気圧制御部1aを
設けても、基板側にこれら元素が析出してしまい都合が
悪い。これらの蒸気圧の低い元素については、これらの
酸化物を当該元素と混合させ、加熱して低級酸化物を形
成させるようにすればよい0例えばGaの場合にあって
は。
Furthermore, even if the quartz ampoule 1 is provided with a vapor pressure control section 1a for these elements, these elements will precipitate on the substrate side, which is inconvenient. For these elements with low vapor pressure, these oxides may be mixed with the element and heated to form lower oxides.For example, in the case of Ga, it is sufficient to mix these oxides with the element and heat it to form a lower oxide.

3Ga20.+40a450a、O+20゜の反応によ
り、蒸気圧の高いGa、Oを発生させることができるの
で、第1図(Q)のように適当な酸化物と当該元素の混
合体を入れたボート4を石英アンプル1内に入れて気相
中の低級酸化物の圧力を制御する。あるいは第1図(d
)のように、多段炉3の中で酸化物と当該元素の混合体
を入れたボート部4の温度を制御して、低級酸化物の圧
力を調節するようにしてもよい。
3Ga20. By the reaction of +40a450a, O+20°, Ga and O with high vapor pressure can be generated, so as shown in Fig. 1 (Q), a boat 4 containing a mixture of an appropriate oxide and the relevant elements is placed in a quartz ampoule. 1 to control the pressure of the lower oxide in the gas phase. Or Figure 1 (d
), the pressure of the lower oxide may be adjusted by controlling the temperature of the boat section 4 containing the mixture of the oxide and the element in the multistage furnace 3.

なお、化合物半導体基板と絶縁膜との間に形成させる混
晶もしくはそれに類似した層の組成は、アンプルの加熱
温度およびそのプロファイル、成分元素の蒸気圧等を系
毎に最適化することで制御することができる。また、絶
縁膜の中にも、これら混晶層の構成元素が入った絶縁膜
が形成されるので、混晶層組成、#@縁膜組成の適合化
条件は各系毎に実験により求めればよい。
The composition of the mixed crystal or similar layer formed between the compound semiconductor substrate and the insulating film is controlled by optimizing the heating temperature of the ampoule, its profile, the vapor pressure of the component elements, etc. for each system. be able to. In addition, since an insulating film containing the constituent elements of these mixed crystal layers is formed in the insulating film, the conditions for optimizing the mixed crystal layer composition and #@edge film composition can be found through experiments for each system. good.

[作用] 上記した手段によれば、絶縁膜の組成が均一となるとと
もに、構成元素のうち高蒸気圧成分の元素をアンプル中
で蒸発させて圧力をかけた状態で絶縁膜を形成するため
、絶縁膜形成中における化合物半導体基板からの構成元
素の分解、揮発が防止され、特性の優れたMOSFET
が得られるようになる上、絶縁膜と化合物半導体基板と
の間(境界)に、混晶もしくはそれに類似した層が形成
され、この層の中もしくはその界面を電子が高速で移動
するので、従来のMISFETやMOSFETよりもは
るかに高速動作可能な化合物半導体装置を作ることがで
きる。
[Function] According to the above means, the composition of the insulating film becomes uniform, and the insulating film is formed under pressure by evaporating the high vapor pressure component among the constituent elements in the ampoule. A MOSFET with excellent characteristics that prevents decomposition and volatilization of constituent elements from a compound semiconductor substrate during the formation of an insulating film.
In addition, a mixed crystal or a layer similar to it is formed between the insulating film and the compound semiconductor substrate (at the boundary), and electrons move at high speed in this layer or at its interface, making it possible to It is possible to create a compound semiconductor device that can operate much faster than MISFETs and MOSFETs.

[実施例1] 本発明によるMOSFETの特性はコルピノデイクス型
FETで評価した。
[Example 1] The characteristics of the MOSFET according to the present invention were evaluated using a Kolpino-Dix type FET.

直径2インチのFeドープ半絶縁性ZnP単結晶をLE
C法で育成し、引上げ軸と直交する方向に切断し、切り
出されたウェーハを有機洗浄後、ブロームメタノールで
エツチング後、Si+イオンを加速電圧150KeV、
ドーズ量2X10”olとして室温でイオン注入した。
Fe-doped semi-insulating ZnP single crystal with a diameter of 2 inches was LE
The wafer was grown using the C method, cut in the direction perpendicular to the pulling axis, and the cut wafer was organically cleaned and etched with brome methanol.
Ion implantation was performed at room temperature with a dose of 2×10”ol.

イオン注入後の基板は有機洗浄、水洗後、スパッタリン
グ法で表面にSiNx膜を1500人堆積させ、その後
、赤外線加熱炉により620℃で15分間活性化アニー
ルを行った。アニール時にPが抜けることを防止するた
めに、試料の両面を別のInP基板で挾んでアニールし
た。活性化アニール後、SiNx膜をフッ酸でエツチン
グして除去した。ゲート領域の活性層は硫酸系のエッチ
ャントでメサエッチングして除去した。
After the ion implantation, the substrate was washed with organic water and washed with water, and a SiNx film was deposited on the surface by sputtering, followed by activation annealing at 620° C. for 15 minutes in an infrared heating furnace. In order to prevent P from being removed during annealing, both surfaces of the sample were sandwiched between other InP substrates and annealed. After activation annealing, the SiNx film was removed by etching with hydrofluoric acid. The active layer in the gate region was removed by mesa etching using a sulfuric acid-based etchant.

以上のような処理を施したウェーハを、第1図(a)の
ような装置の石英アンプル中に赤リンとともに入れ、真
空にした後、酸素ガスを導入して封入した。この際、金
属ヒ素を同時に石英アンプル中に入れた。その量として
は加熱時の圧力が0゜2〜1.Oat@となるように決
定した0次に、ウェーハを入れた上記石英アンプルを4
50〜600℃で5〜20時間熱処理し、均一なN縁酸
化膜をウェーハ上に形成した。
The wafer treated as described above was placed in a quartz ampoule of an apparatus as shown in FIG. 1(a) together with red phosphorus, and after evacuating the ampoule, oxygen gas was introduced and sealed. At this time, metallic arsenic was simultaneously placed in the quartz ampoule. As for the amount, the pressure during heating is 0°2~1. The quartz ampoule containing the wafer was placed in the 4th order determined to be Oat@.
Heat treatment was performed at 50 to 600° C. for 5 to 20 hours to form a uniform N-edge oxide film on the wafer.

以上のように作った絶縁酸化膜で、イオン注入により活
性化した部分に選択エツチングにより、コンタクトホー
ルを開け、Au−Ge合金を蒸着してパターニングを行
いソース・ドレイン電極形成した。なお、オーミック接
触を得るためのアニールはN2雰囲気中で350℃、7
分間行なった。
In the insulating oxide film produced as described above, contact holes were opened by selective etching in the parts activated by ion implantation, and an Au-Ge alloy was deposited and patterned to form source and drain electrodes. Note that annealing to obtain ohmic contact was performed at 350°C in a N2 atmosphere for 7
I did it for a minute.

最後にAQ層を全面蒸着した後、リン酸系エツチング液
でAQ層をパターニングして、ソース、ドレインおよび
ゲート電極を作った。なお、ゲート電極内径は150μ
m、ゲート電極外径は250μmとした。
Finally, after the AQ layer was deposited on the entire surface, the AQ layer was patterned using a phosphoric acid etching solution to form source, drain, and gate electrodes. The inner diameter of the gate electrode is 150μ.
m, and the outer diameter of the gate electrode was 250 μm.

以上のようにして作ったFETの実効電子移動度μof
fは、チャネルコンダクタンス(gd)かここで、Ci
はゲート容量、Vgはゲート印加電圧、VthはFET
のしきい値電圧である。ゲート容量値Ciは、n型In
P基板を用いて同様の酸化膜形成プロセスを用いて作っ
たMISダイオードの測定値から求めた。
The effective electron mobility μof of the FET made as above
f is the channel conductance (gd), where Ci
is gate capacitance, Vg is gate applied voltage, Vth is FET
is the threshold voltage of The gate capacitance value Ci is n-type In
It was determined from the measured values of an MIS diode made using a P substrate using a similar oxide film formation process.

第2図に上記移動度μssfの測定結果を示す。FIG. 2 shows the measurement results of the mobility μssf.

同図において実MAは石英アンプル中にAsを入れた場
合を、また実線BはAsを入れなかった場合を示す。こ
れより、Asを入れた場合には入れない場合よりも移動
度が著しく高くなることが判る。
In the figure, the actual MA indicates the case where As was put into the quartz ampoule, and the solid line B shows the case where As was not put in the quartz ampoule. From this, it can be seen that when As is added, the mobility is significantly higher than when it is not added.

[実施例2] 実施例1と同じ手順でコルピノディスク型FETを形成
した。基板としては実施例1と同i、rreドープ半絶
縁性InP単結晶を用いた。絶縁酸化膜を形成させる際
に、第1図(d)のような装置の石英アンプル1中に0
2ガスと赤リンを入れ、また石英アンプル1の蒸気圧制
御部1aに石英ボート4を置き、この中にGaとGa、
03の混合物を入れた。
[Example 2] A Kolpino disk type FET was formed using the same procedure as in Example 1. As the substrate, the same i, rre doped semi-insulating InP single crystal as in Example 1 was used. When forming an insulating oxide film, zero
2 gas and red phosphorus, and place a quartz boat 4 in the vapor pressure control part 1a of the quartz ampoule 1, and put Ga, Ga,
03 mixture was added.

基板部分の温度は450〜600℃とし、GaおよびG
a、03のボート部分の温度は600〜1000℃とし
て、5〜20時間熱処理し、均一な絶縁酸化膜を形成さ
せた。
The temperature of the substrate part is 450 to 600°C, and the temperature of Ga and G
The temperature of the boat portion of a, 03 was set at 600 to 1000° C., and heat treatment was performed for 5 to 20 hours to form a uniform insulating oxide film.

上記の酸化プロセス以外は実施例1と同様にして作った
コルピノディスクFETの実効電子移動度μoffを測
定した。その測定結果は第3図のとおりで、実線CはG
a、O,を入れた場合、実線りは入れない場合を示す。
The effective electron mobility μoff of a Kolpino disk FET manufactured in the same manner as in Example 1 except for the above oxidation process was measured. The measurement results are shown in Figure 3, where the solid line C is G
When a, O, is included, the solid line indicates the case where it is not included.

GaとGa2O,を入れた場合、GaとGa、O,を入
れない場合に比べて、実効電子移動度の大きなFETが
できた。
When Ga and Ga2O were added, an FET with a higher effective electron mobility was created than when Ga, Ga, and O were not added.

なお、上記実施例ではInP単結晶基板上にMOSFE
Tを形成した場合についても説明したが、InおよびP
を含む三元、四元混晶基板上にMOSFETを形成する
場合はもちろんGaAs等他の化合物半導体基板上にM
OSFETを形成する場合に適用することができ、同様
の効果が得られる。
Note that in the above example, a MOSFE is mounted on an InP single crystal substrate.
The case where T was also formed was also explained, but In and P
When forming a MOSFET on a ternary or quaternary mixed crystal substrate containing
It can be applied when forming an OSFET, and similar effects can be obtained.

[発明の効果] 以上説明したごとくこの発明は、化合物半導体基板を石
英アンプル内に入れ、同時に当該化合物半導体基板の構
成元素のうち蒸気圧の高い元素を酸素ガスと共に真空封
入して加熱し、あるいはこの際、当該化合物半導体基板
の構成元素のうち蒸気圧の低い元素の酸化物をその元素
と混合させてアンプル中に同時に真空封入しアンプルを
加熱して蒸気圧の高い低級酸化物を形成させて絶縁膜の
組成を制御して絶縁膜を形成する際に、上記基板の構成
元素のうち少なくとも一つの元素と同族の他の元素1種
または2種以上をアンプル中に同時に真空封入して加熱
し、化合物半導体基板と絶縁膜の間に混晶もしくはそれ
に類似した組成の層を形成させるようにしたので、絶縁
膜の組成が均一となるとともに、構成元素のうち高蒸気
圧成分の元素をアンプル中で蒸発させて圧力をかけた状
態で絶縁膜を形成するため、絶縁膜形成中における化合
物半導体基板からの構成元素の分解、揮発が防止され、
特性の優れたMOSFETが得られるようになる上、絶
縁膜と化合物半導体基板との間(境界)に新たに形成さ
れた層もしくは界面を電子が高速で移動するため、従来
のMISFETやMOSFETよりも高速動作可能な化
合物半導体装置を得ることができるという効果がある。
[Effects of the Invention] As explained above, the present invention places a compound semiconductor substrate in a quartz ampoule, and simultaneously vacuum-seals an element with a high vapor pressure among the constituent elements of the compound semiconductor substrate together with oxygen gas and heats it. At this time, among the constituent elements of the compound semiconductor substrate, an oxide of an element with a low vapor pressure is mixed with that element and simultaneously vacuum-sealed into an ampoule, and the ampoule is heated to form a lower oxide with a high vapor pressure. When forming an insulating film by controlling the composition of the insulating film, at least one of the constituent elements of the substrate and one or more other elements in the same group are simultaneously vacuum sealed in an ampoule and heated. By forming a layer with a mixed crystal or a similar composition between the compound semiconductor substrate and the insulating film, the composition of the insulating film becomes uniform, and elements with high vapor pressure among the constituent elements are contained in the ampoule. Since the insulating film is formed under pressure by evaporation, decomposition and volatilization of the constituent elements from the compound semiconductor substrate during the insulating film formation are prevented.
In addition to being able to obtain MOSFETs with excellent characteristics, electrons move at high speed through the newly formed layer or interface between the insulating film and the compound semiconductor substrate (boundary), making it more efficient than conventional MISFETs and MOSFETs. This has the effect that a compound semiconductor device capable of high-speed operation can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(d)は本発明方法に使用される絶縁膜
形成装置の構成例を示す断面図、第2図は第1の実施例
により形成されたFETについて測定した実効電子移動
度と結晶中のFe濃度との関係を示すグラフ、 第3図は第2の実施例により形成されたFETについて
測定した実効電子移動度と結晶中のFc濃度との関係を
示すグラフである。 1・・・・石英アンプル、2・・・・ウェーハ、3・・
・・ヒータ、4・・・・ボート。 ( 第  1rlA 第2図 Fc濃、1 (cm−3)
FIGS. 1(a) to (d) are cross-sectional views showing a configuration example of an insulating film forming apparatus used in the method of the present invention, and FIG. 2 is an effective electron transfer measured for an FET formed according to the first embodiment. FIG. 3 is a graph showing the relationship between the effective electron mobility measured for the FET formed according to the second example and the Fc concentration in the crystal. 1...Quartz ampoule, 2...Wafer, 3...
...Heater, 4...Boat. (1st rlA 2nd figure Fc density, 1 (cm-3)

Claims (2)

【特許請求の範囲】[Claims] (1)化合物半導体基板上に絶縁膜を介して電極金属層
が形成されてなる化合物半導体装置であって、上記化合
物半導体基板と絶縁膜との間に半導体基板の構成元素と
それの同族元素とからなる混晶に類似した組成の層を有
することを特徴とする化合物半導体装置。
(1) A compound semiconductor device in which an electrode metal layer is formed on a compound semiconductor substrate with an insulating film interposed therebetween, in which constituent elements of the semiconductor substrate and their homologous elements are disposed between the compound semiconductor substrate and the insulating film. A compound semiconductor device characterized by having a layer having a composition similar to a mixed crystal consisting of.
(2)化合物半導体基板を石英アンプル内に入れ、同時
に当該化合物半導体基板の構成元素のうち蒸気圧の高い
元素を酸素ガスと共に真空封入して加熱し、あるいはこ
の際、当該化合物半導体基板の構成元素のうち蒸気圧の
低い元素の酸化物をその元素と混合させてアンプル中に
同時に真空封入しアンプルを加熱して蒸気圧の高い低級
酸化物を形成させて絶縁膜の組成を制御して絶縁膜を形
成する際に、上記基板の構成元素のうち少なくとも一つ
の元素と同族の他の元素1種または2種以上をアンプル
中に同時に真空封入して加熱し、化合物半導体基板と絶
縁膜の間に混晶もしくはそれに類似した組成の層を形成
させることを特徴とする化合物半導体装置の製造方法。
(2) A compound semiconductor substrate is placed in a quartz ampoule, and at the same time, an element with a high vapor pressure among the constituent elements of the compound semiconductor substrate is sealed in vacuum with oxygen gas and heated, or at this time, the constituent elements of the compound semiconductor substrate are The composition of the insulating film is controlled by mixing an oxide of an element with a low vapor pressure with the other element, vacuum-sealing the mixture into an ampoule, and heating the ampoule to form a lower oxide with a high vapor pressure. When forming the compound semiconductor substrate, one or more other elements in the same group as at least one of the constituent elements of the substrate are vacuum-sealed and heated at the same time in an ampoule to create a bond between the compound semiconductor substrate and the insulating film. A method for manufacturing a compound semiconductor device, comprising forming a layer having a composition of mixed crystal or similar thereto.
JP19919989A 1989-08-02 1989-08-02 Compound semiconductor device and manufacture thereof Pending JPH0364073A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19919989A JPH0364073A (en) 1989-08-02 1989-08-02 Compound semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19919989A JPH0364073A (en) 1989-08-02 1989-08-02 Compound semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH0364073A true JPH0364073A (en) 1991-03-19

Family

ID=16403790

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19919989A Pending JPH0364073A (en) 1989-08-02 1989-08-02 Compound semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH0364073A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5214003A (en) * 1989-05-31 1993-05-25 Nippon Mining Co., Ltd. Process for producing a uniform oxide layer on a compound semiconductor substrate
US7200353B2 (en) 2003-09-01 2007-04-03 Seiko Epson Corporation Image forming apparatus with intermediate transfer member

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5214003A (en) * 1989-05-31 1993-05-25 Nippon Mining Co., Ltd. Process for producing a uniform oxide layer on a compound semiconductor substrate
US7200353B2 (en) 2003-09-01 2007-04-03 Seiko Epson Corporation Image forming apparatus with intermediate transfer member

Similar Documents

Publication Publication Date Title
US5170231A (en) Silicon carbide field-effect transistor with improved breakdown voltage and low leakage current
EP0064829B1 (en) High electron mobility semiconductor device and process for producing the same
Zeng et al. Vertical Ga 2 O 3 MOSFET with magnesium diffused current blocking layer
CN105140283A (en) Silicon carbide MOSEFTs (metal-oxide-semiconductor field-effect transistors) power device and manufacturing method therefor
JP2003243653A (en) Method for manufacturing silicon carbide semiconductor device
JP2612040B2 (en) MOS-FET using β-SiC and manufacturing method thereof
JPH0260063B2 (en)
JPH03774B2 (en)
JPH0364073A (en) Compound semiconductor device and manufacture thereof
US5214003A (en) Process for producing a uniform oxide layer on a compound semiconductor substrate
JPH0770695B2 (en) Method for manufacturing silicon carbide semiconductor device
Scofield et al. Deep level investigation of bulk and epitaxial 6H-SiC at high temperatures
JPS6292327A (en) Semiconductor device and manufacture thereof
JP2660252B2 (en) Method for manufacturing compound semiconductor device
JPS596054B2 (en) Method for manufacturing semiconductor devices
JPS62143461A (en) N-type gaas ohmic electrodes
JPS61185923A (en) Formation of semiconductor low resistance layer
JPH034532A (en) Manufacture of compound semiconductor device
JPS60251631A (en) Manufacture of semiconductor device having non-uniform distribution of impurity concentration
JPH02239666A (en) Manufacture of compound semiconductor device
JPH0349242A (en) Field effect transistor and its manufacture
JPS59165460A (en) Semiconductor device and manufacture thereof
JPH02239668A (en) Compound semiconductor device and manufacture thereof
JPS6191966A (en) Field effect transistor utilizing specified electrode material for semiconductor device
JPS62115831A (en) Manufacture of semiconductor device