JPH0363996A - Programmable associative memory by thin film transistor - Google Patents

Abstract

PURPOSE:To easily execute integration and to increase the number of neutrons by forming a thin film transistor for drive and a thin film transistor for memory on the same insulated substrate for the respective coupling elements of a synapse coupling part. CONSTITUTION:For the respective coupling elements of the synapse coupling part 1, the thin film transistor for drive and the thin film transistor for memory are formed on the same insulated substrate. Namely, to a line where (i)th data INi of the synapse coupling part 1 are inputted, outputs Oj, Oj+1... of the neurons in all the lines are fed back and inputted through coupling elements K1-K5 as exciting or suppressing data. Further, the coupling element K1, to which the (i)th data INi are inputted, is composed of the thin film transistor ST1 for drive and the thin film transistor MT1 for memory. For the thin film transistor ST1 for drive, a Vdd voltage is supplied to a drain electrode and the input data INi are inputted to a gate electrode. Thus, the integration is made easy and the number of the neurons can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a programmable content addressable memory using thin film transistors.

(2) Excitatory coupling elements and inhibitory coupling elements [
Conventional technology] A synaptic connection section that stores input data In recent years, next-generation computers have developed a system for storing data read from the synaptic connections of human nerves.
Neurocomputers with highly parallel distributed processing based on circuits are being researched.

In the above neurocomputer, a programmable associative memory is used, but in the past, St (silicon)
The programmable content addressable memory is constructed using an EEPROM formed on a wafer.

[Problem to be solved by the invention] However, the EE formed on a Si wafer as in the above conventional
When a programmable associative memory is configured using PROM, there is a problem of a decrease in yield when increasing the capacity and multilayer wiring, and it is difficult to increase the number of neurons. Furthermore, if an attempt is made to increase the number of neurons, a wafer-sized LSI will inevitably be required, resulting in a problem of increased cost.

Furthermore, conventionally, when setting the coupling strength, an external computer calculates the coupling strength and writes it into a memory element, which makes setting the coupling strength extremely troublesome.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a programmable associative memory using thin film transistors that can easily increase the number of neurons and automatically set the coupling strength according to the data to be stored. purpose.

[Means and effects for solving the problem] The present invention comprises an excitatory coupling element and an inhibitory coupling element, and sets a synaptic coupling part that stores input data and a signal level of data read from this synaptic coupling part. In a programmable associative memory equipped with a neuron section that amplifies and outputs the amplified signal up to a certain level, each coupling element of the synaptic coupling section is configured such that a driving thin film transistor and a memory thin film transistor are formed on the same insulating substrate.

As described above, by forming each coupling element of the synaptic coupling portion with a driving thin film transistor and a memory thin film transistor, integration becomes easy and the number of neurons can be increased.

Further, the present invention provides a programmable associative memory,
The present invention is characterized by comprising a coupling strength setting means for writing the coupling strength of the synaptic coupling portion as the channel resistance value of the memory thin film transistor in each coupling element in accordance with the data to be stored.

By providing the coupling strength setting means as described above, it is not necessary to have an external computer calculate the coupling strength, and the system can be easily assembled.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 shows a schematic configuration of the entire memory chip, with FIG. 1(a) showing the configuration in storage mode and FIG. 1(b) showing the configuration in associative mode.

The programmable content addressable memory according to the present invention is shown in FIG.
), it is composed of a synapse coupling section 1, a neuron section 2, an arithmetic section 3, and a memory write/erase circuit 4. In the storage mode, the input cover turn INi
is input to the arithmetic unit 3, where the coupling strength Eij is determined by calculating the number of Wij-Σ(2lNi-1)(21Nj-1) patterns and sent to the memory write/erase circuit 4. This memory write/erase circuit 4 writes or erases data to or from the synapse coupling section 1 according to the calculation result of the calculation section 3. In this case, memory write/
The erase circuit 4 repeatedly performs the data write operation for the number of turns.

In the associative mode shown in FIG. 1(b), a circuit is constituted by a synaptic coupling section 1 and a neuron section 2, and when input data INi is given to the synaptic coupling section 1, neuron outputs of all lines of the neuron section 2 ΣOjJ is fed back to the synaptic coupling unit 1. The synaptic coupling unit 1 performs arithmetic processing of INi+ΣWi j xoj (i+j) using the input data INi and the feedback data, and outputs it to the neuron unit 2.

This neuron section 2 identifies the level of the signal given from the synaptic coupling section 1 and outputs data Oi.

Next, details of the synapse coupling section 1 and neuron section 2 will be explained.

Figure 2 shows the three-person power from INI to INS, and from 0UTI to 0.
It shows the configuration of the synaptic coupling section 1 and the neuron section 2 in the case of three outputs of the UT3. Human power data I
NI to INS are input to neurons 2a to 2C in the neuron unit 2 via a matrix-like synapse coupling unit 1 consisting of a plurality of coupling elements K. The data taken out from these neurons 2a to 2C are 0UTl to 0
In addition to being output as UT3, the synaptic connection unit 1
is fed back to neurons 2a to 2C via . In this case, the feedback signals of the neurons 2a to 2c are mutually input to the other neurons 2a to 2C.

That is, the feedback signal of the neuron 2a is inputted to the neurons 2b and 2c, the feedback signal of the neuron 2b is inputted to the neurons 2a and 2c, and the feedback signal of the neuron 2c is inputted to the neurons 2a and 2b, respectively, via the synaptic connection unit 1.

In this synaptic connection portion 1, the coupling elements K shown by white circles are inhibitory connections, and the coupling elements K shown by diagonal lines inside the white circles are excitatory connections. Further, the synaptic coupling section has a function of variably setting each coupling strength with respect to human input data, the details of which will be described later.

Therefore, each neuron 2a to 2 of the neuron section 2
C is a two-stage inverter 11.12 as shown in FIG.
It has a configuration in which they are connected in series.

The inverters 11.12 are, for example, NMOS enhancement type thin film transistors Tl, T2 or T3.
T4 are connected in series, and the thin film transistors Tl and T
Power supply voltage Vdd is applied to the drain electrode of thin film transistor T2. The source electrode of T4 is grounded. Then, a signal from the synaptic coupling matrix section 1 is manually applied to the gate electrode of the thin film transistor T3. An output signal OUT is taken out from the source/drain connection point of T4. The neurons 2a to 2C configured as described above achieve the input/output relationship shown in FIG. 4. For example, with Vdd/2 as the threshold level, when the input signal is larger than this, the signal is high level, and when it is smaller, the signal is low level. Achieve a person-output relationship such as output. In addition,
In an actual circuit, the high level and low level are determined by the delicate amplitude of the input data Vin, so a sense amplifier or the like constituted by, for example, a flip-flop is used.

FIG. 5(a) shows a part of the synaptic connection l, in which the outputs Oj of neurons of all lines are input to the line where the i-th data INi is input.

OJ+++ . . . is fed back to the coupling element Kl- via 5 as excitatory or inhibitory data. These coupling elements 1 to 5 are constructed as shown in FIG. 5(b).

That is, the coupling element 1 to which the i-th data INi is inputted is composed of a driving thin film transistor STI and a memory thin film transistor MTI. Data INi is manually generated. The source electrode of the drive thin film transistor ST1 is connected to the data line Li via the drain and source of the memory transistor MT1, and coupling elements 2 to 5 are connected to the data line Li.

2 to the coupling element. 4 performs excitatory coupling, and similarly to 1, drive thin film transistors S are used as coupling elements.
T2. ST4 and memory thin film transistors MT2, M
T4 are connected in series, and drive thin film transistors ST2. In ST4, Vdd voltage is supplied to the drain electrode, and neuron outputs Oj, OJ+1 are supplied to the gate electrode.
is input.

The source electrode of the drive thin film transistor ST2°Sr1 is connected to the memory transistors MT2 and MT4.
The data line L is connected between the drain and source of
connected to i. On the other hand, 3. and 5 perform suppressive coupling, and drive thin film transistors ST3 . ST5 and memory thin film transistor MT3,
MT5 are connected in series, and drive thin film transistors ST3. The drain electrode of ST5 is grounded, and
Neuron outputs Oj, OJ +1 are manually applied to the gate electrodes. Then, the driving thin film transistor ST3
．． The source electrode of Sr1 is connected to the memory transistor MT3.
, MT5 are connected to the data line Li via their respective drains and sources.

In the synapse coupling unit 1 configured as described above, data is written to the memory thin film transistors MTI-MT5 in the storage mode, and if the i-th data and the j-th data are equal, the synapse coupling unit 1 writes the data to the excitatory coupling element 2 for the memory thin film transistor MTI-MT5. The thin film transistor MT2 is shifted to have a low channel resistance, and the memory thin film transistor MT4 of 3 in the inhibitory coupling element is shifted to have a high channel resistance. In addition, the memory thin film transistor MT
As a characteristic required for channel resistance by 2 to MT5, the product of the strength and number of excitatory connections and the strength and number of inhibitory connections must correspond as a channel resistance ratio. For example, if the strength of the i-th connection is Wi, and if this Wi is positive, it is excitatory, and if it is negative, it is inhibitory, then the strength of the connection is rl, 2.3. Since the neuron takes an integer value such as "...", it is necessary to control the channel resistance so that the neuron outputs "1", and if it is negative, the neuron outputs "0". This relationship is shown in FIG. Ideally, as shown in Figure 7, the supply voltage Vdd is divided by the ratio of the resistance value Ra due to the sum of excitatory connections and the resistance value Rb due to inhibitory connections, so if the input line is higher than Vdd/2, there is no excitement. The sexual connection becomes stronger, and the output of the neuron 21 becomes "1".

In addition, when it is difficult to increase the coupling strength of the memory thin film transistor MT by 1 or 2 times the channel resistance ratio,
As shown in FIG. 8, a plurality of memory thin film transistors MT a l , MT a2 --- MT an
and M T b 1 , M T b 2, −M T
It is also possible to connect b n in parallel and use them sequentially for each data to be stored. However, in this case, the number of data to be stored is limited to n pieces, the number of transistors used increases, and it is necessary to address the memory thin film transistor MT used.

FIG. 9 shows a circuit configuration for writing the strength of each coupling as a channel resistance value of a memory thin film transistor. The circuit shown in FIG. 9 is the same as the circuit shown in FIG. It is set up. The write circuit 21 includes an exclusive OR circuit (hereinafter abbreviated as EX OR circuit) 211 and an inverter 2
12 and a thin film transistor 213.

The EX OR circuit 211 has input data INi, IN
j is input, and its output signal is input to the gate electrode of the thin film transistor 213 via the inverter 212.

The operating voltage Vp is supplied to the drain electrode of the thin film transistor 213, and a signal outputted from the source electrode is inputted to the gate electrode of the memory thin film transistor 5MTa. As the operating voltage Vp, a large negative value is usually used in order to lower the channel resistance of the memory thin film transistor 5MTa.

On the other hand, the write circuit 22 includes an EX-OR circuit 221 and a thin film transistor 222. The EX-OR circuit 221 receives human input data INi and INj, and its output signal is input to the gate electrode of the thin film transistor 222.

In this thin film transistor 222, the operating voltage Vp is supplied to the drain electrode, and a signal outputted from the source electrode is inputted to the gate electrode of the memory thin film transistor 2MTb.

In the above configuration, if the coupling strength is at a high level or both at a low level between the i-th human power and the j-th output for one stored data, the thin film transistor 213 is turned on and the excitable memory is activated. thin film transistor 5M
The coupling strength of Ta is increased by 1, otherwise the thin film transistor 222 is turned on and the suppressive memory thin film transistor 7 is turned on.
This is achieved by increasing the bonding strength of MTb by one.

Note that in the memory mode, the memory thin film transistor MTa,
When writing data to MTb, driving thin film transistors STa and STb are turned on. In this case, the normal Vdd line may also be switched to the ground potential. In the associative mode, the Vp power supply for the thin film transistors 213 and 222 is separated, and the memory thin film transistors MTa,
Prevent the data stored in MTb from changing.

FIG. 10 shows a detailed configuration of the EX-OR circuits 211 and 221, and shows an example configured using NMO8 type thin film transistors. As shown in the figure, input data INi is input from a terminal 31 through inverters 32 and 33 to the gate electrode of a thin film transistor T34, and input data INj is input from a terminal 41 through inverters 42 and 43 to the gate electrode of a thin film transistor T44. be done. Further, the output signal of the inverter 32 is inputted to the drain electrode of the thin film transistor 44, and the output signal of the inverter 42 is inputted to the drain electrode of the thin film transistor 34.

The source electrodes of the thin film transistors 34, 44 are connected together, and a series circuit of thin film transistors 35, 36 and a thin film transistor 45, 4 are connected between this connection point and the ground.
Six series circuits are connected in parallel. The output signal of the inverter 32 is input to the gate electrode of the thin film transistor 35, and the output signal of the inverter 42 is input to the gate electrode of the thin film transistor 36. In addition, input data INj is connected to the gate electrode of the thin film transistor 45 at the terminal 41.
Input data INi is input from the terminal 31 to the gate electrode of the thin film transistor 46 . and,
A signal generated at the common connection point of the source electrodes of the thin film transistors 34, 35, 44, 45 is taken out from the output terminal 47 as an output signal.

In the above configuration, when the human input data INi and INj match, the series circuit of thin film transistors 35 and 36 or the series circuit of thin film transistors 45 and 46 is turned on, and the output terminal 47 goes to the ground level (“0”). Become. Further, if the input data INi and INj do not match, the series circuit of thin film transistors 35 and 36 and the series circuit of thin film transistors 45 and 46 are turned off, and one of the thin film transistors 34 and 44 is turned on, and the output A high level (“1”) signal is output from the terminal 47.

FIG. 11 shows the detailed structure of the memory thin film transistor MT and the driving thin film transistor ST used in each of the above circuits. In the figure, reference numeral 51 denotes an insulating substrate made of glass or the like, and on this insulating substrate 51, the memory thin film transistor MT and the driving thin film transistor ST are respectively formed in an inverted staggered shape. That is, the gate electrodes Gl and G2 of the memory and driving thin film transistors MT and ST are formed on an insulating substrate 51, and the gate insulating film 52 is formed over the entire surface of the substrate. to each gate pole G
Semiconductor layers 53 and 53 made of i-type a-3i (amorphous silicon) are formed opposite to the semiconductor layers 53 and 53, respectively, and n''-a-8t are formed on the semiconductor layers 53 and 53, respectively.
Source/drain electrodes S1°D (and S2.D2 are formed through contact layers 54, 54, and the drain electrode D1 of the memory thin film transistor MT is connected to the source electrode S2 of the drive thin film transistor ST and the connection wiring 55).
Furthermore, the memory thin film transistor MT and the driving thin film transistor ST are covered with a protective film 56 made of a SiN film without hysteresis.

Further, the gate insulating film 52 is a gate insulating film of a memory thin film transistor MT and a driving thin film transistor ST.
It is a common insulating film that also serves as the insulating film of
), and the region of this SiN film except for the memory thin film transistor MT part is made of Si/H by oxidation or nitridation. The value of is expressed as the stoichiometric ratio (St/N-
The non-hysteresis column portion 52a is made small to approximately the same value as 0.75) and eliminates hysteresis.

In the above structure, the gate insulating film 52 is made of a SiN film, but by changing the composition ratio of silicon atoms Si to nitrogen atoms N (Si/N), the characteristics of the memory thin film transistor MT or the driving thin film transistor ST can be changed. You can have it.

That is, when configuring the memory thin film transistor MT, the composition ratio (S
By setting i/N) to a value larger than the stoichiometric ratio (0,75), the gate voltage VG-drain current (current flowing between the source and drain) ID characteristics are shown in Figure 12 (a). It has hysteresis characteristics and can have a memory function.

In addition, when configuring the drive thin film transistor ST, the composition ratio (Si/N) of the gate insulating film 52 is changed by chemically FtL.
By setting a small value to almost the same value as the theoretical ratio (0,75), V as shown in FIG. 12(b). -The ID characteristic has no hysteresis, and can be operated as a normal transistor.

By changing the composition ratio (Si/N) of the gate insulating film 52 as described above, the transistor characteristics can be set arbitrarily, so the memory thin film transistor MT and the driving thin film transistor ST are formed on the same insulating substrate. can do.

In the above embodiment, the output of the neuron section 2 is fed back to the synaptic connection section 1 in the associative mode, but the same method can be applied even when no feedback is included, as shown in FIG. 13(a). It can be implemented by In the case where this feedback is not included, the synapse coupling unit 1 performs I
It performs arithmetic processing of Ni+Σ Wi j ·INj (i≠j) and outputs it to the neuron unit 2.

FIG. 13(b) shows the configuration of the synaptic coupling section 1 and the neuron section 2 when the above-mentioned feedback is not included. By configuring the synapse connection unit 1 in this way, the above-mentioned arithmetic processing is performed, and the human data IN1
-IN3, output data 0UTI-0UT3 are taken out from neurons 2a-2c.

[Effects of the Invention] As detailed above, according to the present invention, there is a synaptic connection section which is composed of an excitatory coupling element and an inhibitory coupling element and stores input data, and a signal level of data read from this synaptic coupling section. In a programmable associative memory equipped with a neuron section that amplifies and outputs to a set level,
Since each of the coupling elements of the synaptic coupling portion, the driving thin film transistor and the memory thin film transistor are formed on the same insulating substrate, integration becomes easy and the number of neurons can be increased.

Furthermore, in the present invention, the coupling strength of the synaptic coupling portion is written as the channel resistance value of the memory thin film transistor in each coupling element according to the data to be stored, so there is no need to have an external computer calculate the coupling strength. You can easily set up the system.

[Brief explanation of drawings]

1 to 13 show embodiments of the present invention,
FIG. 1(a) is a block diagram showing a schematic configuration of the entire memory chip, FIG. 1(b) is a block diagram showing a schematic configuration in associative mode, and FIG. 2 is a synaptic connection section in FIG. 1(a). FIG. 3 is a circuit diagram showing details of each neuron in the neuron section of FIG. 2, FIG. 4 is an input/output characteristic diagram of the neuron, and FIG.
a) is a diagram showing a part of the synaptic connection part in FIG. 2;
FIG. 5(b) is a circuit diagram showing the details of FIG. 5(a), FIG. 6 is a diagram showing the relationship between the channel resistance of a memory thin film transistor and the strength of coupling, and FIG. 7 is the same as FIG. 5(b). Figure 8 is a diagram showing another example of the structure of the memory section of the synaptic junction, and Figure 9 is a diagram for explaining the operation of the synaptic junction shown in Figure 9. Circuit diagram, Fig. 10 is a circuit configuration diagram showing details of the exclusive OR circuit (EX OR circuit) in Fig. 9, Fig. 11
The figure is a cross-sectional view showing the structure of a thin film transistor, and Figure 12 (
a) is the V of the memory thin film transistor. −■. Characteristic diagram,
Figure 12(b) shows V6-ID of the drive thin film transistor.
Characteristic diagram, Fig. 13 (a) is a block diagram showing a schematic configuration in associative mode without feedback, Fig. 13
Figure (b) is a configuration diagram showing details of figure (a). 1... Synaptic connection part, 2... Neuron part, 3.
...Arithmetic unit, 4...Memory write/erase circuit, ]1.
...Inverter, 21.22...Writing circuit, 211
゜221... EX OR circuit, 213, 222... Thin film transistor, 31.41... Terminal, 32.33° 42.43... Inverter, 34~36.44~46
. . . thin film transistor, 51 . . . insulating substrate, 52 gate insulating film, 53 . . . semiconductor layer.

Claims (2)

[Claims] (1) In a programmable content addressable memory comprising a synaptic connection section that stores input data and a neuron section that amplifies the signal level of data read from the synaptic connection section to a set level and outputs the amplified signal level, each connection of the synaptic connection section is provided. A programmable content addressable memory using thin film transistors, characterized in that the element is formed by forming a driving thin film transistor and a memory thin film transistor on the same insulating substrate. (2) It consists of an excitatory coupling element and an inhibitory coupling element, and includes a synaptic coupling section that stores input data, and a neuron section that amplifies the signal level of the data read from the synaptic coupling section to a set level and outputs it. In the programmable content addressable memory, each coupling element of the synaptic coupling part is constituted by a drive thin film transistor and a memory thin film transistor, and an excitatory coupling element or an inhibitory coupling element according to data for storing the coupling strength of the synaptic coupling part. 1. A programmable content addressable memory using thin film transistors, characterized in that the programmable content addressable memory using thin film transistors is provided with coupling strength setting means for writing as a channel resistance value of a memory thin film transistor constituting the memory transistor.