JPH0363769A - Circuit simulator - Google Patents

Abstract

PURPOSE:To perform simulation in accordance with a condition by preliminarily storing data of various test patterns and generating and outputting a test pattern signal by data meeting the request of a circuit to be tested to output a flexible test pattern in accordance with the condition of the circuit to be tested. CONSTITUTION:A circuit 11 to be tested of simulation outputs a request signal to request a test pattern according with the change of the condition. A pattern generator 12 registers data of timing, intervals, or the like in an incorporated memory 12a and successively reads and outputs a normal test pattern and the test pattern, which the circuit 11 to be tested requested in accordance with the condition, from the memory 12a. Since the pattern generator 12 outputs the test pattern meeting the request when the circuit 1 to be tested requests the test pattern according with the change of the condition, the circuit to be tested 11 is simulated in accordance with the condition.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to circuit simulation for simulating a circuit under test in which test patterns change flexibly over time and a dedicated pattern generator must be used in actual hardware testing. It is related to the device.

Prior Art FIG. 3 is a block diagram showing the configuration of a conventional circuit simulation device.

In FIG. 3, reference numeral 1 indicates a circuit under test that performs simulation, and reference numeral 2 indicates a pattern generator that outputs a fixed test pattern.

FIG. 4 is an explanatory diagram showing a test pattern output by a conventional pattern generator.

In FIG. 4, P is a test pattern composed of various data, P , P , P .

1 1 21 31P,
... is a pattern that constitutes the test pattern P, T , T , T , T , ...
Ha Pata+! 21 31
41-n P, P, P, P,
... data length + 21 3
1 41 is shown.

Next, the operation of the conventional example will be explained.

In FIG. 3, when the pattern generator 2 sends the test pattern P shown in FIG. 4 to the circuit under test 1, the circuit under test 1 receives the test pattern P
Each pattern P , P that constitutes.

1 l 21 Since the operation is performed according to P , P , ...,
Covered! 41 Test circuit 1 can be simulated.

Problems to be Solved by the Invention However, in the conventional circuit simulation device described above, the test pattern P outputted by the pattern generator 2 is the pattern P , P , P , P .

+1 21 31 4
1... occurrence order, and data lengths T 1 and T .

Since 11 2 l T , T , . . . are fixed, it is necessary to create a new test pattern in order to perform a simulation that predicts changes in the situation for each circuit under test l.

In this way, there is a problem in that it requires a great deal of effort and time to recreate test patterns for performing simulations that predict changes in the situation for each circuit under test 1.

The present invention solves these conventional problems, and aims to provide a circuit simulation device that can easily simulate a circuit under test in a state similar to an actual hardware test environment. It is.

Means for Solving the Problems In order to achieve the above object, the present invention provides a pattern generator that stores various test pattern data in advance and generates and outputs test pattern signals based on the data according to the requirements of the circuit under test. It is equipped with the following.

Therefore, according to the present invention, when the circuit under test requests a test pattern according to a change in the situation, the pattern generator outputs a test pattern according to the request. can be simulated.

Embodiment FIG. 1 is a block diagram showing the configuration of a circuit simulation apparatus according to an embodiment of the present invention.

In FIG. 1, reference numeral 11 indicates a circuit under test for performing simulation, which outputs a request signal requesting a test pattern in accordance with a change in the situation.

12 indicates a pattern generator, and a built-in memory (RAM).
) By registering data such as timing and intervals in 12a, normal test patterns and test patterns requested by the circuit under test 11 depending on the situation are sequentially stored in memory 2.
This is to read and output from a.

13A is a first data line that sends a request signal from the circuit under test 11 to the pattern generator 12; 13B is a second data line that sends data (test pattern) from the pattern generator 12 to the circuit under test 11; 3C indicates a third data line for sending a data sending completion signal from the pattern generator 12 to the circuit under test 11.

FIG. 2 is an explanatory diagram showing a test pattern output by the pattern generator of the present invention.

In FIG. 2, P is a test pattern composed of various data, P , P , P .

+2 22 32P,... is pie 2 that constitutes the test pattern P

2 turns, T , T , T , T ,
...is pa+2 22 32
42 turns P, P , P , P ,
...data 1-22 3
2 Indicates 42 length.

In addition, the test pattern P is each pattern P, P
, P , P , ... data length 2
22 32 42T ,T
, T , T , ... +2 as necessary
22 32 42 change.

Next, the operation of the above embodiment will be explained.

In the above embodiment, the memory 12 of the pattern generator 12
By registering data in a, various test patterns P can be stored in the memory 2a.

In this way, various test patterns P are stored in the memory 12a.
After storing , the simulation of the circuit under test 11 is started.

However, since handshaking is used to transfer data between the circuit under test 11 and the pattern generator 12, even if the pattern generator 12 starts operating, the circuit under test 11 sends a request via the first data line 13A. If the signal is not sent, the test pattern P is not sent to the circuit under test 11.

Therefore, when a request signal is sent from the circuit under test 11 to the pattern generator 12 via the first data line 13A, the pattern generator 12
After sending a certain amount of data (test pattern P) to the circuit under test 11 via the third data line 13
A data sending completion signal is sent to the circuit under test 11 via C.

The pattern generator 12 then stops until the next request signal is supplied.

Note that the data is transmitted with the timing and interval also controlled.

Thereafter, similar operations are repeated one after another.

Thus, according to the above embodiment, the pattern generator 12
By once registering the data in the memory 2a, the pattern generator 12 sends out data (test pattern P) according to the request signal of the circuit under test 11 while controlling the timing and interval. Flexible data transmission becomes possible.

Further, since the pattern generator 12 can be used in an actual hardware test of the circuit under test 11, a simulation environment close to an actual hardware test environment can be realized.

Effects of the Invention As is clear from the above embodiments, the present invention records various test pattern data in advance, reads out data in accordance with the requirements of the circuit under test, and generates a test pattern signal using this data. Since a pattern generator for output is provided, by registering data in the pattern generator, it is possible to output a temporally flexible test pattern that matches the situation of the circuit under test and perform simulation of the circuit under test.

Another advantage is that the actual hardware test environment and simulation environment can be unified.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a circuit simulation device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing a test pattern output by the pattern generator of the present invention,
FIG. 3 is a block diagram showing the configuration of a conventional circuit simulation device, and FIG. 4 is an explanatory diagram showing a test pattern output by a conventional pattern generator. 1■...Circuit under test, 12...Pattern generator,
12a...Memory. Figure 1

Claims (1)

[Claims] A circuit under test is simulated using a test pattern signal, and a means for pre-storing data of various test patterns is provided, the data corresponding to the request of the circuit under test is read from the storage means, and a test pattern signal is generated using this data. A circuit simulation device equipped with a pattern generator that outputs a pattern.