JPH0363107B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an image processing device. Copying devices that reproduce original images are widely used. However, this type of copying apparatus simply copies the same image as the original. Only image processing such as reducing or enlarging the original image and copying it, changing the image density, etc. is possible. In addition, by reading the original image as an electrical signal and electrically processing the image information converted into an electrical signal, in addition to the above-mentioned functions, it is also possible to extract and duplicate a portion of the original, and to create multiple images. Image processing apparatuses have been proposed that can perform image processing such as combining images or changing the image density of only a portion of a document.
However, as this type of image processing apparatus has many functions, the apparatus becomes complicated and users are limited to those who are familiar with the apparatus. Moreover, the image processing time is long or long, which is inconvenient for the user. In view of the above points, it is an object of the present invention to provide an image processing device that can perform image processing with simple operation and at high speed. a recording means for recording an image; a digitizer having a coordinate input surface corresponding to a document and outputting coordinate information representing a desired area of the document based on instructions on the coordinate input surface with a pen; display means for numerically displaying the coordinate information and graphically displaying a desired area of the document defined by the coordinate information; The present invention provides an image processing apparatus that records an image of a desired area of the displayed document on a recording material by the recording means. FIG. 1-1 shows the configuration of an embodiment of an image processing apparatus according to the present invention. 1 is a reader section that has a line sensor such as a CCD that photoelectrically converts and reads the original image;
Reference numeral 2 denotes a buffer memory constituted by a semiconductor dynamic memory that stores image information of a document converted into an electrical signal serially outputted from the reader section 1 in units of one document of a predetermined size; A printer unit includes a laser beam printer that forms an image on a recording material such as paper using stored image information that is serially output; 4 is a disk memory that stores all or part of the image information stored in the page memory 2; disk memory 4
Image information is also transferred from the buffer memory 2 to the buffer memory 2. The disk memory 4 also stores image processing information. 5 is an image processing unit that processes the image information output from the reader unit 1, the image information stored in the buffer memory 2, and the image information stored in the disk memory 4; 6, the user sends the image processing unit 5 to the image processing unit 5; 7 is a CRT for displaying the processing information input by the digitizer 6 and allowing the user to easily input or modify the processing information in an interactive manner; 9;
is a DMA controller that controls DMA transfer of image information. Further, the buffer memory 2, disk memory 4, and image processing section 5 are collectively referred to as an image processing control section 12. A perspective view of the device of the embodiment is shown in 1-
Shown in Figure 2. 10 is an image processing unit composed of an image processing control section 12 having a buffer memory 2, a disk memory 4, an image processing section 5, a reader section 1, and a printer section 3; 11 is a digitizer 6;
This is an image processing information forming unit composed of CRT7. FIG. 2 shows a perspective view of the digitizer 6. 6 is the digitizer body, 8 is a stylus pen, and when the stylus pen 8 points on the digitizer 6, the coordinate information of the specified point on the digitizer 6 is sent to the image processing unit 5, and the image processing unit 5 Image processing information corresponding to the information is recognized.
The area 6-1 of the digitizer 6 is an input section provided for inputting alphabets, numbers, and character string commands, and the diagonally shaded area 6-2 is a paper placement position where the original or recording material is placed. . FIG. 3 shows a detailed view of the board of the digitizer 6.
In this embodiment, in order to simplify the explanation, a case will be described in which an A4 size original and recording material are used. A paper placement position 6-2 indicated by diagonal lines corresponds to A4 size paper, and the paper is placed in accordance with the placement reference 6-3. As a result, the paper placement position 6-2 on the digitizer 6 and the image information stored in the buffer memory 2 have a one-to-one correspondence. For example, if you want to extract a part of the original image stored in the buffer memory 2, you can specify the extraction position by placing it on the original digitizer 6 and actually pointing the position on the original with the stylus pen 8. . As mentioned above, the input section 6-1 contains numbers,
Alphabetical and character string command groups are divided into sections as shown in the figure. For example, "D"
If you want to input, press "D" with stylus pen 8.
by indicating the enclosed part. Figure 4 shows the screen configuration of the CRT7. In this embodiment, the CRT 7 is a 12-inch color television (JC-1202DH) manufactured by NEC. An area 7-1 on the screen indicates an input image area corresponding to A4 size, the background color is white, and an area 7-4 designated by the digitizer 6 is displayed in green. Area 7-2 indicates an output image area corresponding to A4 size, the ground color is blue, and area 7-5 designated by the digitizer 6 is displayed in red. Area 7-3 is an application buffer that displays processing information input from digitizer 6, and area 7-6 is a text buffer that displays the completed application. A method of operating the image processing apparatus of this embodiment will be described below. For an overview of the operation of this device, please refer to the reader section 1.
The image information thus read is subjected to desired image processing and outputted by the printer section 3. Here, processing information for image processing is provided by the digitizer 6.
This program is previously stored in the disk memory 4 as a program while interacting with the area 7-3 of the CRT 7, and image processing is performed in accordance with the stored processing information. A program for this image processing is defined as an application file. In addition, the image processing unit 5 can store a plurality of application files, and each application file contains a combination of two digit numbers or six alphanumeric characters, numbers, and blanks.
Files are named using a standard method. On the other hand, image information that is transferred from the buffer memory 2 to the disk memory 4 and stored in accordance with processing information is defined as an image file. Since the disk memory 4 stores a plurality of image files, each image file is given a file name using two methods: a two-digit number, a six-character alphabet, or a combination of numbers and blanks. Note that it is possible to specify whether these two types of files can be erased or not when they are stored. In other words, “W”
If you enter "@", it means that it cannot be erased, and if you enter "@", it means that it can be erased. Next, definitions of commands for image processing input from the digitizer 6 will be shown. The format of the command is shown in Figure 5. a is a command character and b is a parameter. As shown in the figure, a command is defined by a parameter consisting of a combination of a single command character (alphabet), a number enclosed in parentheses, an alphabet, and a blank. However, parameter b may be unnecessary depending on the command. The types of parameters will be explained below. [Parameters related to image quality] Regarding image quality, image processing such as halftone specification and edge enhancement can be performed. When specifying halftone, dither processing is performed when reading the original, and there are 8 types of dither patterns, ``1'' and ``2''.
...The darkness of the halftone is fixed by inputting the number "8" through the input section 6-1 of the digitizer 6.
Also, if you do not want to specify a halftone, enter @. In addition, in the case of edge emphasis, the digitizer 6
Enter "E" in the input section 6-1, otherwise enter "@". [Parameters related to coordinates] There are two parameters, position and size, regarding coordinates indicating the extraction position and movement position of the image. Input these parameters using digitizer 6.
The input is made by indicating the desired position of the paper placement position 6-2 with the stylus pen 8, and as described above, the area is displayed on the CRT 7 in a color different from the background color, and at the same time, the area 7 of the CRT 7 is -3 is displayed as a specific 3-digit number (in mm). The parameter "position" indicates the reference coordinates (X and Y coordinates) of the desired position, and the parameter "size" indicates the length in the X and Y directions from the reference coordinates. "Parameters Related to Transfer to Buffer Memory 2" As described above, the image information of the document from the reader section and the image information from the disk memory 4 are input to the buffer memory 2. If these image information are to be combined, "0" is input on the digitizer 6, otherwise "@" is defined. The types of one-character commands are explained below. These are input by pointing each character in the input section of area 6-1 of digitizer 6 with a stylus pen. ΓM... Clear buffer memory 2 ΓF... Clear image file ΓR... Read original ΓP... Printer output ΓL... Load image file into page memory 2 ΓS... Store image information in buffer memory 2 in disk memory 4 ΓE... Application Executing an image file ΓW...Temporarily suspending the application file in progress ΓQ...Cancelling the application file in progress ΓA...Changing the write protect specification for the image file ΓB...Changing the write protection specification for the application file ΓT...Application Transfer the file from the image processing unit and display it on the text buffer Next, we will explain the types of character string commands. "APC transfer"...The processing information of the application buffer in the area 7-3 of the CRT 7 is transferred to the image processing section 5 and stored. “TEX transfer”: Transfers the contents of the text buffer to the image processing unit 5. "EDIT"...Moves the cursor on the CRT 7 to the application buffer in area 7-3. "EXIT"..."EDIT", "TRACE",
Cancel "POSITION" and "SIZE". “TRACE”…Displays the contents of the application file on the CRT7. "ENTER"...Moves the contents of the text buffer to the application buffer. “DELETE”…Deletes the character on the cursor. “CLR LINE”…Clear area 7-3 of CRT7. “←”…Moves the cursor one position to the left. “→”…Moves the cursor one position to the right. “Screen clear”…Area 7-1 and 7- of CRT7
Clear 2. “POSITION”…Position input specification. "SIZE"...Size input specification An example of image processing using the above parameters, single character command, and character string command will be explained using FIG. 6. This image processing extracts the image information of the area n1 of the first document shown by 9 and the area n2 of the second document shown by b, and rearranges them as shown by C to create a list. It is. (Note that the file name of the application file in which this image processing is programmed is 01.) The procedure for creating the application file will be described below. The first document a is placed on the paper placement position 6-2 of the digitizer 6. Indicate "0" and "1". …Set the application file name to 01. Instruct "R". ...The original is read and stored in the buffer memory 2. Indicate "S", "(", "0", and "1")... Store the image information of area n1 extracted from document a in the disk memory 4 as an image file with file name 01. Instruct "POSITION". Fig. 6 Indicate point (A) of document a in Figure 6. “EXIT” …Input position coordinates. Instruct “SIZE”. Indicate point (B) of document a in Figure 6. “EXIT” …Size (distance from position) ) input. ")"...Complete parameter input for image file 01. The original a is removed from the paper placement position 6-2 of the digitizer 6, and the original b is placed thereon. “R”: Reads the original and stores it in the buffer memory 2. "S""(""0""2"...Extract document b
The image information of area n2 is stored in the disk memory 4 as an image file with file name 02. "POSITION" Indicate point (C) of manuscript b in Figure 6. “EXIT”…Input position coordinates. "SIZE" Indicate point (D) on manuscript b in Figure 6. “EXIT”…Enter size. 〓〓 ")"...Complete input of parameters for image file 02. 〓〓 The original b is removed from the paper placement position 6-2 of the digitizer 6, and the recording material C is placed thereon. 〓〓 "L""(""0""3"... Save the image file with file name 03 (content is 0) to buffer memory 2
Stored in. 〓〓 "@"")"...Stores the image information of file name 03 in place of the image information already stored in buffer memory 1. 〓〓 "L"``(''``0''``1''...Load the image file with file name 01 to buffer memory 2. 〓〓 ``0''...Store over the image information already stored in buffer memory 2.〓 〓 "POSITION" 〓 〓 〓 〓 点。。。。。。。。。。。。。。。。。。。。。。. 〓〓 “L” “(” “0” “2”…Load the image file with file name 02 to buffer memory 2. 〓〓 “0”…Storage over the image information already stored in buffer memory 2.〓 〓 "POSITION" 〓 〓 Instructions (F) of the record material C in Fig. 6. 〓 〓 〓… x…………………………。。。。。。。。。。。。。。。。。。。。。。。。 〓〓 “P” “(” “5” “)”…Set the number of prints as 5. 〓〓 "APC transfer"... The application file formed by the above ~〓〓 is transferred to the image processing unit 5.
Transfer to. Stored in disk memory 4. The above processing information is generated by pointing the digitizer 6 with the stylus pen 8. In other words, instructions for extracting arbitrary images and positions for image composition and command information for reading images and performing image processing can be input on the same digitizer 6. Therefore, image processing information can be easily formed by the same means. In addition, the image information formed as above is
It is displayed on the application buffer 7-3 of the CRT7. Figure 7 shows this. At the position indicated by a rectangle in FIG. 7, coordinate information input by pointing the paper placement position 6-2 on the digitizer 6 with the stylus pen 8 is a 3-digit number in each of the X and Y directions. (Unit: mm). For example, point A of document a in Figure 6 is X coordinate 98 mm and Y coordinate 63 mm.
At the position, point B is 23mm in the X direction from the A coordinate in the Y direction.
If it is 54 mm, the first line in Fig. 7 will be 01 RS (01098063023054) RS... Here, the operation of the device using the application file with file name 01 can be summarized as follows. First, the first document shown in FIG. Store. Next, the second document shown in FIG. 6b is read by the reader unit 1, stored in the buffer memory 2, and image information n2 from the stored image information is stored in the disk memory 4 with a file name 02. Store. After that, file name 03 from disk memory 4
(In the image processing example described above, the image file with file name 03 is a white image, and by transferring this image file to buffer memory 2, buffer memory 2 is completely cleared.) , the image file with file name 01 is transferred to the m1 area of the buffer memory 2, and the image file with the file name 02 is transferred to the m2 area of the buffer memory 2 and stored therein. As a result, one page of image information is formed in the buffer memory 2 in which image information n1 and n2 are arranged as shown in FIG. 6C. Then, all the contents in the buffer memory 2 are outputted to the printer section 3, and recorded on five recording materials by the printer section 3. Furthermore, the application file for the above-described image processing was stored in the disk memory 4 with the file name 01 by the "APC transfer" which was last instructed by the digitizer 6. When actually driving the image processing apparatus using the processing information (application file) stored in the disk memory 4 in this way, the driving start command is provided in the image processing unit 10 shown in FIG. 1-2. The information is input from the operating section 13 located there. 8th
The figure shows a detailed view of the operation section 13. 13-1 is a two-digit display that displays the application file name; 13-2 is a number display that displays the desired number of copies to be printed by the printer section 3; 13-3 is a keyboard for setting numerical values; and used to set the desired number of prints. 13-4 is an enter key for inputting numerical values set on the keyboard 13-3, 13-5 is an execute key for starting image processing, and 13-6 is a stop key for interrupting image processing in progress. Stop key 1
When 3-6 is pressed, the device goes into standby after completing the task currently in progress. 1
Reference numerals 3-7 to 13-12 are a group of lamps that display the device status of the image processing unit 10, and 13-7 is a group of lamps that display the device status of the image processing unit 10. Reference numeral 13-7 indicates that the application file input from the keyboard 13-3 and displayed on the display 13-1 is stored in the disk memory 4. A lamp indicating that the memory is not stored.
A lamp 13-8 indicates the occurrence of a paper jam in the recording material supply system of the printer section 3. Reference numeral 13-9 indicates a lamp indicating the occurrence of a paper jam of a document in the automatic document feeder that automatically conveys the document to the reader section 1 and discharges the document after reading the document;
-10 is a lamp indicating that the recording material in the printer section 3 has run out; 13-11 is a lamp indicating when it is time to replenish developer in the printer section 3; 13-12 is a lamp indicating that the device is not in standby mode; If one or more of the five lamps other than the lamps 13-11 are lit, the reader section 1 and printer section 3 do not operate. In addition, if one or more of the above five lamps lights up while the device is operating,
After completing its operation at that point, the device stops. Next, an example of an operation for performing image processing based on the application file formed as described above and stored in the disk memory 4 will be described. As an example, it is assumed that image processing is performed on an application file with file name 23 and five prints are obtained. Processing information related to image processing is stored in the disk memory 4 as an application file, so in this case, the application file with file name 23 is called from the disk memory 4, transferred to the sequence RAM of the image processing section, and then the desired print is performed. The only operations required are setting the number of sheets (5) and setting the document on the reader section 1. Further, this device is designed to provide the user with key input procedures from the device side. In other words, when inputting the file name of the application file, the application name display 13-1 flashes, and when inputting the number of prints, the print number display 13-2 flashes to prompt the user to input. . The situation is described below. 1 Display 1 showing the application file name
3-1 is blinking as "00". 2 The user presses "2" and "3" for the file name on the keyboard 13-3. 3 The display 13-1 is flashing "23". 4 The user presses the "ENTER" key 13-4. 5 Display 13-1 stops blinking and displays "23",
At the same time, the print number display 13-2 flashes "00". 6 The user presses the print number "5" on the keyboard 13-3. 7 The display 13-2 is flashing "5". 8 The user presses the "ENTER" key 13-4. 9 Display 13-2 stops blinking and displays "05". 6 Press the "EXCUT" key 13-5. 7 The device starts operating. In this way, when image processing is performed using the application file already stored in the disk memory 4, the image processing can be performed without the need for the image processing information forming unit constituted by the digitizer 6 and CRT 7. be able to. FIG. 9 shows a block diagram of the circuit of this embodiment. 1 is a reader section, 3 is a printer section, 6 is a digitizer, 7 is a CRT, 12 is a buffer memory 2, a disk memory 4, and an image processing section 5 shown in Figure 1-1.
This is an image processing control section whose main component is a DMA controller 9. The image processing control unit 12 includes a multi-bus 12-1.
0 is set. Multibus 12-10 is typically a standard bus. This multibus 12-1
A circuit block that can obtain the right to use 0 and control other circuit blocks is called a master function block, and one that cannot is called a slave function block.The four circuit blocks connected to multibus 12-10 are called master function blocks. In other words, CPU circuit block 12
-1, DMA controller 9, buffer memory circuit block 12 comprising semiconductor buffer memory;
-3. Of the reader and printer sequence controller 12-4, the CPU 12-1 and DMA controller 9 are master function blocks, and the buffer memory circuit block 12-3 and reader and printer sequence controller 12-4 are slave function blocks. These four circuit blocks are connected to multi-bus lines 12-12, 12-13, 12-14, and 1, respectively.
2-15 is connected to the multi-bus 12-10. 12-16 to 12-20 are a DMA controller 9, a reader & printer sequence controller 12-4, a dither controller 12-9, a shift memory 12-5, and a buffer memory circuit block 1.
This is an interrupt line input from 2-3 to the CPU circuit block 12-1. 12-21, 12-2
2 are two line sensors CCD1 of the reader section 1,
This is an image signal line that transfers image information photoelectrically converted by 2. 12-23 is a dither controller 12-9 in which information regarding dithering for image quality processing is stored.
This is the line output from. 12-24 and 12
-25 A/D converts the image information obtained from the line sensors CCD1 and CCD2 according to a predetermined threshold when edge emphasis is specified, and when halftone is specified, the dither controller 12-9
This line transfers image information that has been A/D-converted and subjected to image quality processing based on signals from , and transfers control information regarding these image quality processes. Reference numeral 12-26 is a line for transferring one scanning line of image signals obtained by the parallel image signals of lines 12-24 and 12-25 to the buffer memory circuit block 12-3, and includes control information thereof. 12-27 is
CPU12-1 is buffer memory circuit block 1
This is a refresh trigger signal line for the dynamic memory which is the buffer memory 2 in 2-3. Since the buffer memory 2 has two banks, 12-28 is a bank selection signal line. Reference numeral 12-29 is a period signal line indicating a period during which image information is being inputted and outputted from the shift memory 12-5 to the buffer memory circuit block 12-3. Reference numeral 12-30 is a line for outputting one piece of serial image information from the buffer memory circuit block 12-3 to the printer section 3. Reference numeral 12-31 is a video blank signal that causes the laser of the printer section 3 to emit light in a non-image area in the case of background scanning, and a signal line that forces the laser to emit light in order to obtain a horizontal synchronization signal. 12-32 is dither controller 1
2-9 is a signal line that determines the coordinate information and design type for specifying the area on the document to be halftone-processed. 12-23 is a line for transferring the coordinate information on the digitizer 7 to the CPU 12-1, and the file information in the disk memory 4 is sent from the CPU 13-1 to the CRT & digitizer controller 12-8 via this line. 12
-34 is a line into which coordinate information from the digitizer 6 is input. 12-35 is a video signal line output from the CRT & digitizer controller 12-8. 12-36 is a line for input signals and processed signals to be processed by the processor in the reader and printer sequence controller 12-4. The interface 12-6 sends the output signals of the various sensors provided in the reader section 1 and printer section 3 to the reader & printer sequence controller 1.
2-4, and output drive signals for motors, heaters, lasers, etc. 12-37 is a signal line for driving the optical system scanning motor of the reader unit 1; 12-38
is a sensor signal line within the reader 1. 12-
39 is a line for interacting with the user via the operation unit 13. 12-40 is a line that detects the rotation of the scanner of the printer section 3; 12-41 is a line that detects the temperature of the laser to stabilize the laser;
Reference numeral 12-42 is a signal line for driving the printer section 3 and a signal line for various sensors. The buffer memory circuit block 12-3 is connected to the multi-bus 12-10.
There are two lines not connected to the line 12, which input serial image information from the reader section 1.
-26, a line 12-30 that outputs serial image information to the printer section 2, and a multibus 12-1
Lines 12-14 connected to 0 are provided as image information transfer lines. This prevents the CPU 2-1 connected to the multi-bus 12-10 from executing operations related to image processing even though image information is being input from the reader section 1 or output to the printer section 3. can. As explained above, when performing image processing, prior to actually driving the image processing device, processing information related to the image processing, such as designation of the image processing area of the document, instruction of image processing content, and printout area designation, designation of the file name of image information to be stored in the image processing unit, and designation of the file name of a set of image processing information by pointing on the digitizer 6 with the stylus pen 8 while interacting with the CRT 7. I will do it. Therefore, an image processing device that can easily perform image processing in that it is easy to operate, does not require complicated equipment, and information regarding image extraction position specification and image processing can be formed by a common means. I will provide a. In addition, since a semiconductor dynamic memory is used to store one page of image information read by the line sensor of the reader section 1 and continuously output, the image information output from the reader section 1 is stored. When inputting to the means, it was possible to directly input without using synchronization means such as an intermediate buffer. The same applies to the case of outputting to the printer section 3, and the image information can be read into and read out from the memory means at high speed. FIG. 10 shows details of the CRT & digitizer controller circuit block 12-8 shown in FIG. 9. This block uses Apple's APPLE, and Figure 10 shows the circuit diagram of APPLE. So APPLE for details
Please refer to the manual. CPU circuit block 12-1 shown in Figure 9
The details are shown in FIG. This block includes Intel's single board computer SBC86/
12 is used, and Figure 11 shows the circuit diagram of the SBC86/12. So for details
Please refer to the SBC86/12 manual. The details of the reader and printer sequence controller circuit block 12-4 shown in FIG.
Shown in Figure 2. This block uses Intel's single board computer SBC569, and Figure 12 shows the circuit diagram of the SBC569. Therefore, please refer to the SBC569 manual for details. Details of the DMA controller circuit block 9 shown in FIG. 9 are shown in FIG. 9-1 is DMA
The Intel 8289, an IO processor with built-in functions, is the core of the functionality of this circuit block.
Please refer to the 8089 manual for details on the device itself. 9-2 is a bus arbiter 8289 that connects to the multibus 12-13 according to the status information from the IO processor 9-1.
Obtained the right to use 2-13, and after using it, multibus 1
It has the function of releasing 2-13. Please refer to the Intel 8289 manual for detailed functions. 9-3 is a bus controller 8288, which after acquiring the right to use the multi-bus 12-13 by the bus arbiter 9-2, outputs or inputs address and data signals to the multi-bus 12-13, and also performs memory line command MWTC and memory read. Output the command. In other words, the block having the master function for the multi-bus 12-13 has the bus arbiter 9-2 and the bus controller 9-3, thereby making it possible to access the multi-bus 12-13. Therefore, the slave function block does not have these two devices, and the multibus 12-13
Access will be more unilateral. The details of the bus controller 9-3 itself are as follows: Intel 8288
Please refer to the manual. 9-4 is a clock generator 8284 which uses an external oscillator as an input means and supplies a clock signal of a predetermined frequency to the IO processor 9-1, bus arbiter 9-2, and bus controller 9-3, and 1, the memory OR is sent from the peripheral circuit as information for determining whether the bus cycle enters a wait state and information for determining whether to cancel the wait state.
Receives an I/O acknowledge signal (response to write or read from memory or I/O),
It has a function of outputting a ready signal accordingly. Please refer to the Intel 8284 manual for details. Reference numeral 9-5 is an internal bus within this circuit block, which serves as a local bus for the multi-bus 12-13. As for the bus structure, the address bus is 16 bits and has an address space of 64 KBYTE, and the data bus is 8 bits. 9-6 is an address/data buffer, and this block consists of two address/data buffers, one for multibus 12-13 and the other for internal bus 9.
-5. The basic function of this buffer 9-6 is the IO processor 9-1.
The address and data information output from is multiplexed and output in a time-divided manner on the same line. In other words, the address information is output first and then the data information, so the address information is first latched into the address buffer. , depending on whether the next data information is a read command or a write command.
The purpose is to switch between transferring and reading this data. Regarding the former buffer, address information has already been output from the IO processor 9-1 to the address/data line at the timing when the address latch enable ALE signal is output from the bus controller 9-3. The address information is latched into the address buffer by the signal. After that, if the bus arbiter 9-2 has acquired the right to use the multibus, the bus arbiter 9-2 outputs an address enable AEN signal, and this signal causes the address buffer to transfer the latched address information to the multibus. Output to 12-13. If this is for a write command, the IO processor 9-1 outputs the address information on the address/data line, and at that point the multibus 12-1 outputs the address information on the address/data line.
13 has been acquired, the data information is output.
Accordingly, the bus controller 9-3 outputs a data enable DEN signal, and outputs data information together with address information to the multi-bus 12-13 via the data buffer. At this time, the transmit or read switching signal is output as DT/R from the bus controller 9-3, and data information is transferred to the multi-bus 12-13 accordingly. In the case of a read command, the bus controller 9-3 does not output the DEN signal, and the data buffer sets the DT/R to read mode and outputs the multibus 1.
2-13 data information to IO processor 9-1
on the address/data line. Reading this data by the IO processor 9-1 uses transfer knowledge from the accessed memory.
This is done after checking the XACK signal. Regarding the address/data buffer for internal bus 9-5, the timing of latching the address is the same as described above. In other words, the address buffer for the multi-bus 12-13 and the address buffer for the internal bus 9-5 latch the address information output from the IO processor 9-1 in the same way, regardless of which bus is accessed. do. However, only for the multi-bus 12-13, the signal indicating whether or not to output is determined by the AEN signal from the bus arbiter 9-2.
Next, whether or not to enable the output of the data buffer for the internal bus is determined by the peripheral data enable PDEN signal of the bus controller 9-3, and the direction switching between transmit and read is determined by the peripheral data enable PDEN signal for the multi-bus 12-13. Like the data buffer, this is done using the DT/R signal of the bus controller 9-3. 9-7 is a synchronization signal generation circuit whose purpose is
When the IO processor 9-1 accesses peripheral units (memory, I/0, etc.) in this block, it checks the responses from these units and then
The IO processor 9-1 is configured to start the next operation, and sends these response signals to the IO processor 9.
The clock generator 9-4 sends a ready signal to the IO processor 9-1 in synchronization with the -1 bus cycle. 9-8 is a ROM and has two 2716 devices. Accordingly
This memory has a capacity of 4 KBYTES and stores the microprogram of the IO processor 9-1. 9-9 is a normal I/O port, and two 8212s are used as devices. Although its purpose is to control peripheral devices, in this embodiment it does not control anything and is left open. 9-10 is an address decoder that connects an internal bus 9-1 to generate chip selection signals for ROM 9-8 and I/0 port 9-9.
Part of the address information (upper few bits) of No. 5 is decoded. 9-11 which is disk memory 4
is a hard disk unit whose storage capacity is
10MBYTE, configuration is 350 tracks, 1 track 18
One sector is 512 BYTE.
It also has a disk controller circuit inside.
It is designed to interface with an 8-bit data bus. The model name is WDS-10, and for details, please refer to the Sword Computer WDS-10 manual. Reference numeral 9-12 is a data/data line of the IO processor 9-1, and address information and data information are output on the same line in a time-division manner.
The order of output is address first, then data.
Reference numeral 9-13 is a signal line for address information and data information output to the internal bus 9-5. 9-14 is a signal line for address information and data information output to the multi-bus 12-13. 9-15 is IO
This is a signal line for status information output from processor 9-1 to bus arbiter 9-2 and bus controller 9-3. 9-16 is CPU12-1
Channel attention CA signal which is a DMA request signal from IO processor 9-1 to CPU1
This is a system interrupt SINTR signal for notifying DMA completion to 2-1. This SINTR signal is input to the interrupt terminal of the CPU 12-1. Lines 9-17 are the address latch enable ALE signal, peripheral data enable PDEN signal, and data input signal that the bus controller 9-3 outputs to the address/data buffer 9-6 based on the status information from the IO processor 9-1. Bull DEN
signal and data transmit/read DT/R signal. Line 9-18 is bus arbiter 9-2
After acquiring the right to use the multibus 12-13 according to the status signal of the IO processor 9-1, it transfers the already latched address information to the address/data buffer 9-6 to the multibus 12-1.
Address enable, which is the signal output to 3.
It is an AEN signal. Lines 9-19 are signal lines for handshaking with multibuses 12-13 regarding the right to use them. The master function circuit blocks connected to the multi-bus 12-13 have predetermined bus usage priorities, and in this embodiment, the CPU 12-1 has the highest priority, and the second
It is set to be DMA controller 9. First, when the bus arbiter 9-2 issues a bus request BREQ signal to the multi-bus 12-13, if the CPU 12-1 with a high priority is not using the multi-bus 12-13, the bus priority is input.
You will receive a reply indicating that it can be used as a BPRN signal. When the bus arbiter 9-2 confirms this, it outputs a busy signal to notify that the bus is in use. Lines 9-20 connect external memory or I/O through multibus 12-13.
etc., the response signal from them is the transfer acknowledgment XACK signal line. Line 9-21 is IO processor 9-1
When accessing byte information at an odd address using the byte high enable BHEN signal that is output together with address information when accessing memory from (data is output to the upper byte of the data bus)
When 16-bit word information is accessed by addressing an even address (byte data at an even address is output to the lower byte of the data bus, byte data at an odd address is output to the upper byte of the data bus). This memory is structured to be divided into even banks and odd banks based on signals, and is used as a switching signal to determine which bank to access. Lines 9-22 are clock signals, and lines 9-23 are two types of reset signals, power-on reset and manual reset. Line 9-24 is a ready signal synchronized with the bus cycle of IO processor 9-1. Lines 9-25 are a memory line command MWTC signal and a memory read command MRDC signal which are output together with address information and data information when accessing the multi-bus 12-13. Line 9-
26 is an ALE signal from the bus controller 9-3 and a signal S2 which is one of the status information.
As mentioned above, this S2 signal is used to store the internal bus address buffer at this point, since the address information is latched simultaneously in the multibus address buffer and the internal bus address buffer, regardless of which buffer is accessed. It is necessary to determine whether the content latched in the buffer is address information for the internal bus. Therefore, this determination is made in the address decoder 9-10 based on the S2 signal. That is, the S2 signal is this identification information, and when S2=1, the multibus 12-13 is used, and when S2=0, the internal bus 9-13 is used.
5, and this signal is latched and held by the ALE signal. Line 9-27 is the IO processor 9-
1 accesses data on the internal bus 9-5 in read mode, the I/O read command IORC signal output from the bus controller 9-3
Interrupt acknowledge INTA signal and ALE output from bus controller 9-3 when fetching the microprogram from ROM 9-8
It's a signal. In the synchronization signal generation circuit 9-7, IORC
IO of internal bus 9-5 by signal and INTA signal
When the processor 9-1 accesses it, an identification signal indicating that it is in read mode is generated. The ALE signal is used as a clock within the synchronization signal generating circuit 9-7. Line 9-28 is a data bus, and command information, result information, and data information on this bus are provided as one address, and status information is provided as another address. The former three pieces of information are differentiated by the disk unit 9-11 by being sequentially input and output.
Lines 9-29 are the two address information lines mentioned above. Lines 9-30 are command busy signals, which are identification signals for the two addresses above.
This is the CBUSY signal. In addition, the synchronization signal generation circuit 9-
The reason why the signal on line 9-30 and the signal on line 9-27 are input to disk unit 9-11 is because
In the read mode and write mode for a set of command information, result information, and data information, the timing at which the data becomes ready is different, and the timing at which the data becomes ready is also different for the read mode and write mode for status information. This is because it is necessary to create four types of wait times to be given to the IO processor 9-1. Line 9-31 is the ready signal mentioned above. Lines 9-32 are a data request DREQ signal indicating that the disk unit 9-11 is in a ready state and an external termination EXT signal indicating DMA completion. Line 9-
33 is a data bus line (8 bits) for I/O port 9-9. Line 9-34 is ROM9
-8 and the upper few bits of the address information for creating the I/O chip selection signal are carried, and the line 9-35
is address information indicating a specific address in the ROM 9-8, and lower bits other than those mentioned above are carried. Line 9-36 is a data signal line of the instruction code fetched from ROM 9-8 and output onto the data bus. Line 9-37 is the chip select signal for I/O port 9-9, and line 9-38 is the ROM 9-9 chip select signal.
8 chip selection signal. Based on the above explanation, DMA in Figure 13
Explain the flow of information over time. CPU12-1 IO via line 9-16
Apply channel attention to processor 9-1. IO processor 9-1 accesses dual port RAM within CPU 12-1 via lines 9-12 and 9-14 to obtain mode and address information regarding DMA. IO processor 9-11 is on line 9-12,
Buffer memory 2 is accessed via lines 9-14. The 16-bit data on the multibus 12-13 read from the buffer memory 2 is transferred to the multibus 12-13, lines 9-14, and lines 9-1.
2 to the IO processor 9-1. The IO processor 9-1 outputs the upper 8 bits of this 16-bit data to lines 9-12 and 9.
-13, internal bus 9-5, and line 9-28 to the disk unit 9-11. Next, the lower 8 bits are taken into the disk unit 9-11 using the same route. Repeat the steps above until the EXT signal appears on line 9-32. CPU12-1 with SINR signal on line 9-16
An interrupt is sent to notify the end of DMA. In this way, image information is transferred by DMA between the buffer memory 2 and the disk memory 4 (disk unit 9-11). Furthermore, the DMA controller 9 that controls this DMA is connected to the multi-bus 12-1.
0, and this master function allows the buffer memory circuit block 12-3, which is a slave function circuit block, to be controlled.
The buffer memory 2 within can be accessed. Therefore, during image information transfer, the CPU 12-1
can perform other operations necessary for image processing. Furthermore, there are two circuit blocks with master functions, namely the CPU 12-1 and the DMA controller 9.
CPU for use of multibus 12-10
Priority is given to 12-1. This causes the DMA controller 9 to connect to the multibus 12-1.
Even if you request DMA transfer using 0, CPU12-1
Therefore, if preprocessing using the multi-bus 12-10 related to image processing and operation of each unit has not been completed, DMA transfer is prohibited. Therefore, competition between signals from a plurality of blocks on the multi-bus line 12-10 can be prevented. [Multi-bus memory space] The memory map in the four circuit blocks related to the multi-bus 12-10 will be described below.
The CPU circuit block 12-1 has a 32 KBYTE dual port RAM and an 8 KBYTE ROM as a program memory for the CPU8086. Buffer memory circuit block 2 supports A4 size images at 12pel/mm
Memory capacity when read with 8709120
Bit capacity (12 bits as 1 word)
725760words). Reader & Printer Sequence Controller Circuit Block 12-4
It has dual port RAM with a capacity of 2KBYTE. All of these are memory mapped memories, and are accessed from the multi-bus 12-13 using the memory write command MWTC signal and the memory read command MRDD signal. In addition, a 4KBYTE CPU8085 is installed on the internal bus of the reader & printer sequence controller circuit block 12-4.
ROM, which is the program memory for the CPU8085, is also memory mapped memory.
This CPU8085 is accessed by signal or has a slave function for multibus 12-13.
The address from will never appear. In addition, the DAM controller circuit block 9 has an IO processor 9.
-1 program memory 4KBYTE ROM
is provided on the internal bus 9-5, but since this memory is I/O mapped memory, this
Even if the IO processor 9-1 accesses the ROM,
That address never appears on multibus 12-13, and this memory cannot be accessed from multibus 12-13. FIG. 14 shows a memory map related to the multi-bus 12-13. The address space of multi-buses 12-13 is a memory mapped memory space for data storage.
00000 to FFFFF as 1 address per 1BYTE
There is up to 1MBYTE. As this space allocation
8 KBYTE from FE000 to FFFFF is the program memory space for 8086 in the CPU circuit block 12-1. Buffer memory 2 is as described above.
There are 755760 WORDS, converted to BYTE units.
Therefore, the buffer memory space is divided into two banks, each address space is set to 725760 addresses, and bank switching is controlled by a signal from the CPU 12-1 (No. This is done in hardware at line 12-28) in Figure 9. And the space of bank O is 0A000~BB2FF,
The space of bank 1 is 0B300 to BC5FF. 2KBYTE dual port in reader & printer sequence controller circuit block 12-4
RAM is the main purpose of the CPU8085 in the block.
This is for communication with the CPU 8086 in the CPU block 12-1, and its address space is 08000~
Assign 087FF. CPU8085 is dual port
As the address space for accessing the RAM, since this RAM has only 64 KBYTE space, the same addresses of 08000 to 087FF are given. Next is the CPU circuit block 12-1.
32KBYTE of dual port RAM
8KBYTE to CPU8086 and DMA in this block
Used for communication with the CPU8089 in the controller circuit block 9, and its address space is 06000~
Allocate up to 07FFF. On the other hand, this space
Address when accessed by CPU8089, i.e.
This address seen from CPU8089 is different,
This is listed as FF800~FFFFF. That is 06000
Make it correspond to FF800 and 07FFF to correspond to FFFFF. Therefore, CPU circuit block 12
-1 contains an address from FF800 to FFFFF, this address code is sent to 06000 via ROM.
Convert the address using hardware so that it becomes ~07FFF. 24KBYTE dual port other than above
00000 to 05FFF is allocated as the RAM address space. The above is the memory space related to the multibus 12-10, and the 4KBYTE ROM in the reader & printer sequence controller circuit block 12-4
The address space of is used as memory mapped memory.
00000~00FFF is allocated, and the address space of 4KBYTE ROM in DMA controller circuit block 9 is 00000~00000 as I/O mapped memory.
Assign 00FFF. [Structure of Buffer Memory] FIG. 15 shows an address map of the buffer memory 2 in the buffer memory circuit 12-3. This buffer memory 2 has the ability to store information resolved into A4 size (288 mm x 210 mm) at 12 pixels per 1 mm. The direction in which this document is main-scanned by the reader unit 1 is 288 mm in the length direction, and it is divided into 12 pixels per 1 mm and input from the CCD, so 3456 bits of pixels are input in one scan. Also, the direction of sub-scanning is 210mm in the width direction, and 12 lines are scanned per 1mm, so A4
A total of 2520 lines are scanned. Therefore, the memory size is 8709120 bits. 3456 bits of pixels per A4 size document are serialized
Entered 2520 times. How to address and store image information input in this way will be explained. First, divide the manuscript into square unit blocks of 1 mm x 1 mm, and use these unit blocks as one memory block.
An A4 manuscript is composed of 60480 blocks. In other words, this memory block has 12 lines of 12 bits.
There is 144 bit image information. 12 bits
If one address is given as one word, the memory block will be made up of a group of pixels with 12 addresses. Therefore, the total memory space has 725760 addresses, from address 0 to 725759, and 00000 in HEXA code.
~B12FF address space. Then,
One line of 3456-bit serial image information is divided into 12-bit pixel groups each having a length of 1 mm, and the first pixel group is stored at address 00000, and the next 12-bit pixel group is stored at address 0000C. furthermore
00018, 00024, etc., and the last 12-bit pixel group of the first line is stored at address 00D74. In other words,
Image information obtained by scanning one line is divided into pixel groups of 12 bits each, which are sequentially input to every 12 addresses. Next, when the 3456-bit serial image information for the second line is input, it will be the same as the first line.
Divided into 12-bit units, each pixel group is stored every 12 addresses from address 00001 to address 00D75. In the same manner, image information for a width of 1 mm and a length of 288 mm is stored at addresses 00000 to 00D7F. And the th
The 3456-bit image information on the 13th line is similarly divided and stored every 12 addresses starting from 00D80. The data is stored in this way, and the last 12 bits are stored at address B12FF. If you use the above method of storing with addresses, the entire A4 area will be stored in consecutive addresses in units of 1 mm x 1 mm squares. This causes the digitizer 4 to specify the image processing area in mm units, so the specified area can be
If you want to file a file, you can use DMA transfer and simply set the start and end addresses, and the data can be transferred at high speed without going through the CPU. In other words, by specifying a set of start address and end address, image information for 12 main scanning lines can be obtained.
DMA transfer will be performed. That is, extraction of 1 mm wide image information is performed by specifying the first address and the last address once. Therefore, fewer address settings are required during DMA transfer, resulting in faster transfer speeds. This is even more effective when extracting image information. To extract an image, addresses are continuous from the right side to the left side of the image to be extracted, so for example, when extracting image information with a vertical length of 20 mm, the address setting by the CPU is
It will only take 20 times. Furthermore, since the address corresponds to the image in mm units, the address can also be set in mm units, which is convenient for the user. Also,
In this example, a line sensor with a reading capacity of 12 bits per mm was used, so 1 address corresponds to 12 bits, but this number of bits may be any other value depending on the capability of the line sensor, or may be in units other than mm. The same effect can be obtained by setting the address in inches, for example. The initial address of each line to the buffer memory 2 is determined by the CPU setting an initial value in the address counter.
Also, when outputting image information from the buffer memory 2 to the laser beam printer 3, it is read every 12 addresses from the initial address, as in the case of input. FIG. 16 shows an address map when looking at the buffer memory 2 from the multi-bus 12-10. In Figure 15, the address space from 00000 to 5897F is defined as bank 0, the address space from 58980 to B12FF is defined as bank 1, and these spaces are defined as OA000 to BB2FE, respectively.
and correspond to the address space of OB300 to BC5FE.
Multibus 12-10 is a 16-bit data bus.
It has a 20-bit address bus, but the area that can be accessed by this bus is 1MBYTE. In other words, 1M pieces of 8-bit data can be accessed, and when accessing 16-bit data, it reaches address 2, so 16-bit data is input/output only when accessing an even address in WORD mode. Ru. For this purpose, as is clear from FIG. 16, every other consecutive address is assigned. Since the real address in the buffer memory circuit block 12-3 is the address shown in FIG. 15, when the buffer memory 2 is accessed from the multibus using the address shown in FIG.
The buffer memory circuit block 2 has a circuit for converting the address into the address shown in the figure in a hardware manner. By having this address conversion circuit, the address area of the buffer memory can be set in any address space. Buffer memory circuit block 12-3 in FIG.
The contents are shown in Figure 17. As shown in the figure, this block includes memory controller 2-1, memory A2-
2, memory B2-3, memory C2-4, and terminator 2-5, all of which are connected by an internal bus 2-6. The memory controller 2-1 is also connected to the multi-bus 12-14, and the buffer memory circuit block 12-3 as a whole is connected to the multi-bus 12-14.
-14 is accessed as a slave function.
Furthermore, a bank switching signal is supplied from the CPU 12-1 via a line 12-28, and a bank switching signal is supplied from the CPU 12-1 via a line 12-28.
Serial image information is input from the shift memory 12-5 via line 26, and an image signal is output from line 12-30 to the laser driver of printer section 3. Memories A, B, and C are 16K dynamic.
It is RAM and its capacity is 12 bits as 1 word.
There are 256Kwords. This memory uses IM1440IMG manufactured by Nissei Electronics, so please refer to the IM1440IMG manual for details. An address signal line, a data signal line, a read signal line, a write signal line, a refresh signal line, a memory status signal line (MEMORY BUSY), and an acknowledge signal line are input to the internal bus 2-6. Table 1 shows memory A, B, C.
for each of the addresses accessed from the multibus 12-14 and the memory controller 4-1.
E represents an address on the internal bus.

【table】

Claims (1)

[Claims] 1. A scanner comprising: a scanning means for scanning a document image; a recording means for recording an image on a recording material; and a coordinate input surface corresponding to the document; a digitizer that outputs coordinate information representing a desired area of the original document; and display means that numerically displays the coordinate information output from the digitizer and graphically displays the desired area of the original document defined by the coordinate information. and an image processing apparatus characterized in that the image of a desired area of the document scanned by the scanning device is recorded on a recording material by the recording device, and the image of the desired area of the document is displayed numerically and graphically on the display device. .