JPH036309U - - Google Patents
Info
- Publication number
- JPH036309U JPH036309U JP6581189U JP6581189U JPH036309U JP H036309 U JPH036309 U JP H036309U JP 6581189 U JP6581189 U JP 6581189U JP 6581189 U JP6581189 U JP 6581189U JP H036309 U JPH036309 U JP H036309U
- Authority
- JP
- Japan
- Prior art keywords
- input
- oscillation
- turn
- nand gate
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Oscillators With Electromechanical Resonators (AREA)
Description
第１図は本考案の一実施例を示す回路図で、第
２図は本考案の発振ＯＮ、ＯＦＦせしめる実施例
の回路図で、第３図は従来例を示す。
１……ＮＡＮＤゲート、２，３，４，１６，１
７……入力端、５……出力端、６……圧電発振素
子、７，１１……抵抗、８，１０……コンデンサ
、９……コイル、１２……電源、１３，１８……
スイツチ、１４……第１の発振回路、１５……第
２の発振回路である。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram of an embodiment of the present invention for turning oscillation on and off, and FIG. 3 is a conventional example. 1...NAND gate, 2, 3, 4, 16, 1
7... Input end, 5... Output end, 6... Piezoelectric oscillation element, 7, 11... Resistor, 8, 10... Capacitor, 9... Coil, 12... Power supply, 13, 18...
Switch, 14...first oscillation circuit, 15...second oscillation circuit.
Claims (1)
圧電発振素子と、入力端と接地間に圧電発振素子
の基本振動周波数と略々等しい共振周波数のＬＣ
直列共振回路とを具備した発振回路。 (2) ２入力ＮＡＮＤゲートの入力端の１をＯＮ
、ＯＦＦ入力せしめて発振をＯＮ・ＯＦＦせしめ
る第１項記載の発振回路。[Claims for Utility Model Registration] (1) A piezoelectric oscillation element connected between the input and output terminals of the NAND gate, and an LC with a resonant frequency approximately equal to the fundamental vibration frequency of the piezoelectric oscillation element between the input terminal and ground.
An oscillation circuit equipped with a series resonant circuit. (2) Turn on 1 of the input terminal of the 2-input NAND gate
, OFF input to turn the oscillation ON/OFF.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6581189U JPH036309U (en) | 1989-06-07 | 1989-06-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6581189U JPH036309U (en) | 1989-06-07 | 1989-06-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH036309U true JPH036309U (en) | 1991-01-22 |
Family
ID=31597978
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6581189U Pending JPH036309U (en) | 1989-06-07 | 1989-06-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH036309U (en) |
-
1989
- 1989-06-07 JP JP6581189U patent/JPH036309U/ja active Pending