JPH0362784A - Scanning method and scanning circuit - Google Patents

Abstract

PURPOSE:To attain complete operation even in the presence of a defect and to improve the yield by transferring 1st, 2nd and 3rd pulse signals whose pulse width is T with a delayed phase by a sequential delay of T/3, where T is a delay time in the drive method of a scanning line selecting and scanning sequentially 3 capacitive loads or over. CONSTITUTION:Normally shift registers A 101-C 103 transfer a delay pulse signal to a succeeding stage with a delay time of T. If there is a defect in the shift registers A101 and C103, a test circuit A104 receives an output VOUTA of the shift register A101 and a VINC to apply discrimination in a truth table as shown in figure. As the result, the VOUTA and the VINC are coincident at 0-2/3T and 5/3T or over and dissident for 2/3T-5/3T. That is, the level of 0-2/3T and T-5/3T is preserved for the periods of 2/3T-T, 5/3T-T and 5/3T-2T,.... Then a pulse signal in the entirely same timing as the delay pulse signal in the signal V'OUTA when no defect exists in the shift register A is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a scanning method and scanning circuit used in liquid crystal displays, contact image sensors, liquid crystal shutters, and the like.

(Prior Art) Scanning circuits are important components of peripheral drive circuits for liquid crystal displays, contact image sensors, liquid crystal shutters, etc.
Traditionally, shift registers have been used. FIG. 4 is a diagram showing a conventional scanning circuit composed of an N-stage shift register 402. The shift register 401 can sequentially transfer the signal input to the input terminal 403 from the first stage output 404 to the Nth stage output 407 at a constant frequency using a clock, and can be used as a scanning circuit or an image signal serial/parallel conversion circuit. It is used for.

Incidentally, recently, in order to make liquid crystal displays, contact image sensors, liquid crystal shutters, and the like smaller in size, lower in cost, and more reliable, driving circuits have been integrated and manufactured. This is based on the concept that by installing the peripheral drive circuit on the same substrate as the pixel electrode, the number of D, connections, if elements, and external drive ICs can be reduced by 1+ times. be.

(Problem to be solved by the invention) However, as liquid crystal displays, contact image sensors, liquid crystal shutters, etc. become larger in area and longer in length, it is currently difficult to form defect-free peripheral drive circuits. This is extremely difficult with process technology. In particular, in scanning circuits using shift registers, the shift registers are connected in series, so if there is even one defect in an intermediate stage, signals cannot be transferred from that stage onward, which reduces the yield of the shift register. Therefore, the poor yield of shift registers is a major factor in reducing the yield of entire devices such as liquid crystal displays, contact image sensors, and liquid crystal shutters.

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention aims to provide a high-yield shift register that operates perfectly even in the presence of defects.

(Means for Solving the Problems) The present invention provides a method for driving a scanning circuit that sequentially selectively scans three or more capacitive loads.
The third pulse signal is sequentially delayed in phase by T/3 with a delay time of T, and the transferred pulse signal is hereinafter referred to as a delayed pulse signal), and the first, second, and third pulse signals are For each signal delayed and transferred n times ((3×
n-2)-th, (3×n-1)-th, and 3×n-th delayed pulse signals, and if the rise time of the I-th pulse signal is 1(, then t□+(3×m- 3)×T/3≦t≦(t□+(
When the logic level of the first delayed pulse signal and the logic level of the third pulse signal are equal in the period T1 of 3×m-1)×T/3), (to+(3×m-2)× T
/3) ≦t≦(to+(3×m-1)×T/3) in period T2, the I-th delayed pulse signal is output as the first scanning pulse signal, and in the period T1, the When the logic level of the delayed pulse signal and the logic level of the third pulse signal are different, the third pulse signal is output as the first scanning pulse signal in the period T2, and (3 When the logic level of the (xn+1)th delayed pulse signal and the logic level of the 3xnth delayed pulse signal are equal, the (
A 3×n+1)th delayed pulse signal is output as a (S×n+1)th scanning pulse signal, and the logic level of the (3×n+1)th delayed pulse signal and the 3×nth delay are determined during the period T1. When the logic level of the pulse signal is different, at T2, the 3×nth delayed pulse signal (3×n+1) is output as the eye scanning pulse signal, and (t□+(3×m+p−2) ×T/3)≦t≦(to
+ (3X m + P) × T/3) during the period T3, the logic level of the (3 × n0 p-1)th delayed pulse signal and the logic level of the (3 × n0 p-2)th delayed pulse signal are When the logic levels are equal, (tO+(3×m+p 1)
×T/3)≦t≦(to + (3X m, + p)
×T/3) during period T4, the above (3×n+p-1)
The th delayed pulse signal is outputted as the (3×n+p-1)th scanning pulse signal, and the (
When the logic level of the 3×n+p-1)th delayed pulse signal is different from the logic level of the (S×n+p-2)th delayed pulse signal, the (3×
The n+p2)th delayed pulse signal is (3×n+p-1)
This scanning method is characterized in that the scanning pulse signal is output as the second scanning pulse signal. Here, m and n are natural numbers, and p is 0 or l.

Further, the scanning circuit of the present invention embodying this scanning method includes delay circuits A, B, and C that delay and transfer the first, second, and third pulse signals, respectively, and the delay circuits A, B, and C.
switching transistors A, B, and C that transfer the output signals of the transistors to the delay circuits D, E, and F, respectively, and transfer the input signals of the delay circuits C, D, and E to the delay circuits D, E, respectively.
, switching transistors D, E,
F, the input signal of the delay circuit C is a first input, the output signal of the delay circuit A is a second input, the inverted signal of the output is a control signal of the switching transistor A, and the output is the control signal of the switching transistor A. A dest circuit A that uses a control signal of D, an input signal of the delay circuit as a first input, an output signal of the delay circuit B as a second input, and an inverted signal of the output to control the switching transistor B. A test circuit B whose output is a control signal of the switching transistor E, an input signal of the delay circuit E as a second input, an output signal of the delay circuit C as a second input, and an inverted signal of the output. a test circuit C whose output is a control signal of the switching transistor C and whose output is a control signal of the switching transistor F, and inverters A, B, and C for inverting the outputs of the test circuits A, B, and C, respectively. and the switching transistors A, B, C, D, E,
Switching radiators G, H, I, J, K for initializing control signals of F, respectively.

L, and a control switch A for taking out the input signals of the delay circuits D, E, and F as (3×n-2)th, (3×n-1)th, and 3×nth scanning pulse signals, respectively.
, B, and C.

(Action) By taking the above-mentioned measures D, the specified time t
In this case, the scanning pulse signal can be extracted from either the output signal of the delay circuit or the defect-remedied pulse signal.Here, the defect-remedied pulse signal is extracted at the predetermined time. At t, it is a signal that has the same logical value as the positive output signal of the delay circuit.

That is, for example, from the rising time of the first pulse signal, 273T and T~5/3T, 2T~8/3T...
The logic level of the first delayed pulse signal and the third
When the logic levels of the pulse signals are equal, the first delayed pulse signal is the correct output signal. Therefore, this delayed pulse signal is output as a pulse signal to be sent to the next stage. On the other hand, if the logic level of the (th delayed pulse signal is different), this delayed pulse signal is an incorrect signal. Therefore, in this case, 0 to 2/3T, T to 5/3T
, 2T to 8/3T... outputs the third pulse signal as a pulse signal to the next stage.

In addition, the selection of these two signals is performed by l'f+7 using a logic circuit.
Since the control signal is a digital signal, even if an error occurs in the test circuit, one of the two signals will always be output as a scanning pulse signal. Therefore, it is possible to realize a scanning circuit that operates perfectly even if there is a defect in either the delay circuit or the test circuit, so that the yield of scanning circuits can be significantly improved.

(Example) Fig. 1 is a diagram showing the circuit configuration of three stages of basic scanning circuits, Fig. 2 is a diagram showing an example of the timing chart of the circuit, and Fig. 3 (aXI)) is the logic of the test circuit. It is a figure which shows a structure and a truth table.

In FIG. 1, 101 to 103 are shift registers that function as delay circuits; 104 to 106L;
Circuits 110 to 112 are switching 1-transistors that transfer signals to the next stage shift register when the output signal of the shift register is correct, and 113 to 115 are switching registers that transfer the signal to the next stage shift register when the shift register output signal is incorrect. Switching I transistors 116 to 11-8 transfer correct signals to switching transistors 113
-118 are reset I switches for initializing the control signals, and 119-121 are control switches for extracting a scanning pulse signal from a correct delayed pulse signal. Furthermore, the lock signals (12) to be input to the respective terminals are indicated by Φ1-ΦG. Signals VINA~VINC-VOUTA-VOUTC- shown in FIG.
“0UTA-■1oUTc, V”0UTA=”0UTC
1 are the signals of the lines respectively specified in FIG.

Next, the operation of the embodiment will be explained.

VINA to VINC of pulse width T are input to shift registers Al01 to Shift 1-register ClO3, respectively, at the timing shown in FIG. Here, VINA-VIN
C is a correct signal whose defects have already been repaired in the previous three stages. Normally, shift registers Al0I to ClO3 transfer delayed pulse signals to the next stage with a delay time T. Now, there are defects in shift register Al0L and shift I register ClO3, and their respective output signals VO
The case where UTA and VOUTC are constant at ground level and high level as shown in FIG. 2 will be explained.

The test circuit AlO4 inputs the outputs VOUTA and VINC of the shift 1 register Al0L and makes a determination as shown in the truth table shown in FIG. 3 (1). Figure 2: Connect VOU'I'A and VINC to 0-2/3T and 5/3
They match above T, and differ between 2/3T and 5/3T. Circuit A is O≦L≦2×T/3.2×
T≦t≦8 X T/3.3×T≦t≦11 X T/
During period 3, switching transistor A is turned on.
Outputs a control signal to set the VOUTA signal to '0UT'
Transfer to A. Further, during the period T≦t≦5×T/3, a control signal for turning on the switching transistor D is output, and the signal of VINC is transferred to V'QUTA. Further, in the periods of 2/3T-T, 5/3T to 2T, . . . , the levels of 0 to 2/3T and T to 5/3T are maintained. As a result, at V'0UTA, a pulse signal having exactly the same timing as the delayed pulse signal when there is no defect in the shift register A is obtained as shown in FIG.

In addition, the test circuit is also -T/3≦ in the same way as the death I/circuit A.
t≦T/3.2 X T/3≦t≦4 X T/3.8
×T/3≦t≦], '0 in the period of OX T/3
Transfer UTB signal to v′OU′J”c d < 5 X
T/3≦L≦7
A control signal for transferring the TC signal to v'our'rc is output to the gates of switching transistors C and F. As a result, there is a defect in the shift register C as shown in FIG. i
: A pulse signal with exactly the same timing as the delayed pulse doubler is generated 7H. .

Next, the correct signal V that relieved the shift L-register defect.
'OU'l'A-V'0From UTC, control switch A-
V"0UTA-V"0U by C1,1,9-121
A scanning pulse signal of TC with a wide pulse width T/3 is extracted.

Furthermore, the dest circuits A, B, and C have a logical value of +1111.
VIN
C, VOUTA, VlOUTA or VOLITB-V'0
Be sure to set either UTB or VOUTC signal to '0UTA'
The switching transistors A and D, B, E, C and F are controlled to transfer , '0UTC'. Therefore, if the shift register is normal, even if there is a defect in the test circuit and outputs an error signal, the correct signal will always be V'0.
UTA, '0UTB, V'□Urrc'2 can be extracted.

With the above, /:, a 3-stage basic circuit is adopted and the 76400
A stage scanning circuit was actually fabricated by integrating poly-8i TFTs on a glass substrate. As a result, the yield was 95% (
4, and the yield was significantly improved by 5% compared to the conventional 40%.

(A result of the invention) If the scanning method and scanning fU-circuit of the present invention are applied to 1'J, as explained in '), the shift) register will be either one of the test circuits')5 It is possible to realize a scanning circuit that operates perfectly even if there are defects in the circuit. Sara(,
2. Defect relief method (since it is a self-repair type using a J logic circuit configuration, it does not require a defect detection circuit to find the defect location, and also requires extra steps such as defect relief by laser trimming. Me etc. 1..l,
l・￥4 more, all thin film LCD display R, Tomii”;
-(,):,) It is extremely effective for improving the accuracy of sensors, liquid crystal shutters, etc. (,rl).

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the scanning force method and scanning circuit of the present invention, and FIG. 2 shows a timing diagram of the scanning circuit.
FIG. 3 is a diagram showing the logic configuration and truth table of a test circuit, and FIG. 4 is a schematic diagram showing a conventional scanning circuit. In FIG. 1, 1.01, 102, 103... shift register, 1o-4, 105, 106... doors 1~
Circuit, 1.07.108.109...Invar, L
Lo, 111.112, II: (, 114, 115・
・・Switching to:/Jista, i, 1.6.117
．． 118・Lise, 71−Switch,]]9゜120, 1
21.-1: Ij control switch.

Claims (2)

[Claims] (1) In a method for driving a scanning circuit that sequentially selectively scans three or more capacitive loads, the first, second, third
The pulse signal is delayed and transferred by sequentially sending the phase by T/3 with a delay time of T (hereinafter, the transferred pulse signal is referred to as a delayed pulse signal), and the first, second, and third pulse signals are The signals obtained by delaying and transferring n times are respectively (3×n-2
)th, (3×n-1)th, and 3×nth delayed pulse signals, and if the rise time of the first pulse signal is t_0, then t_0+(3×m-3)×T/3≦ t≦(t_0
+(3×m-1)×T/3) When the logic level of the first delayed pulse signal and the logic level of the third pulse signal are equal to each other during period T_1, (t_0+(3×m-
2)×T/3)≦t≦(t_0+(3×m−1)×T/
3) is outputted as the first scanning pulse signal of the first delayed pulse signal during the period T_2, and during the period T_
1, when the logic level of the first delayed pulse signal and the logic level of the third pulse signal are different, the third pulse signal is output as the first scanning pulse signal in the period T_2; In the period T_1, when the logic level of the (3×n+1)th delayed pulse signal and the logic level of the 3×nth delayed pulse signal are equal, the (3×n+1)th delayed pulse signal in the period T_2. (3×n+1
)th scanning pulse signal, and the period T_1
When the logic level of the (3×n+1)th delayed pulse signal and the logic level of the 3×nth delayed pulse signal are different in T_2, the 3×nth delayed pulse signal is set to (3× (t_0+(3×m+p-2)×T/3)≦t≦(t_
In period T_3 of 0+(3×m+p)×T/3), (
When the logic level of the 3×n+p-1)th delayed pulse signal and the logic level of the (3×n+p-2)th delayed pulse signal are equal, (t_0+(3×m+p-1)×T/3) ≦t≦(t_
In period T_4 of 0+(3×m+p)×T/3), the (3×n+p-1)th delayed pulse signal is
+p-1)th scanning pulse signal, and in the period T_3, the logic level of the (3×n+p-1)th delayed pulse signal and the logic level of the (3×n+p-2)th delayed pulse signal. A scanning method characterized by outputting the (3×n+p-2)th delayed pulse signal as a (3×n+p-1)th scanning pulse signal in the period T_4 when the two are different from each other. (Here, m,
n is a natural number, p is 0 or 1) (2) In a scanning circuit that sequentially selectively scans three or more capacitive loads, delay circuits A, B, and C that respectively delay and transfer the first, second, and third pulse signals, and the delay circuit A;
Switching transistors A, B, and C transfer the output signals of B and C to delay circuits D, E, and F, respectively, and input signals of the delay circuits C, D, and E are transferred to the delay circuits D, E, and F. Switching transistors D, E, and F to be transferred, the input signal of the delay circuit C are used as the first input, the output signal of the delay circuit A is used as the second input, and the inverted signal of the output is sent to the switching transistor A. A dest circuit A which uses a control signal and an output as a control signal for the switching transistor D, an input signal of the delay circuit D as a first input, an output signal of the delay circuit B as a second input, and an inversion of the output. A test circuit B whose signal is a control signal of the switching transistor B, an output is a control signal of the switching transistor E, an input signal of the delay circuit E is a second input, and an output signal of the delay circuit C is a second input. a test circuit C whose input is an inverted signal of its output as a control signal for the switching transistor C and whose output is a control signal for the switching transistor F; and an inverter A for inverting the outputs of the test circuits A, B, and C, respectively. , B, C, and switching transistors G for initializing the control signals of the switching transistors A, B, C, D, E, and F, respectively.
The input signals of H, I, J, K, and L and the delay circuits D, E, and F are respectively (3×n-2)th, (3×n-1)th, and 3×nth scanning pulse signals. 1. A scanning circuit comprising control switches A, B, and C for taking out the data. (Here, n is a natural number)