JPH0362743A - Method and apparatus of power line carrier communication - Google Patents

Abstract

PURPOSE: To transmit measured energy consumption data by transmitting data in the form of the frequency hopping spectrum transmission and demodulation and making the encoded bits of logic 1 and logic 0 in frequency sequence in a single band. CONSTITUTION: A register 12 storing the reading of a meter in the form of several bits of digital words is provided and a microprocessor 14 receives each bit for transmission and converts each bit into the address of a memory 16 fixing a memory position storing the encoded frequency of a prescribed sequence to be generated by a frequency synthesizing part 18. The logic 1 and logic 0 bits are encoded in a series of four successive frequencies namely a 'hop'. A code sequence expressing the logic 1 and logic 0 bits is stored in the memory 16 and can be changed by programming. The frequency synthesizer 18 generates an individual frequency signal in response to an address sent to the address input.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates generally to power line carrier communications, and more particularly to a power line carrier communication method and apparatus using frequency hopping wideband signal modulation and demodulation. It is related to.

[Background technology]

In some types of communication networks, data stored on remote data storage units is downloaded to a central computer or record storage unit periodically or on demand. For example, in an electrical or other utility meter reading system (in which the present invention is particularly advantageous, but not necessarily limited to), a remote integrating electricity meter is read by a central computer that reads customer electricity for billing purposes. Maintain consumption records.

Typically, one central meter for each household or apartment building occupied by multiple families and for each single-tenant or multi-tenant commercial property was read by a central computer. It would be preferable to monitor the electricity consumption of each user rather than a group of users to create a more fair and personalized bill. However, it is often impractical to install individual meters in individual units, especially older apartment buildings. This is because there are typically no separate data communication lines between each unit and the central site. Rewiring the building is prohibitive due to cost. therefore,
The meters transmit electricity consumption data to a central computer using a power line provided for each unit and to which all meters are connected. This is done by a transmitter located at each meter. This transmitter injects a carrier signal into the power line modulated with data identifying the meter and reports electricity consumption within a given billing period.

However, power lines are electrically noisy and it is difficult to establish a reliable communication link between the meter and the central computer using a correspondingly small amount of signal power. Furthermore, the power line noise spectrum 8 changes over time of day and seasonally, depending on the operation of electrical equipment connected to or near the power line. For example, power line network characteristics have attenuation variations as a function of frequency, with significant reductions in the transmission of certain frequencies that vary throughout the network. Noise injected into the power line includes, for example, constant frequency noise resulting from switching of inductive loads. Other noise comes from the frequency tuning of the network, including Gaussian background noise and fluctuating signals caused by things like televisions operating on power lines.

To improve the reliability of data communications over power lines, broadband transmission of digital information has been implemented using broadband signal processing techniques such as "frequency hopping." Here, each of the logic 1 and logic O bits 1 through 1 is encoded into multiple frequency elements or "hops J" (sometimes referred to as "chips") within two frequency bands. This method is Ga1
No. 4,763,103 to Ula et al. As described in this patent, during transmission, each information element to be transmitted 9 is encoded by a sequence of several different predetermined encoding frequencies.

Here, one sequence represents a logical 1 bit and another sequence represents a logical O bit 1-. These two frequency sequences are in two different bands of frequencies separated from each other.

Within two sequences, signals of the same rank, i.e.
The same frequency locations must be different from each other to maintain a detectable difference between logic 1 sequences and logic O sequences. These sequences are demodulated at a receiver coupled to the power line by correlating with locally generated signals. These signals, with a more or less constant frequency deviation, create a special frequency combination, and the value of the information element is determined as a function of the correlation output.

Although largely satisfactory, this Ga1ula et al. device is relatively complex, has to limit the choice of frequencies for generating sequences, and under certain circumstances can misinterpret the received pips. Possibility: 0. The complexity is a result of heterogain signal demodulation, which requires intermediate frequency conversion and amplification prior to the correlation operation. Frequency selection is limited to two types of frequencies within the band. The signal components occupying one band are sent to one demodulator, the other signal components representing the IT range are sent to the other demodulator, and as mentioned above, at least the corresponding components in the two bands Since the frequencies of the ranks must not be the same, the frequencies cannot be selected arbitrarily. Finally, the correlation determination made in Ga1ula et al. is based on whether the energy content following receipt of each "chip" is above or below a predetermined threshold value. The values of the bits that occur can be ambiguous and the number of decisions that allow one bit value or the other can depend on the precision of the threshold if it is approximately half the total number of chips per bit. Therefore, it may be advantageous or necessary to limit the number of frequencies or "chips" forming the bits to those of an odd number of frequencies. If this is the case, this determination may erroneously identify a logic 1 bit or logic 0 bit as noise.

An overall object of the present invention is to provide a power line carrier communication device.

This and other objects provide an apparatus for broadband transmission of data in a power distribution network, the apparatus comprising at least one coded signal corresponding to a logic 1 bit and a logic O bit, respectively.
In a device containing one transmitter. Each encoded signal corresponding to a logical 1 bit consists of a first predetermined unrelated frequency sequence and each encoded signal corresponding to a logical 0 bit consists of a second different predetermined unrelated frequency sequence. The output of the transmitter is coupled to a power distribution network, and at least one receiver coupled to the power distribution network receives an input encoded signal from the transmitter.

According to one embodiment of the invention, the receiver has a first dc signal corresponding to a logical 1-bit signal on at least the first frequency channel.
a first demodulator for converting the logic 0 bit signal into a corresponding second dc signal into at least a second frequency channel; 2 includes an offset correction circuit that corrects for offset voltages generated as a result of component offsets in 2.

A comparator is provided which compares the output signals from the first and second channels to indicate whether it is a logic 1 bit or a logic O bit.

According to a more particular embodiment of the invention, the receiver includes a hemodyne demodulator system including a first demodulator with first and second channels for demodulating a logical 1-bit signal. In the first channel, a first local signal generator generates a first reference signal that is a replica of the encoded logic 1-bit signal, and a first multiplier multiplies the input encoded signal and the I-th reference signal. a first filter is coupled to the output of the first multiplier to pass substantially only a first dc component therefrom, and a first squaring circuit is connected to the first dc component. d
The c component is squared. In the second channel, a first local signal generator generates a second reference signal that is a replica of the encoded logic 1-bit signal in quadrature, and a second multiplier combines the input encoded signal and the second 3 a second filter is coupled to the output of this second multiplier to pass substantially only a second dc component therefrom; A circuit is adapted to square the second dc component. A first adder is provided to add the outputs of the first and second squaring circuits, and a first integrator is provided to add the outputs of the first and second squaring circuits.
Accumulating an output signal from the adder corresponding to the first frequency sequence.

The receiver further has third and fourth channels.
A second demodulator is included for demodulating the logic O-bit signal. In the third channel, a third local signal generator generates a third reference signal that is a replica of the encoded logic O-bit signal, and a third multiplier multiplies the input encoded signal and the third reference signal. A third filter is coupled to the output of the third multiplier to pass substantially only the third dc component therefrom, and a third squaring circuit squares the third dc component. It is supposed to be done. In the fourth channel,
A fourth local signal generator generates a fourth reference signal in quadrature that is a replica of the encoded logic O-bit signal, and a fourth multiplier generates the product of the input four encoded signal and the fourth reference signal. A fourth filter is coupled to the output of the fourth multiplier to pass substantially only the fourth dc component therefrom, and a fourth squaring circuit divides the fourth dc component. It's supposed to be squared. A second adder is provided to add the outputs of the third and fourth squaring circuits, and a second integrator accumulates the output signal corresponding to the second frequency sequence from the second adder. The integration times of the first and second integrators are equal to the number of sequences forming one bit. A comparator is provided which compares the output signals from the first and second integrators to indicate whether it is a logic 1 bit or a logic 0 bit.

This comparator thus makes a bit decision based on all the "hops" of the sequence that make up one bit, rather than comparing the energy content independently from successive hops in logic 1 bits, logic 0 bits. Establish.

According to another aspect of the invention, an offset correction circuit corrects the receiver for any error voltages occurring as a result of receiver component offsets. Preferably, the offset correction circuit includes circuitry that shunts the input of the receiver to provide a "zero input" so that the output voltage developed at the receiver is solely from the offset voltage developed therein. . This offset is then calculated by the microprocessor and offset correction is performed by the rough 1-ware.

According to another aspect of the invention, both the receiver and the transmitter of the device are synchronized with the electricity of the electrical grid. Preferably, the synchronization circuit within the device is synchronized to the electrical zero-crossings of the power grid and includes a zero-crossing detector that generates line synchronization pulses. A phase-locked loop controls the generation of encoded signals by the transmitter in response to the line sync pulse.

According to another aspect, a limiter circuit is provided that limits the input signal applied to the receiver. A transformer couples the encoded signal from the power grid to the receiver, and a bandpass filter between the transformer and the receiver limits the frequency range of the input signal.

According to yet another aspect of the invention, the transmitter includes a frequency synthesizer that generates logic G 1 and logic 0 encoded signals, respectively. On the receiver side, a front-end demodulation operation is performed in hardware, and the remainder of this demodulation operation is implemented in software.

According to the method of the invention, broadband pig transmission in the power distribution network is
This is implemented by generating encoded signals corresponding to a logic 1 bit and a logic O bit, respectively. here,
Each encoded signal corresponds to a logical 1 bit of a first predetermined unrelated frequency sequence, and each encoded signal corresponds to a logical O bit of a second different predetermined unrelated frequency sequence. The encoded signals are combined in the electrical grid,
An input encoded signal on a power distribution network is received.

According to the present invention, the receiving operation establishes first and second frequency channels for demodulating the logical 1-bit signal and third and fourth channels for modulating the logical O-bit signal by '4X. It includes the actions to do.

In the first channel, a first reference signal, which is a replica of the encoded logic 1-bit signal, and a first product signal, which is the product of the input code signal and the seven first reference signals, are generated.

The first product signal is filtered to pass substantially only its first dc component and squared to obtain a first output signal. Second
In the channel, a second local signal, which is a replica of the encoded logic 1-bit signal in quadrature, and a second product signal, which is the product of the input encoded signal and the second reference signal B, are generated. The second reference signal is filtered so that substantially only its second dc component is passed and squared to obtain a second output signal. Third
In the channel, a third reference signal, which is a replica of the encoded logic 0-1 signal, and a third product of the input encoded signal and the third reference signal are generated. the third reference signal is filtered;
Substantially only the third dc component is passed and squared to obtain the third output signal. Finally, on the fourth channel,
A fourth reference signal is generated which is a replica of the encoded logic OPI signal in quadrature and a fourth product of the input encoded signal and the fourth reference signal. the fourth reference signal is filtered;
Substantially only the 4th dc)j2 minutes are passed, and the 4th
squared to obtain the output signal.

8 The first and second output signals are summed to obtain a first summed output signal corresponding to the first frequency sequence;
, a fourth output signal is also summed to obtain a second summed output signal corresponding to the second frequency sequence. The first summed signal is integrated to obtain a first integrated output signal, and the second summed signal is integrated to obtain a second integrated output signal. Finally, the first and second integrated output signals are compared with each other to indicate whether it is a logic 1 bit or a logic 0 bit.

Other objects and advantages of the present invention will be appreciated by those skilled in the art.
It will be easily understood from the detailed description below. Only the preferred embodiments of the invention are shown and described herein to illustrate the best mode for carrying out the invention. It will be obvious that the invention is capable of other different embodiments and its several details may be changed in various obvious forms without departing from the invention. therefore,
The drawings and description are intended to be illustrative in nature and not in a limiting sense.

EXAMPLE 9 Referring to FIG. 1, a non-limiting environment to which the present invention is applicable includes an apartment building B having a number of individual bays as shown;
Each section has one set of power lines P common to each power company.
Electricity is supplied via L. Distributed over the power supply line PLj and placed in each section is a power meter EM that monitors and accounts for the power consumption of each section.

Periodically or on demand, the power meter EM is polled by a centrally located building control unit ECU in the pilling B.

This control unit comprises or includes a local computer, which may be a "personal computer", which is connected to the modem PLM on the power line, and is connected to the ECU and the power line PLM.
A modulated gear rear signal is connected between the terminal and f7. Each wattmeter EM also includes a modem and line interface to allow direct two-way communication between the EM and the ECU over the power line when the EM and BCU are on a common power transformer; Or these two are separate transformers.
In the second case, two-way communication is possible between the EM and the BCU via another F, M or PLM used as a bridge.

Systems are known for scheduling polling between BCUs and power meters EM and for determining communication routes between all power meters EM and BCUs, either directly or via intermediate meters. A self-learning system that optimally performs this routing is described in "Network Routing and Learning Method for Electricity Carrier Communications," filed April 27, 1989, and assigned to the assignee of the present invention.
g and Learning Strategy for
r Power Carrier Communica
tions) J. The present invention relates to an improved frequency hopping distributed spectrum power line carrier communication system that is easy to implement and has very low bit error rates even in the presence of significant electrical noise on the power line.

Inside each wattmeter 8M is a transmitter of the type shown at 10 in FIG.
= and within the PTM is a receiver of the type shown at 30 in FIG. 4 connected to the power supply line. Preferably, each wattmeter EM includes a receiver 30 and each PLM preferably includes a transmitter 10, so that communication routing can be carried out as disclosed in the said patent application. .

Each transmitter 10 shown in FIG. 3 is equipped with a register 12 which stores the information to be transmitted, for example the reading of a meter (not shown), in the form of a digital word of several bits. Microprocessor 14 receives each bit for transmission and converts each bit into an address in memory 16 that defines a memory location storing a predetermined sequence of coded frequencies to be generated by frequency synthesis section 18. A first predetermined frequency combination is used to code a logic 1 bit, and a second predetermined frequency combination is used to code a logic 0 bit. For each bit, the signal generated by the summarizing section 18 takes the form of a series of frequency bursts whose frequency changes step by step periodically during the transmission of that bit, and is transmitted by the synchronization unit 20 onto the power line. Synchronized to power.

An example of successive frequency values used to encode logic 1 and logic O bits is shown in FIG. 2(a). In this example, the logic 1 and logic 0 bits are encoded as a series of four summative frequencies or "hops" (sometimes referred to as "'chips"). Here, logic 1
The bits are in the sequence F11, F12, F1a and F14
These four hops are synchronized to the half cycle of power on power line PL as shown on the horizontal axis of the graph. Similarly, the power synchronized logic 0 bit on line P1 consists of the sequence FOI, FO2, F03 and FO4. The number of hops that form each bit is arbitrary; a larger number of hops per bit reduces the error rate but increases the required processing speed and complexity of the transmitter and receiver circuits.

3 The selection of the frequencies forming the hops is also arbitrary, but in order to improve the synchronization between the transmitter and receiver, the sequence between the coded logic 1 bits and the logic 1 bits may be It is preferable to keep the difference large. Therefore, it is preferable to code the bits such that the frequencies within corresponding hops, ie logical 1 and logical 0 bits of a common rank, are different from each other. Further, it is preferable to separate the frequencies from each other by a multiple of 120" ntlz if the number of hontubes per bit is n. In the example shown in FIG. 2(a), 5
The hops fall within a frequency band bounded by 0 and 150 KHz, and the baud rate is 120 bps.

Another example of successive frequency values used to encode bits is shown in FIG.
l, F 1-2, F1a and F14, and the same frequency sequences in quadrature, Fol, FO2,
FO3 and FO4 form a coded logic 1 bit. In other words, the frequency of the first hop (Fll, ) in the logical 1-bit sequence is equal to the frequency of the third hop (FO3) in the logical 1-bit sequence, and similarly the frequency of the second hop (Fll, ) in the logical 1-bit sequence is F12) is the frequency of the fourth hop (FO4) of the logical O bit sequence.
) is equal to the frequency of The same relationship is maintained for the remaining hops of the two sequences. In this example, the hops are again in the band bordering 50 and 150 KHz, and the transmission is 120 bps.

An important effect of the encoding shown in FIGS. 2(a) and 2(b) is that the encoded logic 1 and logic O bits are integrated in a common band, i.e. the frequencies of the two sequences are relative to each other. It is about overlapping. This provides greater flexibility than the Galula et al. patent.

Referring again to FIG. 3, code sequences representing logic 1 and logic 0 bits are prestored in memory 16 and can be changed by programming. The addresses stored in the memory 16 corresponding to the two sequences are sent to the address input of the conventional frequency platform 5 stratification 18. Frequency synthesizer 18
produces a coded logic 1 bit and a coded logic 0 bit. Microphone 11 Prosens°14
controls the code that needs to be sent to the frequency synthesizer depending on what is in memory 18 and by the logical bits that should be sent over the line.

The output of the combiner is amplified in an amplifier 24 and passed through a line interface transformer L1 to the power supply line PL.
is injected into.

Frequency synthesizer 18 generates individual frequency signals in response to an address, eg, an 8-bit word, sent to its address input. Thus, to generate a coded logic I or logic 1 bit, the frequency synthesizer receives a series of words corresponding to hops of the form PI. Frequency synthesizer 18 may be software or firmware preferred.

In the case of a transmission defect of the type where the frequency synthesizer 18 "latches on", the entire communications network will become inoperable due to the continuous carrier injection into the power supply line by the inoperable unit. be done.

Inoperability results from either hardware or software/firmware errors. In either case, a watchdog timer 26 monitors the output of frequency synthesizer 18 to avoid this defective mode.

Each time frequency synthesizer 18 generates a sequence, watchdog timer 26 measures the duration of the sequence. If the measured time duration exceeds the predetermined sequence duration,
The synthesizer operation is assumed to be incomplete and the watchdog timer 26 resets the synthesizer. This causes the transmission of the carrier by the transmitter 10 to be terminated until another transmission cycle occurs.

Referring to FIG. 4, a receiver 30 in each wattmeter EM connects power line P to line interface transformer L1.
Monitor L. The signal detected by this transformer is sent to a bandpass filter 32, which minimizes the amount of noise detected on the power line by limiting the frequency of the line signal to be processed in the receiver. .

7 For example, the bandpass filter 32 may
an upper band that primarily attenuates the network frequency and its harmonics and exceeds the highest coding frequency used;
For example, it is preferable to limit it to about 100-150 KIIz. The output of the filter 32 is amplified 111 by an amplifier 34.
and is adjusted by limiter 36 to reject signals detected on the power line that exceed the normal operating range of the receiver.

The output of limiter 36, labeled AA in FIG. expressed.

a 9 cos (wilt + phi) (1) No FAA forms the input of a homodyne demodulation circuit according to the present invention to accurately detect logic 1 and logic O bits received by receiver 30. This demodulator, designated generally by the number 38, has four frequency channels 38(a).
, 38 (b), 38 (c) and 38 (d). Within each channel, the input channel at AA is multiplied by a reference signal generated by the local signal generator shown in FIG.

A first multiplier 40(a) in channel 38(a) multiplies the input signal at node AA by a first locally generated reference signal cos (wilt) corresponding to frequencies forming a logic one sequence. Multiply. This frequency sequence is generated by frequency synthesizer 51(a) of FIG. 5 and appears at the receiver. Therefore, the first channel 38
The output of multiplier 40(a) appearing on line A1 in (a) is as follows.

2 ・cos (will → phi) ・co
s(iyllt) (2) Channel 38
(The second multiplier 40(b) in bJ receives the input signal of no FAA and the second
The second reference signal is therefore a replica of the first reference signal and is in quadrature with it. Therefore, the second multiplier 40 appearing on line A2 of the second channel 938 (b)
The output of (b) is as follows.

a -cos (wllt + phi) ・si
n(will) (3) Similarly, the multiplier 40
(The third and fourth reference signals sent to c1 and 40(d) correspond to a logical O sequence of frequencies. Therefore, the third and fourth reference signals in channels 38(c) and 313(d)
and the fourth reference signal are cos (i101t) and sin (wolt), respectively. These are all generated by the frequency synthesizer 51(b) in FIG. The fourth reference signal in channel 38(d) is a replica of the third reference signal in third channel 38(c) and is in quadrature therewith.

The four reference signals generated by frequency synthesizers 5Ha) and 51(b) (FIG. 5) are controlled by a microprocessor 52, which includes a zero-crossing detector for synchronizing a phase-locked loop 56. 54 to the power on the power line.

Zero-crossing detector 54 and phase-locked loop 56 are well known to those skilled in the art and will not be described in detail here. The reference signal in quadrature phase is passed through phase shifter 5 as shown here.
8(a) and 58(b) from the signals of the other channels.

The signals on lines A3 and A4 are each as follows.

a-cos (wilt 4 phi) ・c
os(wllt) (4)a-cos
(wilt + phi) ・sin(wilt)
(5) Each of the above equations (2) to 5) can be expanded as follows.

a/2 ・(cos (2wll t+phi) t+
cos (phi)) a/2 ・(sin(2wllt
+phi)t+5in(phi))a/2 ・(cos
[(wll+w01) t+phi]+cos[(w
ll-prisonQl)t+phil) a/2 ・(sin [(wllllwol) t+ph
i]+sin[(wll-wol) t+phil)(
8) (9) Life B of four channels 3 B (a) - (d)
The 1-B4-hi signals are sent to the low pass filters 42(a)-42(d) to pass only the DC component. Therefore, the AC component of equations (6)-(9) is removed and the equation 00
) −(I+) are each as follows.

a/2 ・(cos(phi)) a/2 ・(sin(phi)) From equation (to)-(13), the side wave 11F of the input signal going to AA is channel 38(a) and 38( b) applied to lines B1 and B2 or channel 38
(c) and 38 (d) on lines B3 and B4 based on whether an encoded logic 1-bit signal or an encoded logic O-bit signal is received. I can do it. Line Bl
The signals on lines B3 and B2 are in quadrature with each other, and similarly the signals on lines B3 and B4 are in quadrature with each other.

The outputs of the low-pass filters 42(a)-(d) are sent to respective square circuits 44(a)-(d) on lines C1
, C2, 2 The signals on C3 and C4 are each (a/2)cos(phi
), (a/2)cos(phi), O and 0.

The outputs of squaring circuits 44(a)-(d) are then sent to first and second adders 46(a) and 46(b).

In particular, the first and second channels 38(a) and 3B
The outputs of square circuits 44 (a) and 44 (b) in (b) are added together at 46 (a) and on line D1
．． The signal on 2 becomes as shown in equation 04).

a/4(cos2(phi)+5in2(phi))-
a/4 G(1) is cos2(phi)→5in2(phi)=1
05) That's why.

Similarly, the outputs of square circuits 44(c), 44(d) are 4
6(b) and the signal on line D3.4 becomes as shown in 204).

0ω Therefore, the signal on output line DI,2 or output line D3.4 will be C2 depending on whether a logic 1 bit is received by the receiver 30 or a logic 1 bit is taken by the receiver 30. .

Therefore, if a logic 1-bit signal is received, a DC signal of magnitude 8/4 applied on line D1.2 is integrated in the integrator circuit 48b, contributing to noise on the other output line D3.4. The above signal is sent to integrator 48(b). The integration period of integrators 48(a) and 4B(b) is equal to the number of hops per bit, for example 4 in the example shown in FIGS. 2(a) and 2(b). The output of the integrator appearing on output lines El,2 and C3,4 is fed to the input of a comparator 50, which comparator determines whether a logic 1 pip 1- signal or a logic O bit signal is received on output line F. A signal is given to indicate whether the

Therefore, comparator 50 determines that the signal accumulated on channels 38 (a) and 3B (b) during the pip 1-sequence is equal to (ij') on channels 3 B (c) and 38 (d).
”: Determine whether the received bit is greater or less than 4. If its magnitude is large, the received bit is considered to be a logical 1, for example, and if its magnitude is small, the received bit is considered to be 4. In this case, it is considered to be a logic 0 pin 1-.

Of particular importance to the invention is that the bit determination is not made by comparing the energy contained in the channel pairs of GJ, logic 1 bit and logic 1 bit, but rather the signals on output lines D1.2 and C3,4. The magnitude of is added through all hops of the bit sequence and a bit decision is made. In the example of FIGS. 2(a) and 20), bit decisions are made for every four-hop sequence. This technique eliminates the ambiguity in bit determination inherent in the Gurara et al. patent.

In more detail regarding the bit decisions, the circuit of FIG. 4 compares the sum of four samples on each output line E1.2 and C3,4. The difference is determined in comparator 50, and if the difference is greater than that attributable to noise, a logic 1 bit or logic O bit decision is made.

The level of noise 5, which forms the calibration reference for receiver 30, is determined by the usual Hose, which can conveniently be chosen to be equal to 1 hour. The noise on lines E1.2 and 17.3.4- is in the form of a DC signal provided as an offset voltage due to voltage variations within the components of receiver 30. The Offsen I detection and correction circuit shown in FIG. 6 for reducing the magnitude of this offset voltage includes a first controlled switch 60 in shunt with the input of the receiver 30. At the beginning of the calibration cycle, switch 60 is closed, connecting the input of receiver 30 to ground, so that the DC output level from the receiver is due only to noise.

This DC level is stored in the microprocessor 62,
Thereafter, during receiver operating mode, microprocessor 62 subtracts this stored offset from the signal output of receiver 30. Therefore, offset compensation is performed as each bit is received.

According to another embodiment of the invention, the receiver 30' shown in FIG. 7 has a demodulation section implemented at least partially in software or firmware. In this case, microprocessor 62' is programmed to perform at least the functions of squaring circuit 44, adder 46, integrator 48, and comparator 50. Microprocessor programming for implementing the functions of these circuits is well known to those skilled in the art, as noted above.

2. A power line carrier communication system particularly suitable for transmitting energy consumption measurement data for power company billing, wherein the data transmission is in the form of frequency pumped spectrum transmission and signal demodulation. A power line carrier communication system has been disclosed in which the encoded bits of logic 1 and logic O are integrated into a single band to form a frequency sequence. The demodulation is
This is done by a non-coherent homodyne quadrature demodulator which converts the modulated carrier to its corresponding DC level without intermediate frequency conversion.

Voltage offsets that characteristically induce errors in homodyne demodulators are compensated for by a calibration circuit, and by integrating frequency hops through the bit sequence before making decisions, the bit error rate is considerably lower than in the known case. Become.

Although only preferred embodiments of the invention have been illustrated and described herein, it will be appreciated that the invention may be used in other combinations and environments and that various modifications may be made within the scope of the invention. It is understood that changes and modifications may be made.

[Brief explanation of drawings]

FIG. 1 shows a number of individual compartments each having an energy meter on the distributed power line and a building control polling the energy make to accumulate individual energy consumption data for billing or other purposes. FIG. 2(a) is an example of a combination of coding sets of logic 1 and logic O bits using two different frequency sequences; FIG. ) The diagram shows the logic l and logic o bits using the same sequence of quadrature 8 phases to represent the two bits.
Another example showing a coding frequency combination of -, FIG. 3 shows that in the system shown in FIG.
b) A simplified block diagram of a transmitter provided in accordance with an aspect of the invention for generating the coded frequency combination set of FIG. FIG. 5 is a block diagram illustrating a receiver for non-coherent homodyne demodulation of an encoded carrier signal, which generates the four reference signals shown in FIG. FIG. 6 shows a circuit for synchronizing to the above zero crossing, FIG. FIG. 7 is a circuit diagram of a receiver with demodulation functionality implemented in software. PL...Power line EM...Power meter BCU...
・Building controller 1 - Roll unit 9 L M... Power line 0... Transmitter 2... Register 6... Memory 0... Synchronous unit Modem 30... Receiver 14... Microprocessor 18 ... Frequency synthesizer 1~0 Engraving of drawings (no change in content) 111 --- Fuu Ding OUTILITYP 71 Procedural amendment (method) 1. Indication of case 1990 Patent Application No. 1 1603 No. 2, Name of the invention: Method and apparatus for power line carrier communication 3, Person making the amendment Relationship to the case Applicant 4, Agent

Claims (1)

[Scope of Claims] (1) An apparatus for broadband transmission of data in a power distribution network, comprising at least one transmitter including means for generating coded signals corresponding to a logic 1 bit and a logic 0 bit, respectively. transmission in which each encoded signal corresponding to a logical 1 bit consists of a first predetermined unrelated frequency sequence and each encoded signal corresponding to a logical 0 bit consists of a second different predetermined unrelated frequency sequence. at least one receiver having a homoturn non-coherent demodulator and means for receiving an input encoded signal on the power distribution network from the at least one transmitter; and the demodulator includes: (a) first demodulator means having first and second channels for demodulating the logical 1-bit signal; , the first demodulator means comprising: (i) first logic signal generator means for generating on the first channel a first reference signal that is a replica of the encoded logic 1-bit signal; first multiplier means for producing the product of the reference signal and the first reference signal; and substantially only one first dc component coupled to one output of the first multiplier means; and first squaring means for squaring the 1 dc component; second logic signal generator means for generating a second reference signal; second multiplier means for generating a product of said input encoded signal and said second reference signal; Combined, there is only one d
a second filter means that allows only the c component to pass;
a second squaring means for squaring the dc component; a first adder means for adding the outputs of the first and second squaring means;
first integrator means for accumulating a first output signal corresponding to the first frequency sequence from the converter means; (b) the demodulator includes second demodulator means; a third, wherein device means demodulates the logic zero bit signal;
a fourth channel, the second demodulator means further comprising: (i) generating a third reference signal on the third channel that is a replica of the encoded logic zero bit signal;
logic signal generator means, said input encoded signal and said third
third multiplier means for producing a product of the reference signals; and a third filter coupled to one output of the third multiplier means for substantially only passing a third dc component therefrom. and third squaring means for squaring the third dc component;
fourth logic signal generator means for generating a reference signal of; and fourth logic signal generator means for generating a product of said input encoded signal and said fourth reference signal.
multiplier means; fourth filter means coupled to one output of the fourth multiplier means for passing substantially only a fourth dc component therefrom; fourth squaring means for squaring the components; second adder means for summing the outputs of said third and fourth squaring means; and a second frequency sequence corresponding to said second frequency sequence from said second adder means. (c) further comparing the output signals from said first and second integrator means to indicate whether they are a logic 1 bit or a logic 0 bit; Comparator means (2) Apparatus according to claim 1, characterized in that said at least one
Apparatus according to claim 1, characterized in that it includes synchronization means for synchronizing two receivers with said at least one transmitter. (3) The apparatus according to claim 1, wherein the at least one
A device according to claim 1, characterized in that one receiver and the at least one transmitter are synchronized to the electricity of the power distribution network. 4. The apparatus of claim 3, wherein said synchronization means includes zero-crossing detector means synchronized to zero-crossings of said electrical grid for generating line synchronization pulses. 5. The apparatus of claim 4 including a phase-locked loop for controlling said encoded signal generating means in response to said line synchronization pulse. 6. The apparatus of claim 1, further comprising limiter means for limiting said input signal applied to said receiver. 7. The apparatus of claim 1, further comprising transformer means for coupling said encoded signal from said electrical grid to said receiver, and further comprising a bandpass filter between said transformer and said receiver. A device characterized by: (8) The apparatus according to claim 1, wherein the coded signal generating means includes first and second frequency synthesizers that generate the logic 1 coded signal and the logic 0 coded signal, respectively. device to do. 9. The apparatus of claim 1, wherein each of said sequences consists of four frequency "hops." (10) The apparatus according to claim 9, wherein the first and second
An apparatus characterized in that the integration time of each of the integrator means is four said "hops". 11. The apparatus of claim 1 including offset correction means for correcting said receiver for error voltages generated as a result of receiver component offsets. (12) The apparatus according to claim 11, wherein the offset correction means shunts the input of the receiver to provide "
means for generating a zero input so that the output voltage produced by said receiver is solely due to the offset voltage produced therein; and means for latching said output offset voltage; and responsive to said latching means. and means for correcting the output of the receiver. (13) A method for broadband transmission of data in a power distribution network, the step of which is to generate coded signals corresponding to a logical 1 bit and a logical 0 bit, each coded signal corresponding to a logical 1 bit being 1 predetermined unrelated frequency sequence, each encoded signal corresponding to a logical 0 bit consisting of a second different predetermined unrelated frequency sequence; and combining the encoded signals on the electrical grid. and receiving an input encoded signal on the electrical grid, the receiving step comprising: (a) first and second frequency channels for demodulating the logic 1 bit signal and the logic 0 bit signal; (b) in said first channel, said encoding logic 1;
generating a first reference signal that is a replica of the bit signal;
a first signal that is the product of the input encoded signal and the first reference signal;
(c) generating a product signal, filtering the first product signal to pass substantially only a first dc component thereof, and squaring the first dc component to obtain a first output signal; generating in a channel a second reference signal that is a replica of the encoded logic 1-bit signal in quadrature, producing a second product signal that is the product of the input encoded signal and the second reference signal; filtering the double product signal to pass substantially only its second dc component;
squaring the dc component to obtain a second output signal;
) generating in the third channel a third reference signal that is a replica of the encoded logic 0 bit signal and producing a third product signal that is a product of the input encoded signal and the third reference signal; filtering the third product signal to pass substantially only its third dc component and squaring the third dc component to obtain a third output signal; (e) in quadrature in the fourth channel; generating a fourth reference signal that is a replica of the encoded logic 0 bit signal, generating a fourth product signal that is a product of the input encoded signal and the fourth reference signal, and filtering the fourth product signal. to allow substantially only the fourth dc component to pass through the fourth dc component.
(f) squaring the dc component to obtain a fourth output signal;
(g) summing the first and second output signals to obtain a first summed output signal corresponding to the first frequency sequence; and (g) summing the third and fourth output signals to obtain the second summed output signal. (h) integrating the first summation signal to obtain a first summation output signal; (i) integrating the second summation signal to obtain a first summation output signal; (j) comparing the first and second integral output signals to obtain a logical 1;
a bit or a logical 0 bit. 14. The method of claim 13, further comprising the step of synchronizing the transmitting and receiving steps. 15. The method of claim 14, wherein said synchronizing step includes synchronizing a transmitting step and a receiving step to said electrical grid electricity. 16. The method of claim 14, wherein the synchronization step includes a zero-crossing detection step synchronized to electrical zero-crossings of the electrical grid to generate line synchronization pulses. 17. The method of claim 16, including the step of controlling said coded signal generation step using said line sync pulse. 18. The method of claim 17, further comprising the step of limiting the magnitude of the input encoded signal. (19) The method of claim 14, comprising the steps of combining the encoded signals from the power distribution network and bandpass filtering the combined encoded signal from the power distribution network. how to. (20) The method of claim 14, wherein the encoded signal generation step includes the step of generating first and second frequency synchronization signals corresponding to the logic 1 and logic 0 encoded signals, respectively. A method characterized by: 21. The method of claim 14, wherein each of the sequences consists of four frequency "hops." 22. The method of claim 21, wherein the integration time of each of the first and second integration stages consists of four of the "hops." (23) A device for wideband data transmission over a power distribution network, which is a means for generating encoded signals corresponding to a logical 1 bit and a logical 0 bit, in which each encoded signal corresponding to a logical 1 bit is a first predetermined unrelated frequency sequence, each encoded signal corresponding to a logical 0 bit being a second predetermined unrelated frequency sequence;
at least one transmitter comprising means consisting of different predetermined unrelated frequency sequences of; means for combining the encoded signals on the electrical grid; means for receiving the input encoded signal;
at least one homodyne demodulator comprising first demodulator means for converting to a dc signal and second demodulator means for converting the logical zero signal to a corresponding second dc signal, the second demodulator being disposed in a second frequency channel means. one receiver, offset correction means for correcting said receiver for error voltages generated as a result of receiver component offsets, and comparing output signals from said first and second channel means to determine whether a logical one bit or and comparator means indicating a 0 bit. 24. The apparatus of claim 23, wherein the offset correction means shunts the input of the receiver to produce a "zero input" thereon, such that an output voltage produced by the receiver is produced therein. 1. A device comprising: means for latching said output offset voltage; and means for correcting said receiver output in response to said latching means. (25) The apparatus of claim 24, wherein the input shunting means includes a first switch, and the offset correction means further comprises differential amplifier means and an uncompared output voltage from the receiver. Apparatus characterized in that it includes second switch means for feeding the output of said latch means to one input of said differential amplifier means and third switch means for feeding the output of said latching means to another input of said differential amplifier means. 26. The apparatus of claim 23, wherein the first demodulator means has first and second channels for demodulating the logical 1-bit signal, and wherein the first demodulator means (i
) a first logic signal generator means for generating in said first channel a first reference signal which is a replica of said encoded logic one bit signal; and a product of said input encoded signal and said first reference signal. first multiplier means for generating;
first filter means coupled to one output of the multiplier means for passing substantially only a first dc component therefrom; and first squaring means for squaring said first dc component. and further comprising: (ii) second logic signal generator means for generating in said second channel a second reference signal that is a replica of said encoded logic 1-bit signal in quadrature; and said input encoded signal; a second multiplier means for producing a product of said second reference signal; a second multiplier means coupled to one output of said second multiplier means for passing substantially only one dc component therefrom; 2 filter means;
a second squaring means for squaring the second dc component; and a second squaring means for squaring the second dc component;
, first adder means for summing the outputs of the second squaring means;
first integrator means for accumulating a first output signal corresponding to the first frequency sequence from the first converter means; and further, the second demodulator means demodulates the logic zero bit signal. the second demodulator means having a third channel and a fourth channel, the second demodulator means further comprising: (i) providing a third channel, a replica of the encoded logic zero bit signal, to the third channel;
third logic signal generator means for generating a reference signal; third multiplier means for generating a product of said input encoded signal and said third reference signal; coupled to one output of said third multiplier means; (ii) third filter means for substantially passing only a third dc component therefrom; and third squaring means for squaring the third dc component; , fourth logic signal generator means for generating a fourth reference signal that is a replica of said encoded logic zero bit signal in quadrature, and a fourth logic signal generator means for generating a product of said input encoded signal and said fourth reference signal. multiplier means; fourth filter means coupled to one output of the fourth multiplier means for passing substantially only a fourth dc component therefrom; fourth squaring means for squaring the components; second adder means for summing the outputs of said third and fourth squaring means; and from said second adder means a second frequency sequence corresponding to said second frequency sequence. second integrator means for accumulating the output signal. (27) In the apparatus according to claim 26, at least the first to fourth squaring means, the first and second adding means, the first and second integrating means, and the comparator means are realized by software. A device characterized by: