JPH0362129A - Instruction decoding device - Google Patents

Abstract

PURPOSE:To eliminate waste by providing newly a means which sends an instruction in a 2nd instruction register to a 1st register. CONSTITUTION:One instruction is held in each of buffers IBR1 - IBR4. An aligner 116 sends the instructions in the IBRs and following instructions, and selectors 122 and 124 select decoders 138 and 140. The decoders decode the instructions and an instruction decoding and reading, and end decision circuit 180 controls the selectors 122 and 124 to control the aligner 116 through an IR state update circuit 166. When the decoding of only a precedent instruction in the 1st instruction register is finished, a following instruction in the 2nd instruction register is put in the 1st instruction register according to an IR state flag. Consequently, while the following instruction in the 1st instruction register is decoded, a next following instruction can be decoded by the 2nd register and at this time, the limitation of the following instruction decoding is held after the end of the precedent instruction decoding, so that decoding is performed even by the 1st instruction register which had been empty when conventional technique was applied, thus saving waste.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an instruction decoding device within an information processing device.

[Conventional technology]

As a conventional technique for decoding a plurality of instructions at the same time, there is a method called JP-A-56-7147R, ``Method of simultaneously executing multiple instructions''.

I will explain this below, but here.

The explanation will be based on the case where two instructions are decoded at the same time. -Generally N
The situation does not change in the slightest even when the commands are decoded simultaneously.

When decoding two instructions simultaneously, a t-th instruction register and a second instruction register are placed. In order to facilitate design, the following restrictions are imposed.

(Limited) When viewed at a certain time, the instruction in the first instruction register is always an instruction that precedes the instruction in the second instruction register.

(Limitation 2) When viewed at a certain point in time, it is absolutely impossible for the instruction in the second instruction register (successor instruction) to finish decoding before the instruction in the first instruction register (preceding instruction) has finished decoding. Not in.

[Problem to be solved by the invention]

In the case of the prior art, waste occurs when only the preceding instruction in the first instruction register finishes decoding and the subsequent instruction in the second instruction register does not finish decoding.

In other words, even though the first instruction register is empty after the decoding of the preceding instruction is completed, the subsequent instruction remains in the second instruction register. It cannot be deciphered by the instruction register.

The purpose of the present invention is to eliminate this waste.

[Means to solve the problem]

For this purpose, the instructions in the second instruction register are
A new means for sending the command to the instruction register is provided.

[Effect]

With this method, waste will be eliminated as follows.

That is, when only the preceding instruction in the first instruction register has been decoded, this means is used to place the subsequent instruction in the second instruction register into the first instruction register. Then, it becomes possible to decode the subsequent instruction in the second instruction register at the same time as decoding the subsequent instruction in the first instruction register, and even in this case, the above-mentioned restrictions are observed. In the prior art, decoding is performed even in the first instruction register, which was vacant, eliminating waste.

(Embodiment) Hereinafter, an embodiment of the present invention will be described by referring to FIGS. 1 to 4.

First, the overall configuration will be explained using FIG. 1.

100 to 106 are instruction buffers that hold prefetched instructions. It is assumed that four instruction buffers (IBI (1 to 4) each hold one instruction.

The details of the instruction prefetch control are not related to the description of this embodiment, so they will not be described.

116 is an aligner in which the instruction in IBR pointed to by IBRO' signal line 198 and its successor instruction are
XTIR signal line 118 and NHXTNE! It is output on the XT engineering H signal line 120.

122 and 124 are selectors, respectively SHLNH
wIHI signal line 182, St<LNt! IIIH2
Controlled by signal line 184.

IRI (130) and IR2 (132) are first and second instruction registers, respectively. II (2 signal lines 136,
Selector 122. Signal line 126 provides a path for passing the instructions in the second instruction register to the first instruction register.

138.140 is a decoder (instruction decoding wI),
142 and 144 are decode signals, DtICODE
The HND1 signal 146, DF, and CODBIEND2 signal 148 are signals indicating that the decoding of the instructions in IRI and IR2 has been completed, respectively.

IBHVAiLD(1-4)150.152.154
.

A status flag 156 corresponds to the instruction buffers IBRL to IBR4, respectively, and indicates whether an instruction exists in IBRI to IBR4.

1B)tO)'196 indicates the numbers 1-4 of the instruction buffers IBRI-4 in which the instruction to be stored in the next instruction register is located.

This status flag becomes "1" when an instruction is read ahead and stored in the instruction buffer, and becomes "0" when the instruction is read out from the instruction buffer and manually entered into the instruction register.

IRI)lBIADY172.1R21(SHIAD'/F/
4 are status flags indicating whether or not the instruction registers IRI and IR2 are instructions, respectively.

This status flag becomes "1" when the corresponding LBHVALiD is "11" and an instruction is read from the instruction buffer and stored in the instruction register, and becomes "0" when the decoding of the instruction in the instruction register is completed.

166 is an IBR/IR status update circuit;
LiD (1-4) and IHIRHADY 1828
1<ADY (1) The value is updated. 200 is I
This is a circuit for updating the BROP, and 180 is an instruction decoding completion determination circuit. 166.200 and 180 will be explained in detail next using FIGS. 2, 3, and 4vi4.

First, the function of the instruction decoding completion determination circuit 180 will be explained using the second example. The human input signals of this circuit are IRI and IR
IHII (HADY signal and IR2 lung ADY signal and IRI) indicating whether there is a command in 2.

The deciphering of IR2's command is finished! DECOD indicating whether or not
hE:NL)1 signal and LlhCODhEND2 signal. The output signals of this circuit are the ShLNM111R1 signal 182 and the Sl:LN signal that control selectors 122 and 124.
HILR2 ID branch 84° and NEEL) IR# signal 1
It is 86.

NEEL) IR#id indicates the number of instructions to be read next from the instruction buffer and stored in the instruction register. f'l
:El) IR#=2 indicates that the next two instructions are read from the instruction buffer and stored in the instruction register, and NE
ED IR#=1 indicates that the next l instruction is read from the instruction buffer and stored in the instruction register, and N
EEL) IR#=O indicates that the instruction will not be read from the instruction buffer and stored in the instruction register next time.

The instruction decoding completion determination circuit 180 controls the selectors 122 and 124 by functioning as shown in FIG.
EI) Place the required value on the IR# signal. Figure 2 is 1
Explain line by line.

Line 41 of FIG. 2 shows IRII (BIADY = tH2H
When HADY=O, that is, when there is no command in either iRl or lR2, at this time, NEEυ IR#=2
Then, two instructions are read from the instruction buffer and stored in the instruction register. 5hLNE111R1= NEXT
IR, which indicates that the IRI is capable of manually inputting commands on the NBI-XTIH signal. Also, SI:LNt<1
11 (2=NE<XTNhXTIN, which means that l
R2 has NHIXTNBIXTII (instruction to manually execute the commands on No. 41).

Line 43 of Figure 2 is 1) lit(HIADY=RobiC0
DIitfNDl=1.

11(21(21) indicates when EADY=O, that is, the decoding of the instruction in IBI is completed and there is no instruction in lR2.

Also at the time of cono, NEEυ I R# = 2, 5HLN
14Vl) 11=Nt! :XTII(, SbiLNI11
(2=N14XTNhiXTI)l, read two instructions from the instruction buffer in the same way as above, and transfer them to the IR.
Manually input I and lR2.

The 46th line in Figure 2 is 11(1)+1(ADY=IH21
(B ADY = D B COO Bibi NDl = D H COD North ND
When 2=1, that is, the decoding of both the instruction in IBI and the instruction in lR2 is completed.
ED IR#=2, 5ELNI41111(1=
NHXTIR, S)! LNE! VII (2=N14XT
NHXTIl(, and in the same way as above, reads two instructions from the instruction buffer and inputs them to IRI and lR2.

Line 42 of Figure 2 is 1)+1HHADY=1, D
I:C013141END1=0. IH2RHIADY=
At the time of O, that is, there is an instruction in lR1, but N reading has not finished, and there is no instruction in lRZ. At this time, Nil! :Since EDIR$=1, one instruction is read from the instruction buffer.514LN[(VIB2=
N1 (XTI) l note, read l instruction is lR
2 is done manually. The IRI instruction remains as it is since the decoding has not yet been completed.

Figure 2 (1) #4 line is 1 old 1 (14 ADY = 1) 12
1()<ADY=1.

1) I<C0DE! [ENDl = 1) When hcODE HiNro2 = 0, that is, there is an instruction in both IRI and lR2, but both have not finished decoding.
At this time, NEEDIR$=O, no instructions are read from the instruction buffer, and the instructions in IRI and lR2 remain as they are.

Line 45 of Figure A2 is IRI)lt<ADY=IR2HHIADY ~1) ECODEHIND1=1, DHC
When OD Baboon ND2=O, that is.

There are instructions in both xal and lR2, and the decoding of the IRI instruction has been completed, but the decoding of the lR2 instruction has finished! Indicates when not. At this time, since NEEI)IL#=ENG, one instruction is read from the instruction buffer, 514LNHVI)
11 = I R2 note, l R14: is l) + 2 command is manually input, and 514LNt<111H2=
Since Nl:XTIH, the read l instruction is manually input to lR2.

This concludes the explanation of the instruction decoding completion determination circuit.

FIG. 3 is a diagram illustrating the entire state update process between IBM/IR state updates. The power of this circuit is the NEEI) R# signal, the 1BHVALiD(1-4) signal, and the IBHOP signal. The output of this circuit is N14111 (old) IHAI)
Y signal and N11) t2HHADY signal and Nl! , VIB
) tVALiD(1~4”) 1ltlltl!ADY and 1R2) IEADY and IB according to the 0 human power which is the signal
Update HVALiD (L~4).

NEEI on line #1 in Figure 3) When IR#=O,
NhlllHIHHAl)Y=:NHVII2)+1:
ADY=1.

181) +14 ADY, If (2) 1 Bi ADY is “1
” (indicating that there is an instruction), and “
EllRVALiD (7) The number is set to ``0'' and remains in front of the ``None'' note, IBI (VALiD (1-4)).

This case corresponds to the case where no instruction was read from the instruction buffer, and therefore IHII(BIADV).

1R2) 1hADY remains rlJ (7) and 1B
It remains the same as before RVALiD (1 to 4).

NEEI on line #2 in Figure 3) When IR$=1,
Nh[I(II(?4ADY = Eng, NHVII(2
8V ADY = 1)IHVALiD(IHRO)')
, 11(114#!, Al)Y remains "1", and 1) 121(IBRO for BiALl\)'''r IBRVALiD(7) value of the number pointed to is entered manually.

Also, IBHVALiD pointed to by IBRO)' is rO
Become J.

This case corresponds to the case where one instruction is read from the instruction buffer pointed to by IBRQ)' and manually input to the instruction register.

When IR#=2,
NIwIHI)it(ADY = 1HHVALiD(
IBI(UP).

Nt<VIH2HhADY=IBHVALjD(181
(0)'+1)'? 'can be.

IRl) 1t: ADY is 1B) pointed to by 1BROP
The IVALiD (1) value was manually set to 11 (2H BiADY
is the next IB) IVALi pointed to by Ik3ROP.
The value of D is entered manually. Also, at the point pointed to by IBROP and at the next point (1) 1B) IVALiD is set to rO.

This case corresponds to the case where two instructions are read from the instruction buffer pointed to by IBRO' and the next instruction buffer and input into the instruction register.

Above is the IHR/1 shaku status update IL! End of 1st route theory 1st1.

Figure 4 is IBROP Sarazan-! 2 is a diagram illustrating the function of a path 200. FIG. The human power of this circuit is IBRO)'signal
DII (# signal and IBRVALiD (1 to 4) signals. The output is IBRO)" is the new value of N VIB
This is a HOP signal. FIG. 4 shows the difference ΔIBROP between IIIBROP and IBRO'.

In line #1 of FIG. 4, ΔIBROP=O, and IH
The ROP is not updated, which corresponds to when no instructions were read from the instruction buffer.

At #2h in Figure 4, ΔIBKO)”=iBHVAL
il) (IBHOP) If 1tlHVALiD pointed to by IBROP (1) is 1, IBROF is +1, and if it is 0, IBROP is not updated. This means that one instruction is read from the location pointed to by IBROP in the instruction buffer. Respond when needed.

#3 line of the fourth country is ΔIBRO)'=1B)IVAL
iD (IBROP) + IBRVALiD (iBRO
P+1), and if the sum of 113HVALil) at the location pointed to by IBROP and the next location is O, IBRO)' remains unchanged without being updated, and if the sum is 1, IBROP is +
1, and if the sum or 2, IBROP is increased by +2. This corresponds to when two instructions are read from the location pointed to by IBROP of the instruction buffer and the next location.

This concludes the explanation of the IBROP update circuit.

According to this embodiment, the decoding of the IRI instruction is completed, and the lR
If the decoding of the second instruction is not completed.

As seen in the explanation on line #5 in FIG. 2, the instruction of lR2 is input to the IRI, and the next instruction after that instruction is manually input to lR2 and decoded. Therefore, decoding is performed even in IRIs that are vacant in the conventional technology.

There is no more waste.

〔Effect of the invention〕

According to the present invention, when only the preceding instruction in the first instruction register has finished decoding, the subsequent instruction in the second instruction register is placed in the first instruction register, and the subsequent next instruction is placed in the second instruction register. Since it can be placed in the instruction register and decoded, the first instruction register, which was vacant in the prior art, can be used effectively, eliminating waste.

[Brief explanation of drawings]

Fig. 1 is an overall configuration diagram of the embodiment, Fig. 2 is a functional explanatory diagram of the instruction release termination path, Fig. 3 is a functional explanatory diagram of the IBM/IR status update circuit, and Fig. 4 is a functional explanatory diagram of the IHROP update circuit. It is an explanatory diagram. 100-106...instruction buffer, 130-132...
...Instruction register, 138-140...Decoder. 180...Instruction decoding completion determination circuit, 166...IB
R/IR status update circuit, 200...IBROP update circuit ? ~0-

Claims (1)

[Claims] 1, a first instruction register, and a second instruction register; and first and second decoding means for decoding the instructions in the first and second instruction registers, respectively; An instruction decoding device comprising means for sending a first instruction register to a first instruction register.