JPH036153A - Line driver circuit - Google Patents
Line driver circuitInfo
- Publication number
- JPH036153A JPH036153A JP14034389A JP14034389A JPH036153A JP H036153 A JPH036153 A JP H036153A JP 14034389 A JP14034389 A JP 14034389A JP 14034389 A JP14034389 A JP 14034389A JP H036153 A JPH036153 A JP H036153A
- Authority
- JP
- Japan
- Prior art keywords
- input
- waveform
- transformer
- generated
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 11
- 230000002159 abnormal effect Effects 0.000 claims abstract description 9
- 230000005540 biological transmission Effects 0.000 claims abstract description 3
- 229920006395 saturated elastomer Polymers 0.000 claims description 3
- 230000007423 decrease Effects 0.000 abstract description 2
- 230000002401 inhibitory effect Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 238000010276 construction Methods 0.000 description 2
- 230000007935 neutral effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Landscapes
- Dc Digital Transmission (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はライントライノく回路に関し、特Ｇこノくイボ
ーラ波形に代表される矩形波伝送を行なうディジタル回
線のライントライノ（回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a line trino circuit, and more specifically to a line trino circuit for a digital line that transmits rectangular waves such as the Ibora waveform.
従来、この種のライントライノく回路の異常入力に対す
る保護方式は、抵抗により流れる電流を常に一定のレベ
ル以下に制限する方式と、ヒユーズにより一定値以上の
電流が継続して流れたら回路をしゃ断する方式とがある
。Traditionally, the protection methods for this type of line inline circuit against abnormal input are two methods: one uses a resistor to limit the current flowing below a certain level, and the other uses a fuse to cut off the circuit if the current continues to flow above a certain value. There is a method to do this.
上述した従来のライントライノく保護方式Ｇこお１）て
、抵抗により電流を制限する方式では、抵抗て゛電力が
むだに消費されるという欠点があり、またヒユーズを用
いた方式では切れたヒユーズを交換しなければ再び回路
を動作させること力≦できな（Ｘという欠点がある。Among the conventional line line protection methods described above, the method that limits the current using a resistor has the disadvantage that power is wasted due to the resistor, and the method that uses a fuse has the disadvantage that the current is limited by a blown fuse. It is impossible to operate the circuit again unless the power is replaced (there is a drawback of X).
本発明の目的は上述した欠点を除去し、抵抗番こよる電
力の浪費とヒユーズ交換を排除したラインドライバ回路
を提供することにある。SUMMARY OF THE INVENTION It is an object of the present invention to provide a line driver circuit which eliminates the above-mentioned drawbacks and eliminates power consumption due to resistance and fuse replacement.
本発明の回路は、１次側からパルス幅ｔの矩形波列を入
力しこの入力による駆動電流によって駆動されて２次側
から所望の出力を得るトランスを用いたラインドライバ
回路において、充電電流の流通期間が前記駆動電流をｔ
時間以上確保できるように回路抵抗分を加味して設定し
た静電容量を有するコンデンサを前記トランスの一次側
に直列接続して正常入力を１次側から２次側へ伝送せし
めるとともに、異常入力時には前記コンデンサを飽和状
態に充電して駆動電流の発生を抑止し異常入力の伝送遮
断を行なう手段を備えて備えて構成される。The circuit of the present invention is a line driver circuit using a transformer that inputs a rectangular wave train with a pulse width t from the primary side and is driven by the drive current generated by this input to obtain a desired output from the secondary side. The flow period is t for the driving current.
A capacitor having a capacitance set by taking into account the circuit resistance is connected in series to the primary side of the transformer so that normal input can be transmitted from the primary side to the secondary side, and when an abnormal input occurs, The device is configured to include means for charging the capacitor to a saturated state to suppress generation of drive current and cut off transmission of abnormal input.
次に、図面を参照して本発明を説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明のラインドライバ回路の一実施例の回路
図を示し、中性点を一次側に有するトランス１と、トラ
ンス１の１次側の直流抵抗分としてのトランス抵抗分２
，３．１次側に直列接続したコンデンサ４，５を備えて
成り、なお第１図には入力端子７，８．９および出力端
子１０．１１を併記して示す。FIG. 1 shows a circuit diagram of an embodiment of the line driver circuit of the present invention, which includes a transformer 1 having a neutral point on the primary side, and a transformer resistance 2 as a DC resistance on the primary side of the transformer 1.
, 3. comprises capacitors 4, 5 connected in series on the primary side, and input terminals 7, 8.9 and output terminals 10.11 are also shown in FIG.
第２図は第１図の実施例の主要波形図であり、トランス
１の１次側の入力端子７，９からはそれぞれ第２図ａ、
ｃで示す入力波形が供給される。FIG. 2 is a main waveform diagram of the embodiment shown in FIG. 1.
An input waveform indicated by c is provided.
これら入力波形は、パルス幅ｔの矩形波列で、入力端子
８から供給される直流電圧ＶＣＣと接地レベルＧＮＤで
設定される値を有し、入力波形Ｃは入力波形ａの矩形波
の中間位置で発生する矩形波列で、この入力波形ａ、Ｃ
によって発生する駆動電流す、ｄによって駆動されたト
ランス１の２次側の出力端子１０．１１間には出力波形
ｅで示すバイポーラ波形を発生させている。These input waveforms are rectangular wave trains with a pulse width t, and have values set by the DC voltage VCC supplied from the input terminal 8 and the ground level GND, and the input waveform C is at an intermediate position of the rectangular wave of the input waveform a. This input waveform a, C is a rectangular wave train generated at
A bipolar waveform shown as an output waveform e is generated between the output terminals 10 and 11 on the secondary side of the transformer 1 driven by the drive currents S and d generated by the transformer 1.
正常時の入力波形ａ、ｃはそれぞれ、を秒以上ＧＮＤレ
ベルが継続することはなく、コンデンサ４．５の静電容
量は、入力による充電電流がトランス１を駆動するに必
要な駆動電流を少なくともｔ秒確保できるようにトラン
ス抵抗分２．３を含んでその時定数が決定される値とし
て設定される。The input waveforms a and c during normal operation do not remain at the GND level for more than a second, and the capacitance of the capacitor 4.5 is such that the charging current from the input can at least cover the drive current necessary to drive the transformer 1. The time constant is set to a determined value including the transformer resistance of 2.3 so as to ensure t seconds.
いま、第２図に示すように、入力波形ａに障害発生点６
で障害が発生し、入力端子７が継続的にＧＮＤレベルに
保持されると、トランス１に流れる駆動電流すはｔに比
して十分長い時間にわたって第２図すに示す如く徐徐に
減少していき、コンデンサ４はＶＣＣによって飽和状態
に充電され、駆動電流すは流れなくなり、入力端子７の
ＧＮＤレベルにおかれた影響はトランスの２次側には現
われず第２図ｅに示す如くなり、こうして異常入力によ
る影響発生は遮断、排除される。Now, as shown in Fig. 2, there is a failure point 6 in the input waveform a.
When a fault occurs and the input terminal 7 is continuously held at the GND level, the drive current flowing through the transformer 1 gradually decreases over a sufficiently long time compared to t, as shown in Figure 2. Then, the capacitor 4 is charged to a saturated state by VCC, the drive current stops flowing, and the influence of the GND level of the input terminal 7 does not appear on the secondary side of the transformer, as shown in Figure 2e. In this way, the influence caused by abnormal input is blocked and eliminated.
なお、第１図の実施例では、トランスｌの１次側を中性
点を有する２人力構成としたが、これを１人力構成とし
ても同様に実施しうろことは明らかである。In the embodiment shown in FIG. 1, the primary side of the transformer l has a two-man construction with a neutral point, but it is clear that this can also be implemented in the same manner as a one-man construction.
以上説明したように本発明によれば、コンデンサの充電
特性を利用することにより、障害時に駆動電流をしゃ断
できる簡素な構成のラインドライバ回路が実現できると
いう効果がある。As described above, according to the present invention, by utilizing the charging characteristics of a capacitor, it is possible to realize a line driver circuit with a simple configuration that can cut off the drive current in the event of a failure.
第１図は本発明のラインドライバ回路の一実施例を示す
回路図、第２図は第１図の実施例の主要波形図である。
１・・・トランス、２．３・・・トランス抵抗分、４゜
５・・・コンデンサ、６・・・障害発生点、７．８．９
・・・入力端子、１０．１１・・・出力端子、ａ・・・
入力波形、ｂ・・・駆動電流、Ｃ・・・入力波形、ｄ・
・・駆動電流、ｅ・・・出力波形。FIG. 1 is a circuit diagram showing one embodiment of the line driver circuit of the present invention, and FIG. 2 is a main waveform diagram of the embodiment of FIG. 1. 1...Transformer, 2.3...Transformer resistance, 4゜5...Capacitor, 6...Fault point, 7.8.9
...Input terminal, 10.11...Output terminal, a...
Input waveform, b... Drive current, C... Input waveform, d.
... Drive current, e... Output waveform.
Claims (1)
る駆動電流によって駆動されて２次側から所望の出力を
得るトランスを用いたラインドライバ回路において、 充電電流の流通期間が前記駆動電流をｔ時間以上確保で
きるように回路抵抗分を加味して設定した静電容量を有
するコンデンサを前記トランスの一次側に直列接続して
正常入力を１次側から２次側へ伝送せしめるとともに、
異常入力時には前記コンデンサを飽和状態に充電して駆
動電流の発生を抑止し異常入力の伝送遮断を行なう手段
を備えて成ることを特徴とするラインドライバ回路。[Claims] In a line driver circuit using a transformer that inputs a rectangular wave train with a pulse width t from the primary side and is driven by the drive current generated by this input to obtain a desired output from the secondary side, A capacitor having a capacitance set by taking into account the circuit resistance so that the driving current can be maintained for a period of time t or more is connected in series to the primary side of the transformer to transfer normal input from the primary side to the secondary side. In addition to transmitting to
1. A line driver circuit comprising means for charging the capacitor to a saturated state when an abnormal input occurs, suppressing generation of drive current, and cutting off transmission of the abnormal input.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14034389A JPH036153A (en) | 1989-06-01 | 1989-06-01 | Line driver circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14034389A JPH036153A (en) | 1989-06-01 | 1989-06-01 | Line driver circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH036153A true JPH036153A (en) | 1991-01-11 |
Family
ID=15266625
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14034389A Pending JPH036153A (en) | 1989-06-01 | 1989-06-01 | Line driver circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH036153A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4957874A (en) * | 1987-11-27 | 1990-09-18 | Nec Corporation | Self-aligned Bi-CMOS device having high operation speed and high integration density |
-
1989
- 1989-06-01 JP JP14034389A patent/JPH036153A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4957874A (en) * | 1987-11-27 | 1990-09-18 | Nec Corporation | Self-aligned Bi-CMOS device having high operation speed and high integration density |
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