JPS63194413A - Pulse signal deliver circuit - Google Patents

Pulse signal deliver circuit

Info

Publication number
JPS63194413A
JPS63194413A JP62027739A JP2773987A JPS63194413A JP S63194413 A JPS63194413 A JP S63194413A JP 62027739 A JP62027739 A JP 62027739A JP 2773987 A JP2773987 A JP 2773987A JP S63194413 A JPS63194413 A JP S63194413A
Authority
JP
Japan
Prior art keywords
output
variable resistor
transformer
circuit
diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62027739A
Other languages
Japanese (ja)
Inventor
Masatomi Hiraga
平賀 正富
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62027739A priority Critical patent/JPS63194413A/en
Publication of JPS63194413A publication Critical patent/JPS63194413A/en
Pending legal-status Critical Current

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  • Dc Digital Transmission (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To realize the compression of a circuit scale and the reduction of a price and to easily perform the successive and variable adjustment of the amplitude of an output pulse, by obtaining a pulse output from the secondary side output terminal of a transformer, by connecting the output of a logic IC to the anode of a first diode and the one end of a variable resistor, and connecting the other end of the variable resistor to the anode of a second diode. CONSTITUTION:A transistor 2 is turned ON when the logic IC6 is set at an 'H' level, and goes to an OFF state when it is set at an 'L' level, and to the primary side of the transformer 1, a collector voltage at respective state is inputted, and at the secondary side output, the output pulse to be sent to a transmission line appears. And potential V1 at a point B is increased when the value of the variable resistor 8 is set at a large value, then, the amplitude of the output pulse is decreased. Also, the potential is decreased when that of the variable resistor 8 is set at a small value, and also, the amplitude of the output pulse is increased. Thus, since the amplitude of the output pulse can be adjusted successively by adjusting the variable resistor 8, it is possible to make an ATT circuit being provided at the secondary side of the transformer in a conventional circuit unnecessary.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明はディジタル伝送システムにおけるパルス信号送
出回路、特にトランジスタのオン、オフによりトランス
を定電圧駆動することにより、伝送路にパルス信号を送
出するパルス信号送出口路に関する。
[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a pulse signal sending circuit in a digital transmission system, in particular, to send a pulse signal to a transmission line by driving a transformer at a constant voltage by turning on and off a transistor. It relates to a pulse signal output path.

(従来技術) 一般にディジタル伝送方式では、伝送路にパルス信号を
送出するパルス信号送出回路を組み込んでパルス信号振
幅及び占有率を一定の規格内に制限してパルス信号を送
出している。従来よく使用されている送出回路として、
第2図に例示する回路が知られており、トランス1の1
次側をトランジスタ2のオン、オフにより定電圧駆動し
、トランス1の2次側に伝送路の特性インピーダンスと
同一のインピーダンスを持った可変抵抗減衰器(以下、
ATTと称する)3を設け、ダイオード4.5、トラン
ジスタ2およびトランス1のバラツキによる送出パルス
振幅の変動を調整して一定の規格内のパルスを送出する
ようにしている。ここで6は一般の論理IC,7はダイ
オード4と接地間に設けた抵抗器である。
(Prior Art) Generally, in a digital transmission system, a pulse signal sending circuit for sending out a pulse signal is incorporated into a transmission path, and the pulse signal is sent out while limiting the pulse signal amplitude and occupancy within a certain standard. As a conventionally commonly used transmission circuit,
The circuit illustrated in FIG. 2 is known, and one of the transformers 1
The secondary side of the transformer 1 is driven at a constant voltage by turning on and off the transistor 2, and the secondary side of the transformer 1 is connected to a variable resistance attenuator (hereinafter referred to as
(referred to as ATT) 3 is provided, and fluctuations in the sending pulse amplitude due to variations in the diodes 4, 5, the transistor 2, and the transformer 1 are adjusted to send out pulses within a certain standard. Here, 6 is a general logic IC, and 7 is a resistor provided between the diode 4 and ground.

(発明が解決しようとする問題点) ム 第2図に示す従来回路では、22力回路素子のバラツキ
によるパルス振幅の変動を前記ATT3にて調整してい
るため、以下のような問題が生じる。
(Problems to be Solved by the Invention) In the conventional circuit shown in FIG. 2, since fluctuations in pulse amplitude due to variations in the 22-power circuit elements are adjusted by the ATT 3, the following problems occur.

第1に、前記ATTは伝送路の特性インピーダンスと同
一のインピーダンスを有する定抵抗回路でなければなら
ないため、回路構成が通常の抵抗分圧等の簡単な回路と
違って、例えばT型又はπ型のように複雑になってしま
い、回路規模が大きくなり、価格も高価な物となってし
まう。第2に、前記のATTでは減衰量を連続的に変化
させることは回路構成上不可能で、通常は数ステップの
切替選択方法をとっているため、減衰量がステップ式に
変化し、出力パルスを一定規格内に正確に調整すること
ができず、さらに正確に調整する時には可変ステップ数
をさらに大きくしなければならず、実装規模がかなり大
きなものとなり、ATT自体がかなり高価な物となる。
First, since the ATT must be a constant resistance circuit with the same impedance as the characteristic impedance of the transmission line, the circuit configuration is different from a simple circuit such as a normal resistance voltage divider, for example, a T-type or π-type. The circuit becomes complicated, the circuit scale becomes large, and the price becomes expensive. Second, in the above-mentioned ATT, it is impossible to change the attenuation amount continuously due to the circuit configuration, and the attenuation amount changes in a stepwise manner, since the switching selection method usually takes several steps, and the output pulse cannot be accurately adjusted within a certain standard, and when adjusting more accurately, the number of variable steps must be increased, resulting in a fairly large implementation scale and making the ATT itself quite expensive.

本発明は上述の第1、第2のような問題点をなくし、回
路規模が従来より小さく、さらに従来より安価で、出力
パルス振幅を連続可変調整することができるパルス信号
送出回路を提供することにある。
It is an object of the present invention to provide a pulse signal sending circuit which eliminates the first and second problems mentioned above, has a smaller circuit scale than the conventional one, is cheaper than the conventional one, and is capable of continuously variable adjustment of the output pulse amplitude. It is in.

(問題点を解決するための手段) 本発明のパルス信号送出回路は、論理ICの出力を第1
のダイオードのアノードと可変抵抗器の一端に接続し、
前記第1のダイオードのカソードを抵抗の一端とトラン
ジスタのベースに接続し、前記抵抗の他端と前記トラン
ジスタのエミッタを接地し、前記可変抵抗器の他端を第
2のダイオードのアノードに接続し、該第2のダイオー
ドのカソードを前記トランジスタのコレクタに接続する
と共にトランスの1次側入力端に接続し、該トランスの
2次側出力端よりパルス出力を得るようにしたものであ
る。
(Means for Solving the Problems) The pulse signal sending circuit of the present invention transmits the output of the logic IC to the first
Connect the anode of the diode and one end of the variable resistor,
A cathode of the first diode is connected to one end of a resistor and a base of a transistor, the other end of the resistor and an emitter of the transistor are grounded, and the other end of the variable resistor is connected to an anode of a second diode. The cathode of the second diode is connected to the collector of the transistor and also to the primary input terminal of the transformer, so that a pulse output is obtained from the secondary output terminal of the transformer.

(実施例) 次に、本発明を図面を参照して実施例につき説明する。(Example) Next, the present invention will be explained by way of example with reference to the drawings.

第1図は本発明の実施例によるパルス信号送出回路のブ
ロック図である。この実施例では、論理IC6の出力を
第1のダイオード4のアノードと可変抵抗器8の一端に
接続し、前記第1のダイオード4のカソードを抵抗7の
一端とトランジスタ2のベースに接続し、前記抵抗7の
他端および前記トランジスタ2のエミッタをそれぞれ接
地し、可変抵抗器8の他端を第2のダイオード5のアノ
ードに接続し、該第2のダイオード5のカソードヲ前記
トランジスタ2のコレクタに接続すると共にトランス1
の1次側入力端に接続しである。
FIG. 1 is a block diagram of a pulse signal sending circuit according to an embodiment of the present invention. In this embodiment, the output of the logic IC 6 is connected to the anode of the first diode 4 and one end of the variable resistor 8, the cathode of the first diode 4 is connected to one end of the resistor 7 and the base of the transistor 2, The other end of the resistor 7 and the emitter of the transistor 2 are grounded, the other end of the variable resistor 8 is connected to the anode of the second diode 5, and the cathode of the second diode 5 is connected to the collector of the transistor 2. Connect and transformer 1
It is connected to the primary side input terminal of.

このような構成になる本回路では、論理IC6が#H#
レベルの時トランジスタ2はオンし、“L”レベルの時
はオフ状態となり、トランス1の1次側人力にはそれぞ
れの状態の時のコレクタ電圧が人力する、いわゆるトラ
ンス1の定電圧駆動形式になっており、トランス1の2
次側出力に伝送路へ送出するための出力パルスが現われ
る。
In this circuit with such a configuration, the logic IC6 is #H#
Transistor 2 is turned on when the level is low, and turned off when it is low, and the collector voltage at each state is applied to the primary side of the transformer 1, which is the so-called constant voltage drive type of the transformer 1. and transformer 1 and 2
An output pulse for sending out to the transmission line appears at the next output.

トランジスタ2がオフの時のB点の電位V+は、トラン
ス供給電圧(vcc)に等しく、トランジスタ2がオン
のときのV+はA点〜B点間を流れる電流工 による降
下電圧即ち(rxRV t 十v o 2 、ここでV
D2はD2の降下電圧)でクランプされる。
The potential V+ at point B when transistor 2 is off is equal to the transformer supply voltage (vcc), and when transistor 2 is on, V+ is equal to the voltage drop due to the current flowing between points A and B, that is, (rxRV t v o 2 , where V
D2 is clamped at the voltage drop of D2).

即ち可変抵抗器8が大なる時はVlは大きくなり、出力
パルス振幅は小さくなる。又可変抵抗器8が小なる時は
Vlが小さくなると共に出力パルス振幅は大きくなる。
That is, when the variable resistor 8 becomes large, Vl becomes large and the output pulse amplitude becomes small. Further, when the variable resistor 8 becomes small, Vl becomes small and the output pulse amplitude becomes large.

こうして可変抵抗器8を調整することにより、出力パル
ス振幅を連続的に調整できるために、トランス2次側に
従来設けていたATT回路は不用となる。
By adjusting the variable resistor 8 in this manner, the output pulse amplitude can be adjusted continuously, so that the ATT circuit conventionally provided on the secondary side of the transformer becomes unnecessary.

(発明の効果) 以上説明したように本発明によれば、従来高価で実装規
模の大きいATTを使用し、完全な振幅調整が不可能で
あったパルス信号送出回路を、安価で回路規模が小さく
、しかも完全な振幅調整が可能なパルス信号送出回路と
して提供できる効果がある。
(Effects of the Invention) As explained above, according to the present invention, the pulse signal sending circuit, which conventionally used an expensive and large-scale ATT and was unable to perform complete amplitude adjustment, can be replaced with an inexpensive and small-scale circuit. Moreover, the present invention has the advantage that it can be provided as a pulse signal sending circuit that allows complete amplitude adjustment.

【図面の簡単な説明】 第1図は本発明の実施例によるパルス信号送出回路を示
す図、第2図は従来のパルス信号送出回路を示す図であ
る。 1・・・トランス、2・・・トランジスタ、3・・・可
変抵抗減衰器(ATT)、 4・・・第1のダイオード、5・・・第2のダイオード
、6・・・集積論理IC17・・・抵抗、8・・・可変
抵抗器。 代理人  弁理士  染 川 利 吉 第1図 第2し VC[
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a pulse signal sending circuit according to an embodiment of the present invention, and FIG. 2 is a diagram showing a conventional pulse signal sending circuit. DESCRIPTION OF SYMBOLS 1... Transformer, 2... Transistor, 3... Variable resistance attenuator (ATT), 4... First diode, 5... Second diode, 6... Integrated logic IC17. ...Resistance, 8...Variable resistor. Agent Patent Attorney Toshiyoshi Somekawa Figure 1 Figure 2 VC [

Claims (1)

【特許請求の範囲】[Claims] 論理ICの出力を第1のダイオードのアノードと可変抵
抗器の一端に接続し、前記第1のダイオードのカソード
を抵抗の一端とトランジスタのベースに接続し、前記抵
抗の他端および前記トランジスタのエミッタをそれぞれ
接地し、前記可変抵抗器の他端を第2のダイオードのア
ノードに接続し、前記第2のダイオードのカソードを前
記トランジスタのコレクタに接続すると共にトランスの
1次側入力端に接続し、該トランスの2次側出力端より
パルス出力を得ることを特徴とするパルス信号送出回路
The output of the logic IC is connected to the anode of the first diode and one end of the variable resistor, the cathode of the first diode is connected to one end of the resistor and the base of the transistor, and the other end of the resistor and the emitter of the transistor are connected. are respectively grounded, the other end of the variable resistor is connected to the anode of a second diode, the cathode of the second diode is connected to the collector of the transistor and to the primary input end of the transformer, A pulse signal sending circuit characterized in that a pulse output is obtained from a secondary output end of the transformer.
JP62027739A 1987-02-09 1987-02-09 Pulse signal deliver circuit Pending JPS63194413A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62027739A JPS63194413A (en) 1987-02-09 1987-02-09 Pulse signal deliver circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62027739A JPS63194413A (en) 1987-02-09 1987-02-09 Pulse signal deliver circuit

Publications (1)

Publication Number Publication Date
JPS63194413A true JPS63194413A (en) 1988-08-11

Family

ID=12229401

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62027739A Pending JPS63194413A (en) 1987-02-09 1987-02-09 Pulse signal deliver circuit

Country Status (1)

Country Link
JP (1) JPS63194413A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5147510A (en) * 1990-02-09 1992-09-15 Sumitomo Wiring Systems, Ltd. Flat multicore wire and method of forming the same wire
US5179779A (en) * 1990-07-13 1993-01-19 Sumitomo Wiring Systems Ltd. Method of forming flat multicore wire
US5206462A (en) * 1990-07-13 1993-04-27 Sumitomo Wiring System Ltd. Flat multicore wire and method of forming the same wire

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5665527A (en) * 1979-11-01 1981-06-03 Fujitsu Denso Ltd Transistor switching circuit of class-a operation

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5665527A (en) * 1979-11-01 1981-06-03 Fujitsu Denso Ltd Transistor switching circuit of class-a operation

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5147510A (en) * 1990-02-09 1992-09-15 Sumitomo Wiring Systems, Ltd. Flat multicore wire and method of forming the same wire
US5179779A (en) * 1990-07-13 1993-01-19 Sumitomo Wiring Systems Ltd. Method of forming flat multicore wire
US5206462A (en) * 1990-07-13 1993-04-27 Sumitomo Wiring System Ltd. Flat multicore wire and method of forming the same wire

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